source: trunk/packages/xen-common/xen-common/xen/include/asm-x86/cpufeature.h @ 34

Last change on this file since 34 was 34, checked in by hartmans, 17 years ago

Add xen and xen-common
File size: 7.0 KB
Line 
1/*
2 * cpufeature.h
3 *
4 * Defines x86 CPU feature bits
5 */
6
7#ifndef __ASM_I386_CPUFEATURE_H
8#define __ASM_I386_CPUFEATURE_H
9
10#include <xen/bitops.h>
11
12#define NCAPINTS        7       /* N 32-bit words worth of info */
13
14/* Intel-defined CPU features, CPUID level 0x00000001 (edx), word 0 */
15#define X86_FEATURE_FPU         (0*32+ 0) /* Onboard FPU */
16#define X86_FEATURE_VME         (0*32+ 1) /* Virtual Mode Extensions */
17#define X86_FEATURE_DE          (0*32+ 2) /* Debugging Extensions */
18#define X86_FEATURE_PSE         (0*32+ 3) /* Page Size Extensions */
19#define X86_FEATURE_TSC         (0*32+ 4) /* Time Stamp Counter */
20#define X86_FEATURE_MSR         (0*32+ 5) /* Model-Specific Registers, RDMSR, WRMSR */
21#define X86_FEATURE_PAE         (0*32+ 6) /* Physical Address Extensions */
22#define X86_FEATURE_MCE         (0*32+ 7) /* Machine Check Architecture */
23#define X86_FEATURE_CX8         (0*32+ 8) /* CMPXCHG8 instruction */
24#define X86_FEATURE_APIC        (0*32+ 9) /* Onboard APIC */
25#define X86_FEATURE_SEP         (0*32+11) /* SYSENTER/SYSEXIT */
26#define X86_FEATURE_MTRR        (0*32+12) /* Memory Type Range Registers */
27#define X86_FEATURE_PGE         (0*32+13) /* Page Global Enable */
28#define X86_FEATURE_MCA         (0*32+14) /* Machine Check Architecture */
29#define X86_FEATURE_CMOV        (0*32+15) /* CMOV instruction (FCMOVCC and FCOMI too if FPU present) */
30#define X86_FEATURE_PAT         (0*32+16) /* Page Attribute Table */
31#define X86_FEATURE_PSE36       (0*32+17) /* 36-bit PSEs */
32#define X86_FEATURE_PN          (0*32+18) /* Processor serial number */
33#define X86_FEATURE_CLFLSH      (0*32+19) /* Supports the CLFLUSH instruction */
34#define X86_FEATURE_DTES        (0*32+21) /* Debug Trace Store */
35#define X86_FEATURE_ACPI        (0*32+22) /* ACPI via MSR */
36#define X86_FEATURE_MMX         (0*32+23) /* Multimedia Extensions */
37#define X86_FEATURE_FXSR        (0*32+24) /* FXSAVE and FXRSTOR instructions (fast save and restore */
38                                          /* of FPU context), and CR4.OSFXSR available */
39#define X86_FEATURE_XMM         (0*32+25) /* Streaming SIMD Extensions */
40#define X86_FEATURE_XMM2        (0*32+26) /* Streaming SIMD Extensions-2 */
41#define X86_FEATURE_SELFSNOOP   (0*32+27) /* CPU self snoop */
42#define X86_FEATURE_HT          (0*32+28) /* Hyper-Threading */
43#define X86_FEATURE_ACC         (0*32+29) /* Automatic clock control */
44#define X86_FEATURE_IA64        (0*32+30) /* IA-64 processor */
45
46/* AMD-defined CPU features, CPUID level 0x80000001, word 1 */
47/* Don't duplicate feature flags which are redundant with Intel! */
48#define X86_FEATURE_SYSCALL     (1*32+11) /* SYSCALL/SYSRET */
49#define X86_FEATURE_MP          (1*32+19) /* MP Capable. */
50#define X86_FEATURE_NX          (1*32+20) /* Execute Disable */
51#define X86_FEATURE_MMXEXT      (1*32+22) /* AMD MMX extensions */
52#define X86_FEATURE_RDTSCP      (1*32+27) /* RDTSCP */
53#define X86_FEATURE_LM          (1*32+29) /* Long Mode (x86-64) */
54#define X86_FEATURE_3DNOWEXT    (1*32+30) /* AMD 3DNow! extensions */
55#define X86_FEATURE_3DNOW       (1*32+31) /* 3DNow! */
56
57/* Transmeta-defined CPU features, CPUID level 0x80860001, word 2 */
58#define X86_FEATURE_RECOVERY    (2*32+ 0) /* CPU in recovery mode */
59#define X86_FEATURE_LONGRUN     (2*32+ 1) /* Longrun power control */
60#define X86_FEATURE_LRTI        (2*32+ 3) /* LongRun table interface */
61
62/* Other features, Linux-defined mapping, word 3 */
63/* This range is used for feature bits which conflict or are synthesized */
64#define X86_FEATURE_CXMMX       (3*32+ 0) /* Cyrix MMX extensions */
65#define X86_FEATURE_K6_MTRR     (3*32+ 1) /* AMD K6 nonstandard MTRRs */
66#define X86_FEATURE_CYRIX_ARR   (3*32+ 2) /* Cyrix ARRs (= MTRRs) */
67#define X86_FEATURE_CENTAUR_MCR (3*32+ 3) /* Centaur MCRs (= MTRRs) */
68/* cpu types for specific tunings: */
69#define X86_FEATURE_K8          (3*32+ 4) /* Opteron, Athlon64 */
70#define X86_FEATURE_K7          (3*32+ 5) /* Athlon */
71#define X86_FEATURE_P3          (3*32+ 6) /* P3 */
72#define X86_FEATURE_P4          (3*32+ 7) /* P4 */
73#define X86_FEATURE_CONSTANT_TSC (3*32+ 8) /* TSC ticks at a constant rate */
74
75/* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */
76#define X86_FEATURE_XMM3        (4*32+ 0) /* Streaming SIMD Extensions-3 */
77#define X86_FEATURE_MWAIT       (4*32+ 3) /* Monitor/Mwait support */
78#define X86_FEATURE_DSCPL       (4*32+ 4) /* CPL Qualified Debug Store */
79#define X86_FEATURE_VMXE        (4*32+ 5) /* Virtual Machine Extensions */
80#define X86_FEATURE_EST         (4*32+ 7) /* Enhanced SpeedStep */
81#define X86_FEATURE_TM2         (4*32+ 8) /* Thermal Monitor 2 */
82#define X86_FEATURE_CID         (4*32+10) /* Context ID */
83#define X86_FEATURE_CX16        (4*32+13) /* CMPXCHG16B */
84#define X86_FEATURE_XTPR        (4*32+14) /* Send Task Priority Messages */
85
86/* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, word 5 */
87#define X86_FEATURE_XSTORE      (5*32+ 2) /* on-CPU RNG present (xstore insn) */
88#define X86_FEATURE_XSTORE_EN   (5*32+ 3) /* on-CPU RNG enabled */
89#define X86_FEATURE_XCRYPT      (5*32+ 6) /* on-CPU crypto (xcrypt insn) */
90#define X86_FEATURE_XCRYPT_EN   (5*32+ 7) /* on-CPU crypto enabled */
91
92/* More extended AMD flags: CPUID level 0x80000001, ecx, word 6 */
93#define X86_FEATURE_LAHF_LM     (6*32+ 0) /* LAHF/SAHF in long mode */
94#define X86_FEATURE_CMP_LEGACY  (6*32+ 1) /* If yes HyperThreading not valid */
95#define X86_FEATURE_SVME        (6*32+ 2) /* Secure Virtual Machine */
96#define X86_FEATURE_FFXSR       (6*32+25) /* FFXSR instruction optimizations */
97
98#define cpu_has(c, bit)         test_bit(bit, (c)->x86_capability)
99#define boot_cpu_has(bit)       test_bit(bit, boot_cpu_data.x86_capability)
100
101#ifdef __i386__
102#define cpu_has_vme             boot_cpu_has(X86_FEATURE_VME)
103#define cpu_has_de              boot_cpu_has(X86_FEATURE_DE)
104#define cpu_has_pse             boot_cpu_has(X86_FEATURE_PSE)
105#define cpu_has_tsc             boot_cpu_has(X86_FEATURE_TSC)
106#define cpu_has_pae             boot_cpu_has(X86_FEATURE_PAE)
107#define cpu_has_pge             boot_cpu_has(X86_FEATURE_PGE)
108#define cpu_has_apic            boot_cpu_has(X86_FEATURE_APIC)
109#define cpu_has_sep             boot_cpu_has(X86_FEATURE_SEP)
110#define cpu_has_mtrr            boot_cpu_has(X86_FEATURE_MTRR)
111#define cpu_has_mmx             boot_cpu_has(X86_FEATURE_MMX)
112#define cpu_has_fxsr            boot_cpu_has(X86_FEATURE_FXSR)
113#define cpu_has_xmm             boot_cpu_has(X86_FEATURE_XMM)
114#define cpu_has_xmm2            boot_cpu_has(X86_FEATURE_XMM2)
115#define cpu_has_xmm3            boot_cpu_has(X86_FEATURE_XMM3)
116#define cpu_has_ht              boot_cpu_has(X86_FEATURE_HT)
117#define cpu_has_mp              boot_cpu_has(X86_FEATURE_MP)
118#define cpu_has_nx              boot_cpu_has(X86_FEATURE_NX)
119#define cpu_has_k6_mtrr         boot_cpu_has(X86_FEATURE_K6_MTRR)
120#define cpu_has_cyrix_arr       boot_cpu_has(X86_FEATURE_CYRIX_ARR)
121#define cpu_has_centaur_mcr     boot_cpu_has(X86_FEATURE_CENTAUR_MCR)
122#define cpu_has_clflush         boot_cpu_has(X86_FEATURE_CLFLSH)
123#else /* __x86_64__ */
124#define cpu_has_vme             0
125#define cpu_has_de              1
126#define cpu_has_pse             1
127#define cpu_has_tsc             1
128#define cpu_has_pae             1
129#define cpu_has_pge             1
130#define cpu_has_apic            boot_cpu_has(X86_FEATURE_APIC)
131#define cpu_has_sep             0
132#define cpu_has_mtrr            1
133#define cpu_has_mmx             1
134#define cpu_has_fxsr            1
135#define cpu_has_xmm             1
136#define cpu_has_xmm2            1
137#define cpu_has_xmm3            boot_cpu_has(X86_FEATURE_XMM3)
138#define cpu_has_ht              boot_cpu_has(X86_FEATURE_HT)
139#define cpu_has_mp              1
140#define cpu_has_nx              boot_cpu_has(X86_FEATURE_NX)
141#define cpu_has_k6_mtrr         0
142#define cpu_has_cyrix_arr       0
143#define cpu_has_centaur_mcr     0
144#define cpu_has_clflush         boot_cpu_has(X86_FEATURE_CLFLSH)
145#endif
146
147#endif /* __ASM_I386_CPUFEATURE_H */
148
149/*
150 * Local Variables:
151 * mode:c
152 * comment-column:42
153 * End:
154 */
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