| 1 | #ifndef __ASM_APICDEF_H |
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| 2 | #define __ASM_APICDEF_H |
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| 3 | |
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| 4 | #define APIC_DEFAULT_PHYS_BASE 0xfee00000 |
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| 5 | |
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| 6 | #define APIC_ID 0x20 |
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| 7 | #define APIC_ID_MASK (0xFFu<<24) |
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| 8 | #define GET_APIC_ID(x) (((x)>>24)&0xFFu) |
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| 9 | #define SET_APIC_ID(x) (((x)<<24)) |
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| 10 | #define APIC_LVR 0x30 |
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| 11 | #define APIC_LVR_MASK 0xFF00FF |
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| 12 | #define GET_APIC_VERSION(x) ((x)&0xFF) |
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| 13 | #define GET_APIC_MAXLVT(x) (((x)>>16)&0xFF) |
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| 14 | #define APIC_INTEGRATED(x) ((x)&0xF0) |
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| 15 | #define APIC_XAPIC(x) ((x) >= 0x14) |
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| 16 | #define APIC_TASKPRI 0x80 |
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| 17 | #define APIC_TPRI_MASK 0xFF |
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| 18 | #define APIC_ARBPRI 0x90 |
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| 19 | #define APIC_ARBPRI_MASK 0xFF |
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| 20 | #define APIC_PROCPRI 0xA0 |
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| 21 | #define APIC_EOI 0xB0 |
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| 22 | #define APIC_EIO_ACK 0x0 |
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| 23 | #define APIC_RRR 0xC0 |
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| 24 | #define APIC_LDR 0xD0 |
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| 25 | #define APIC_LDR_MASK (0xFF<<24) |
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| 26 | #define GET_APIC_LOGICAL_ID(x) (((x)>>24)&0xFF) |
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| 27 | #define SET_APIC_LOGICAL_ID(x) (((x)<<24)) |
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| 28 | #define APIC_ALL_CPUS 0xFF |
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| 29 | #define APIC_DFR 0xE0 |
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| 30 | #define APIC_DFR_CLUSTER 0x0FFFFFFFul |
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| 31 | #define APIC_DFR_FLAT 0xFFFFFFFFul |
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| 32 | #define APIC_SPIV 0xF0 |
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| 33 | #define APIC_SPIV_FOCUS_DISABLED (1<<9) |
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| 34 | #define APIC_SPIV_APIC_ENABLED (1<<8) |
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| 35 | #define APIC_ISR 0x100 |
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| 36 | #define APIC_TMR 0x180 |
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| 37 | #define APIC_IRR 0x200 |
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| 38 | #define APIC_ESR 0x280 |
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| 39 | #define APIC_ESR_SEND_CS 0x00001 |
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| 40 | #define APIC_ESR_RECV_CS 0x00002 |
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| 41 | #define APIC_ESR_SEND_ACC 0x00004 |
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| 42 | #define APIC_ESR_RECV_ACC 0x00008 |
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| 43 | #define APIC_ESR_SENDILL 0x00020 |
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| 44 | #define APIC_ESR_RECVILL 0x00040 |
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| 45 | #define APIC_ESR_ILLREGA 0x00080 |
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| 46 | #define APIC_ICR 0x300 |
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| 47 | #define APIC_DEST_SELF 0x40000 |
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| 48 | #define APIC_DEST_ALLINC 0x80000 |
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| 49 | #define APIC_DEST_ALLBUT 0xC0000 |
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| 50 | #define APIC_ICR_RR_MASK 0x30000 |
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| 51 | #define APIC_ICR_RR_INVALID 0x00000 |
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| 52 | #define APIC_ICR_RR_INPROG 0x10000 |
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| 53 | #define APIC_ICR_RR_VALID 0x20000 |
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| 54 | #define APIC_INT_LEVELTRIG 0x08000 |
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| 55 | #define APIC_INT_ASSERT 0x04000 |
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| 56 | #define APIC_ICR_BUSY 0x01000 |
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| 57 | #define APIC_DEST_LOGICAL 0x00800 |
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| 58 | #define APIC_DEST_PHYSICAL 0x00000 |
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| 59 | #define APIC_DM_FIXED 0x00000 |
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| 60 | #define APIC_DM_LOWEST 0x00100 |
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| 61 | #define APIC_DM_SMI 0x00200 |
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| 62 | #define APIC_DM_REMRD 0x00300 |
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| 63 | #define APIC_DM_NMI 0x00400 |
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| 64 | #define APIC_DM_INIT 0x00500 |
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| 65 | #define APIC_DM_STARTUP 0x00600 |
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| 66 | #define APIC_DM_EXTINT 0x00700 |
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| 67 | #define APIC_VECTOR_MASK 0x000FF |
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| 68 | #define APIC_ICR2 0x310 |
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| 69 | #define GET_APIC_DEST_FIELD(x) (((x)>>24)&0xFF) |
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| 70 | #define SET_APIC_DEST_FIELD(x) ((x)<<24) |
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| 71 | #define APIC_LVTT 0x320 |
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| 72 | #define APIC_LVTTHMR 0x330 |
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| 73 | #define APIC_LVTPC 0x340 |
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| 74 | #define APIC_LVT0 0x350 |
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| 75 | #define APIC_LVT_TIMER_BASE_MASK (0x3<<18) |
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| 76 | #define GET_APIC_TIMER_BASE(x) (((x)>>18)&0x3) |
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| 77 | #define SET_APIC_TIMER_BASE(x) (((x)<<18)) |
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| 78 | #define APIC_TIMER_BASE_CLKIN 0x0 |
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| 79 | #define APIC_TIMER_BASE_TMBASE 0x1 |
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| 80 | #define APIC_TIMER_BASE_DIV 0x2 |
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| 81 | #define APIC_LVT_TIMER_PERIODIC (1<<17) |
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| 82 | #define APIC_LVT_MASKED (1<<16) |
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| 83 | #define APIC_LVT_LEVEL_TRIGGER (1<<15) |
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| 84 | #define APIC_LVT_REMOTE_IRR (1<<14) |
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| 85 | #define APIC_INPUT_POLARITY (1<<13) |
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| 86 | #define APIC_SEND_PENDING (1<<12) |
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| 87 | #define APIC_MODE_MASK 0x700 |
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| 88 | #define GET_APIC_DELIVERY_MODE(x) (((x)>>8)&0x7) |
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| 89 | #define SET_APIC_DELIVERY_MODE(x,y) (((x)&~0x700)|((y)<<8)) |
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| 90 | #define APIC_MODE_FIXED 0x0 |
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| 91 | #define APIC_MODE_NMI 0x4 |
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| 92 | #define APIC_MODE_EXTINT 0x7 |
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| 93 | #define APIC_LVT1 0x360 |
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| 94 | #define APIC_LVTERR 0x370 |
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| 95 | #define APIC_TMICT 0x380 |
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| 96 | #define APIC_TMCCT 0x390 |
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| 97 | #define APIC_TDCR 0x3E0 |
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| 98 | #define APIC_TDR_DIV_TMBASE (1<<2) |
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| 99 | #define APIC_TDR_DIV_1 0xB |
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| 100 | #define APIC_TDR_DIV_2 0x0 |
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| 101 | #define APIC_TDR_DIV_4 0x1 |
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| 102 | #define APIC_TDR_DIV_8 0x2 |
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| 103 | #define APIC_TDR_DIV_16 0x3 |
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| 104 | #define APIC_TDR_DIV_32 0x8 |
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| 105 | #define APIC_TDR_DIV_64 0x9 |
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| 106 | #define APIC_TDR_DIV_128 0xA |
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| 107 | |
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| 108 | #endif |
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