| 1 | /* |
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| 2 | * This program is free software; you can redistribute it and/or modify |
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| 3 | * it under the terms of the GNU General Public License as published by |
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| 4 | * the Free Software Foundation; either version 2 of the License, or |
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| 5 | * (at your option) any later version. |
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| 6 | * |
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| 7 | * This program is distributed in the hope that it will be useful, |
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| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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| 10 | * GNU General Public License for more details. |
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| 11 | * |
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| 12 | * You should have received a copy of the GNU General Public License |
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| 13 | * along with this program; if not, write to the Free Software |
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| 14 | * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. |
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| 15 | * |
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| 16 | * Copyright (C) IBM Corp. 2005 |
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| 17 | * |
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| 18 | * Authors: Jimi Xenidis <jimix@watson.ibm.com> |
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| 19 | */ |
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| 20 | |
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| 21 | #ifndef _POWERPC_MSR_H |
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| 22 | #define _POWERPC_MSR_H |
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| 23 | |
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| 24 | #ifdef __ASSEMBLY__ |
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| 25 | #define ULL(x) x |
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| 26 | #else |
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| 27 | #define ULL(x) x ## ULL |
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| 28 | #endif |
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| 29 | |
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| 30 | /* Flags in MSR: */ |
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| 31 | #define MSR_SF ULL(0x8000000000000000) |
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| 32 | #define MSR_TA ULL(0x4000000000000000) |
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| 33 | #define MSR_ISF ULL(0x2000000000000000) |
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| 34 | #define MSR_HV ULL(0x1000000000000000) |
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| 35 | #define MSR_VMX ULL(0x0000000002000000) |
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| 36 | #define MSR_MER ULL(0x0000000000200000) |
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| 37 | #define MSR_POW ULL(0x0000000000040000) |
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| 38 | #define MSR_ILE ULL(0x0000000000010000) |
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| 39 | #define MSR_EE ULL(0x0000000000008000) |
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| 40 | #define MSR_PR ULL(0x0000000000004000) |
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| 41 | #define MSR_FP ULL(0x0000000000002000) |
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| 42 | #define MSR_ME ULL(0x0000000000001000) |
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| 43 | #define MSR_FE0 ULL(0x0000000000000800) |
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| 44 | #define MSR_SE ULL(0x0000000000000400) |
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| 45 | #define MSR_BE ULL(0x0000000000000200) |
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| 46 | #define MSR_FE1 ULL(0x0000000000000100) |
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| 47 | #define MSR_IP ULL(0x0000000000000040) |
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| 48 | #define MSR_IR ULL(0x0000000000000020) |
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| 49 | #define MSR_DR ULL(0x0000000000000010) |
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| 50 | #define MSR_PMM ULL(0x0000000000000004) |
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| 51 | #define MSR_RI ULL(0x0000000000000002) |
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| 52 | #define MSR_LE ULL(0x0000000000000001) |
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| 53 | |
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| 54 | /* MSR bits set on the systemsim simulator */ |
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| 55 | #define MSR_SIM ULL(0x0000000020000000) |
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| 56 | #define MSR_SYSTEMSIM ULL(0x0000000010000000) |
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| 57 | |
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| 58 | /* On a trap, srr1's copy of msr defines some bits as follows: */ |
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| 59 | #define MSR_TRAP_FE ULL(0x0000000000100000) /* Floating Point Exception */ |
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| 60 | #define MSR_TRAP_IOP ULL(0x0000000000080000) /* Illegal Instruction */ |
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| 61 | #define MSR_TRAP_PRIV ULL(0x0000000000040000) /* Privileged Instruction */ |
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| 62 | #define MSR_TRAP ULL(0x0000000000020000) /* Trap Instruction */ |
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| 63 | #define MSR_TRAP_NEXT ULL(0x0000000000010000) /* PC is next instruction */ |
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| 64 | #define MSR_TRAP_BITS (MSR_TRAP_FE|MSR_TRAP_IOP|MSR_TRAP_PRIV|MSR_TRAP) |
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| 65 | |
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| 66 | #endif /* _POWERPC_MSR_H */ |
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