1 | /* |
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2 | * This file is subject to the terms and conditions of the GNU General Public |
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3 | * License. See the file "COPYING" in the main directory of this archive |
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4 | * for more details. |
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5 | * |
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6 | * Copyright (C) 1992 - 1997, 2000-2003 Silicon Graphics, Inc. All rights reserved. |
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7 | */ |
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8 | #ifndef _ASM_IA64_SN_PCI_PIC_H |
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9 | #define _ASM_IA64_SN_PCI_PIC_H |
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10 | |
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11 | /* |
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12 | * PIC AS DEVICE ZERO |
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13 | * ------------------ |
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14 | * |
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15 | * PIC handles PCI/X busses. PCI/X requires that the 'bridge' (i.e. PIC) |
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16 | * be designated as 'device 0'. That is a departure from earlier SGI |
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17 | * PCI bridges. Because of that we use config space 1 to access the |
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18 | * config space of the first actual PCI device on the bus. |
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19 | * Here's what the PIC manual says: |
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20 | * |
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21 | * The current PCI-X bus specification now defines that the parent |
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22 | * hosts bus bridge (PIC for example) must be device 0 on bus 0. PIC |
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23 | * reduced the total number of devices from 8 to 4 and removed the |
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24 | * device registers and windows, now only supporting devices 0,1,2, and |
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25 | * 3. PIC did leave all 8 configuration space windows. The reason was |
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26 | * there was nothing to gain by removing them. Here in lies the problem. |
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27 | * The device numbering we do using 0 through 3 is unrelated to the device |
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28 | * numbering which PCI-X requires in configuration space. In the past we |
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29 | * correlated Configs pace and our device space 0 <-> 0, 1 <-> 1, etc. |
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30 | * PCI-X requires we start a 1, not 0 and currently the PX brick |
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31 | * does associate our: |
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32 | * |
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33 | * device 0 with configuration space window 1, |
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34 | * device 1 with configuration space window 2, |
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35 | * device 2 with configuration space window 3, |
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36 | * device 3 with configuration space window 4. |
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37 | * |
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38 | * The net effect is that all config space access are off-by-one with |
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39 | * relation to other per-slot accesses on the PIC. |
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40 | * Here is a table that shows some of that: |
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41 | * |
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42 | * Internal Slot# |
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43 | * | |
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44 | * | 0 1 2 3 |
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45 | * ----------|--------------------------------------- |
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46 | * config | 0x21000 0x22000 0x23000 0x24000 |
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47 | * | |
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48 | * even rrb | 0[0] n/a 1[0] n/a [] == implied even/odd |
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49 | * | |
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50 | * odd rrb | n/a 0[1] n/a 1[1] |
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51 | * | |
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52 | * int dev | 00 01 10 11 |
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53 | * | |
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54 | * ext slot# | 1 2 3 4 |
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55 | * ----------|--------------------------------------- |
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56 | */ |
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57 | |
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58 | #define PIC_ATE_TARGETID_SHFT 8 |
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59 | #define PIC_HOST_INTR_ADDR 0x0000FFFFFFFFFFFFUL |
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60 | #define PIC_PCI64_ATTR_TARG_SHFT 60 |
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61 | |
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62 | |
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63 | /***************************************************************************** |
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64 | *********************** PIC MMR structure mapping *************************** |
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65 | *****************************************************************************/ |
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66 | |
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67 | /* NOTE: PIC WAR. PV#854697. PIC does not allow writes just to [31:0] |
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68 | * of a 64-bit register. When writing PIC registers, always write the |
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69 | * entire 64 bits. |
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70 | */ |
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71 | |
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72 | struct pic { |
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73 | |
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74 | /* 0x000000-0x00FFFF -- Local Registers */ |
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75 | |
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76 | /* 0x000000-0x000057 -- Standard Widget Configuration */ |
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77 | u64 p_wid_id; /* 0x000000 */ |
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78 | u64 p_wid_stat; /* 0x000008 */ |
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79 | u64 p_wid_err_upper; /* 0x000010 */ |
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80 | u64 p_wid_err_lower; /* 0x000018 */ |
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81 | #define p_wid_err p_wid_err_lower |
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82 | u64 p_wid_control; /* 0x000020 */ |
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83 | u64 p_wid_req_timeout; /* 0x000028 */ |
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84 | u64 p_wid_int_upper; /* 0x000030 */ |
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85 | u64 p_wid_int_lower; /* 0x000038 */ |
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86 | #define p_wid_int p_wid_int_lower |
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87 | u64 p_wid_err_cmdword; /* 0x000040 */ |
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88 | u64 p_wid_llp; /* 0x000048 */ |
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89 | u64 p_wid_tflush; /* 0x000050 */ |
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90 | |
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91 | /* 0x000058-0x00007F -- Bridge-specific Widget Configuration */ |
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92 | u64 p_wid_aux_err; /* 0x000058 */ |
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93 | u64 p_wid_resp_upper; /* 0x000060 */ |
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94 | u64 p_wid_resp_lower; /* 0x000068 */ |
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95 | #define p_wid_resp p_wid_resp_lower |
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96 | u64 p_wid_tst_pin_ctrl; /* 0x000070 */ |
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97 | u64 p_wid_addr_lkerr; /* 0x000078 */ |
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98 | |
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99 | /* 0x000080-0x00008F -- PMU & MAP */ |
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100 | u64 p_dir_map; /* 0x000080 */ |
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101 | u64 _pad_000088; /* 0x000088 */ |
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102 | |
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103 | /* 0x000090-0x00009F -- SSRAM */ |
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104 | u64 p_map_fault; /* 0x000090 */ |
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105 | u64 _pad_000098; /* 0x000098 */ |
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106 | |
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107 | /* 0x0000A0-0x0000AF -- Arbitration */ |
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108 | u64 p_arb; /* 0x0000A0 */ |
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109 | u64 _pad_0000A8; /* 0x0000A8 */ |
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110 | |
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111 | /* 0x0000B0-0x0000BF -- Number In A Can or ATE Parity Error */ |
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112 | u64 p_ate_parity_err; /* 0x0000B0 */ |
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113 | u64 _pad_0000B8; /* 0x0000B8 */ |
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114 | |
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115 | /* 0x0000C0-0x0000FF -- PCI/GIO */ |
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116 | u64 p_bus_timeout; /* 0x0000C0 */ |
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117 | u64 p_pci_cfg; /* 0x0000C8 */ |
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118 | u64 p_pci_err_upper; /* 0x0000D0 */ |
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119 | u64 p_pci_err_lower; /* 0x0000D8 */ |
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120 | #define p_pci_err p_pci_err_lower |
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121 | u64 _pad_0000E0[4]; /* 0x0000{E0..F8} */ |
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122 | |
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123 | /* 0x000100-0x0001FF -- Interrupt */ |
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124 | u64 p_int_status; /* 0x000100 */ |
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125 | u64 p_int_enable; /* 0x000108 */ |
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126 | u64 p_int_rst_stat; /* 0x000110 */ |
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127 | u64 p_int_mode; /* 0x000118 */ |
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128 | u64 p_int_device; /* 0x000120 */ |
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129 | u64 p_int_host_err; /* 0x000128 */ |
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130 | u64 p_int_addr[8]; /* 0x0001{30,,,68} */ |
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131 | u64 p_err_int_view; /* 0x000170 */ |
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132 | u64 p_mult_int; /* 0x000178 */ |
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133 | u64 p_force_always[8]; /* 0x0001{80,,,B8} */ |
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134 | u64 p_force_pin[8]; /* 0x0001{C0,,,F8} */ |
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135 | |
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136 | /* 0x000200-0x000298 -- Device */ |
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137 | u64 p_device[4]; /* 0x0002{00,,,18} */ |
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138 | u64 _pad_000220[4]; /* 0x0002{20,,,38} */ |
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139 | u64 p_wr_req_buf[4]; /* 0x0002{40,,,58} */ |
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140 | u64 _pad_000260[4]; /* 0x0002{60,,,78} */ |
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141 | u64 p_rrb_map[2]; /* 0x0002{80,,,88} */ |
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142 | #define p_even_resp p_rrb_map[0] /* 0x000280 */ |
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143 | #define p_odd_resp p_rrb_map[1] /* 0x000288 */ |
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144 | u64 p_resp_status; /* 0x000290 */ |
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145 | u64 p_resp_clear; /* 0x000298 */ |
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146 | |
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147 | u64 _pad_0002A0[12]; /* 0x0002{A0..F8} */ |
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148 | |
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149 | /* 0x000300-0x0003F8 -- Buffer Address Match Registers */ |
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150 | struct { |
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151 | u64 upper; /* 0x0003{00,,,F0} */ |
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152 | u64 lower; /* 0x0003{08,,,F8} */ |
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153 | } p_buf_addr_match[16]; |
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154 | |
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155 | /* 0x000400-0x0005FF -- Performance Monitor Registers (even only) */ |
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156 | struct { |
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157 | u64 flush_w_touch; /* 0x000{400,,,5C0} */ |
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158 | u64 flush_wo_touch; /* 0x000{408,,,5C8} */ |
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159 | u64 inflight; /* 0x000{410,,,5D0} */ |
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160 | u64 prefetch; /* 0x000{418,,,5D8} */ |
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161 | u64 total_pci_retry; /* 0x000{420,,,5E0} */ |
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162 | u64 max_pci_retry; /* 0x000{428,,,5E8} */ |
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163 | u64 max_latency; /* 0x000{430,,,5F0} */ |
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164 | u64 clear_all; /* 0x000{438,,,5F8} */ |
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165 | } p_buf_count[8]; |
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166 | |
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167 | |
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168 | /* 0x000600-0x0009FF -- PCI/X registers */ |
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169 | u64 p_pcix_bus_err_addr; /* 0x000600 */ |
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170 | u64 p_pcix_bus_err_attr; /* 0x000608 */ |
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171 | u64 p_pcix_bus_err_data; /* 0x000610 */ |
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172 | u64 p_pcix_pio_split_addr; /* 0x000618 */ |
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173 | u64 p_pcix_pio_split_attr; /* 0x000620 */ |
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174 | u64 p_pcix_dma_req_err_attr; /* 0x000628 */ |
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175 | u64 p_pcix_dma_req_err_addr; /* 0x000630 */ |
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176 | u64 p_pcix_timeout; /* 0x000638 */ |
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177 | |
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178 | u64 _pad_000640[120]; /* 0x000{640,,,9F8} */ |
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179 | |
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180 | /* 0x000A00-0x000BFF -- PCI/X Read&Write Buffer */ |
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181 | struct { |
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182 | u64 p_buf_addr; /* 0x000{A00,,,AF0} */ |
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183 | u64 p_buf_attr; /* 0X000{A08,,,AF8} */ |
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184 | } p_pcix_read_buf_64[16]; |
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185 | |
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186 | struct { |
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187 | u64 p_buf_addr; /* 0x000{B00,,,BE0} */ |
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188 | u64 p_buf_attr; /* 0x000{B08,,,BE8} */ |
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189 | u64 p_buf_valid; /* 0x000{B10,,,BF0} */ |
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190 | u64 __pad1; /* 0x000{B18,,,BF8} */ |
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191 | } p_pcix_write_buf_64[8]; |
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192 | |
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193 | /* End of Local Registers -- Start of Address Map space */ |
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194 | |
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195 | char _pad_000c00[0x010000 - 0x000c00]; |
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196 | |
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197 | /* 0x010000-0x011fff -- Internal ATE RAM (Auto Parity Generation) */ |
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198 | u64 p_int_ate_ram[1024]; /* 0x010000-0x011fff */ |
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199 | |
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200 | /* 0x012000-0x013fff -- Internal ATE RAM (Manual Parity Generation) */ |
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201 | u64 p_int_ate_ram_mp[1024]; /* 0x012000-0x013fff */ |
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202 | |
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203 | char _pad_014000[0x18000 - 0x014000]; |
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204 | |
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205 | /* 0x18000-0x197F8 -- PIC Write Request Ram */ |
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206 | u64 p_wr_req_lower[256]; /* 0x18000 - 0x187F8 */ |
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207 | u64 p_wr_req_upper[256]; /* 0x18800 - 0x18FF8 */ |
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208 | u64 p_wr_req_parity[256]; /* 0x19000 - 0x197F8 */ |
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209 | |
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210 | char _pad_019800[0x20000 - 0x019800]; |
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211 | |
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212 | /* 0x020000-0x027FFF -- PCI Device Configuration Spaces */ |
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213 | union { |
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214 | u8 c[0x1000 / 1]; /* 0x02{0000,,,7FFF} */ |
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215 | u16 s[0x1000 / 2]; /* 0x02{0000,,,7FFF} */ |
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216 | u32 l[0x1000 / 4]; /* 0x02{0000,,,7FFF} */ |
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217 | u64 d[0x1000 / 8]; /* 0x02{0000,,,7FFF} */ |
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218 | union { |
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219 | u8 c[0x100 / 1]; |
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220 | u16 s[0x100 / 2]; |
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221 | u32 l[0x100 / 4]; |
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222 | u64 d[0x100 / 8]; |
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223 | } f[8]; |
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224 | } p_type0_cfg_dev[8]; /* 0x02{0000,,,7FFF} */ |
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225 | |
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226 | /* 0x028000-0x028FFF -- PCI Type 1 Configuration Space */ |
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227 | union { |
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228 | u8 c[0x1000 / 1]; /* 0x028000-0x029000 */ |
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229 | u16 s[0x1000 / 2]; /* 0x028000-0x029000 */ |
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230 | u32 l[0x1000 / 4]; /* 0x028000-0x029000 */ |
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231 | u64 d[0x1000 / 8]; /* 0x028000-0x029000 */ |
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232 | union { |
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233 | u8 c[0x100 / 1]; |
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234 | u16 s[0x100 / 2]; |
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235 | u32 l[0x100 / 4]; |
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236 | u64 d[0x100 / 8]; |
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237 | } f[8]; |
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238 | } p_type1_cfg; /* 0x028000-0x029000 */ |
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239 | |
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240 | char _pad_029000[0x030000-0x029000]; |
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241 | |
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242 | /* 0x030000-0x030007 -- PCI Interrupt Acknowledge Cycle */ |
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243 | union { |
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244 | u8 c[8 / 1]; |
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245 | u16 s[8 / 2]; |
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246 | u32 l[8 / 4]; |
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247 | u64 d[8 / 8]; |
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248 | } p_pci_iack; /* 0x030000-0x030007 */ |
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249 | |
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250 | char _pad_030007[0x040000-0x030008]; |
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251 | |
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252 | /* 0x040000-0x030007 -- PCIX Special Cycle */ |
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253 | union { |
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254 | u8 c[8 / 1]; |
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255 | u16 s[8 / 2]; |
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256 | u32 l[8 / 4]; |
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257 | u64 d[8 / 8]; |
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258 | } p_pcix_cycle; /* 0x040000-0x040007 */ |
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259 | }; |
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260 | |
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261 | #endif /* _ASM_IA64_SN_PCI_PIC_H */ |
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