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source: trunk/packages/xen-common/xen-common/xen/include/asm-ia64/linux-xen/asm/pgtable.h @ 34

Last change on this file since 34 was 34, checked in by hartmans, 17 years ago
Add xen and xen-common
File size: 23.8 KB

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1	#ifndef _ASM_IA64_PGTABLE_H
2	#define _ASM_IA64_PGTABLE_H
3
4	/*
5	* This file contains the functions and defines necessary to modify and use
6	* the IA-64 page table tree.
7	*
8	* This hopefully works with any (fixed) IA-64 page-size, as defined
9	* in <asm/page.h>.
10	*
11	* Copyright (C) 1998-2005 Hewlett-Packard Co
12	* David Mosberger-Tang <davidm@hpl.hp.com>
13	*/
14
15	#include <linux/config.h>
16
17	#include <asm/mman.h>
18	#include <asm/page.h>
19	#include <asm/processor.h>
20	#include <asm/system.h>
21	#include <asm/types.h>
22	#ifdef XEN
23	#ifndef __ASSEMBLY__
24	#include <xen/sched.h> /* needed for mm_struct (via asm/domain.h) */
25	#endif
26	#endif
27
28	#define IA64_MAX_PHYS_BITS 50 /* max. number of physical address bits (architected) */
29
30	/*
31	* First, define the various bits in a PTE. Note that the PTE format
32	* matches the VHPT short format, the firt doubleword of the VHPD long
33	* format, and the first doubleword of the TLB insertion format.
34	*/
35	#define _PAGE_P_BIT 0
36	#define _PAGE_A_BIT 5
37	#define _PAGE_D_BIT 6
38
39	#define _PAGE_P (1 << _PAGE_P_BIT) /* page present bit */
40	#define _PAGE_MA_WB (0x0 << 2) /* write back memory attribute */
41	#ifdef XEN
42	#define _PAGE_RV1_BIT 1
43	#define _PAGE_RV2_BIT 50
44	#define _PAGE_RV1 (__IA64_UL(1) << _PAGE_RV1_BIT) /* reserved bit */
45	#define _PAGE_RV2 (__IA64_UL(3) << _PAGE_RV2_BIT) /* reserved bits */
46
47	#define _PAGE_MA_ST (0x1 << 2) /* is reserved for software use */
48	#endif
49	#define _PAGE_MA_UC (0x4 << 2) /* uncacheable memory attribute */
50	#define _PAGE_MA_UCE (0x5 << 2) /* UC exported attribute */
51	#define _PAGE_MA_WC (0x6 << 2) /* write coalescing memory attribute */
52	#define _PAGE_MA_NAT (0x7 << 2) /* not-a-thing attribute */
53	#define _PAGE_MA_MASK (0x7 << 2)
54	#define _PAGE_PL_0 (0 << 7) /* privilege level 0 (kernel) */
55	#define _PAGE_PL_1 (1 << 7) /* privilege level 1 (unused) */
56	#define _PAGE_PL_2 (2 << 7) /* privilege level 2 (unused) */
57	#define _PAGE_PL_3 (3 << 7) /* privilege level 3 (user) */
58	#define _PAGE_PL_MASK (3 << 7)
59	#define _PAGE_AR_R (0 << 9) /* read only */
60	#define _PAGE_AR_RX (1 << 9) /* read & execute */
61	#define _PAGE_AR_RW (2 << 9) /* read & write */
62	#define _PAGE_AR_RWX (3 << 9) /* read, write & execute */
63	#define _PAGE_AR_R_RW (4 << 9) /* read / read & write */
64	#define _PAGE_AR_RX_RWX (5 << 9) /* read & exec / read, write & exec */
65	#define _PAGE_AR_RWX_RW (6 << 9) /* read, write & exec / read & write */
66	#define _PAGE_AR_X_RX (7 << 9) /* exec & promote / read & exec */
67	#define _PAGE_AR_MASK (7 << 9)
68	#define _PAGE_AR_SHIFT 9
69	#define _PAGE_A (1 << _PAGE_A_BIT) /* page accessed bit */
70	#define _PAGE_D (1 << _PAGE_D_BIT) /* page dirty bit */
71	#define _PAGE_PPN_MASK (((__IA64_UL(1) << IA64_MAX_PHYS_BITS) - 1) & ~0xfffUL)
72	#define _PAGE_ED (__IA64_UL(1) << 52) /* exception deferral */
73	#ifdef XEN
74	#define _PAGE_VIRT_D (__IA64_UL(1) << 53) /* Virtual dirty bit */
75	#define _PAGE_PROTNONE 0
76
77	#ifdef CONFIG_XEN_IA64_TLB_TRACK
78	#define _PAGE_TLB_TRACKING_BIT 54
79	#define _PAGE_TLB_INSERTED_BIT 55
80	#define _PAGE_TLB_INSERTED_MANY_BIT 56
81
82	#define _PAGE_TLB_TRACKING (1UL << _PAGE_TLB_TRACKING_BIT)
83	#define _PAGE_TLB_INSERTED (1UL << _PAGE_TLB_INSERTED_BIT)
84	#define _PAGE_TLB_INSERTED_MANY (1UL << _PAGE_TLB_INSERTED_MANY_BIT)
85	#define _PAGE_TLB_TRACK_MASK (_PAGE_TLB_TRACKING \| \
86	_PAGE_TLB_INSERTED \| \
87	_PAGE_TLB_INSERTED_MANY)
88
89	#define pte_tlb_tracking(pte) \
90	((pte_val(pte) & _PAGE_TLB_TRACKING) != 0)
91	#define pte_tlb_inserted(pte) \
92	((pte_val(pte) & _PAGE_TLB_INSERTED) != 0)
93	#define pte_tlb_inserted_many(pte) \
94	((pte_val(pte) & _PAGE_TLB_INSERTED_MANY) != 0)
95	#endif // CONFIG_XEN_IA64_TLB_TRACK
96
97	#define _PAGE_PGC_ALLOCATED_BIT 59 /* _PGC_allocated */
98	#define _PAGE_PGC_ALLOCATED (__IA64_UL(1) << _PAGE_PGC_ALLOCATED_BIT)
99	/* domVTI */
100	#define GPFN_MEM (0UL << 60) /* Guest pfn is normal mem */
101	#define GPFN_FRAME_BUFFER (1UL << 60) /* VGA framebuffer */
102	#define GPFN_LOW_MMIO (2UL << 60) /* Low MMIO range */
103	#define GPFN_PIB (3UL << 60) /* PIB base */
104	#define GPFN_IOSAPIC (4UL << 60) /* IOSAPIC base */
105	#define GPFN_LEGACY_IO (5UL << 60) /* Legacy I/O base */
106	#define GPFN_GFW (6UL << 60) /* Guest Firmware */
107	#define GPFN_HIGH_MMIO (7UL << 60) /* High MMIO range */
108
109	#define GPFN_IO_MASK (7UL << 60) /* Guest pfn is I/O type */
110	#define GPFN_INV_MASK (1UL << 63) /* Guest pfn is invalid */
111
112	#else
113	#define _PAGE_PROTNONE (__IA64_UL(1) << 63)
114	#endif
115
116	/* Valid only for a PTE with the present bit cleared: */
117	#define _PAGE_FILE (1 << 1) /* see swap & file pte remarks below */
118
119	#define _PFN_MASK _PAGE_PPN_MASK
120	/* Mask of bits which may be changed by pte_modify(); the odd bits are there for _PAGE_PROTNONE */
121	#define _PAGE_CHG_MASK (_PAGE_P \| _PAGE_PROTNONE \| _PAGE_PL_MASK \| _PAGE_AR_MASK \| _PAGE_ED)
122
123	#define _PAGE_SIZE_4K 12
124	#define _PAGE_SIZE_8K 13
125	#define _PAGE_SIZE_16K 14
126	#define _PAGE_SIZE_64K 16
127	#define _PAGE_SIZE_256K 18
128	#define _PAGE_SIZE_1M 20
129	#define _PAGE_SIZE_4M 22
130	#define _PAGE_SIZE_16M 24
131	#define _PAGE_SIZE_64M 26
132	#define _PAGE_SIZE_256M 28
133	#define _PAGE_SIZE_1G 30
134	#define _PAGE_SIZE_4G 32
135
136	#define __ACCESS_BITS _PAGE_ED \| _PAGE_A \| _PAGE_P \| _PAGE_MA_WB
137	#define __DIRTY_BITS_NO_ED _PAGE_A \| _PAGE_P \| _PAGE_D \| _PAGE_MA_WB
138	#define __DIRTY_BITS _PAGE_ED \| __DIRTY_BITS_NO_ED
139
140	/*
141	* Definitions for first level:
142	*
143	* PGDIR_SHIFT determines what a first-level page table entry can map.
144	*/
145	#define PGDIR_SHIFT (PAGE_SHIFT + 2*(PAGE_SHIFT-3))
146	#define PGDIR_SIZE (__IA64_UL(1) << PGDIR_SHIFT)
147	#define PGDIR_MASK (~(PGDIR_SIZE-1))
148	#define PTRS_PER_PGD (1UL << (PAGE_SHIFT-3))
149	#define USER_PTRS_PER_PGD (5PTRS_PER_PGD/8) / regions 0-4 are user regions */
150	#define FIRST_USER_ADDRESS 0
151
152	/*
153	* Definitions for second level:
154	*
155	* PMD_SHIFT determines the size of the area a second-level page table
156	* can map.
157	*/
158	#define PMD_SHIFT (PAGE_SHIFT + (PAGE_SHIFT-3))
159	#define PMD_SIZE (1UL << PMD_SHIFT)
160	#define PMD_MASK (~(PMD_SIZE-1))
161	#define PTRS_PER_PMD (1UL << (PAGE_SHIFT-3))
162
163	/*
164	* Definitions for third level:
165	*/
166	#define PTRS_PER_PTE (__IA64_UL(1) << (PAGE_SHIFT-3))
167
168	/*
169	* All the normal masks have the "page accessed" bits on, as any time
170	* they are used, the page is accessed. They are cleared only by the
171	* page-out routines.
172	*/
173	#define PAGE_NONE __pgprot(_PAGE_PROTNONE \| _PAGE_A)
174	#define PAGE_SHARED __pgprot(__ACCESS_BITS \| _PAGE_PL_3 \| _PAGE_AR_RW)
175	#define PAGE_READONLY __pgprot(__ACCESS_BITS \| _PAGE_PL_3 \| _PAGE_AR_R)
176	#define PAGE_COPY __pgprot(__ACCESS_BITS \| _PAGE_PL_3 \| _PAGE_AR_R)
177	#define PAGE_COPY_EXEC __pgprot(__ACCESS_BITS \| _PAGE_PL_3 \| _PAGE_AR_RX)
178	#define PAGE_GATE __pgprot(__ACCESS_BITS \| _PAGE_PL_0 \| _PAGE_AR_X_RX)
179	#define PAGE_KERNEL __pgprot(__DIRTY_BITS \| _PAGE_PL_0 \| _PAGE_AR_RWX)
180	#define PAGE_KERNELRX __pgprot(__ACCESS_BITS \| _PAGE_PL_0 \| _PAGE_AR_RX)
181
182	# ifndef __ASSEMBLY__
183
184	#include <asm/bitops.h>
185	#include <asm/cacheflush.h>
186	#include <asm/mmu_context.h>
187	#include <asm/processor.h>
188
189	/*
190	* Next come the mappings that determine how mmap() protection bits
191	* (PROT_EXEC, PROT_READ, PROT_WRITE, PROT_NONE) get implemented. The
192	* _P version gets used for a private shared memory segment, the _S
193	* version gets used for a shared memory segment with MAP_SHARED on.
194	* In a private shared memory segment, we do a copy-on-write if a task
195	* attempts to write to the page.
196	*/
197	/* xwr */
198	#define __P000 PAGE_NONE
199	#define __P001 PAGE_READONLY
200	#define __P010 PAGE_READONLY /* write to priv pg -> copy & make writable */
201	#define __P011 PAGE_READONLY /* ditto */
202	#define __P100 __pgprot(__ACCESS_BITS \| _PAGE_PL_3 \| _PAGE_AR_X_RX)
203	#define __P101 __pgprot(__ACCESS_BITS \| _PAGE_PL_3 \| _PAGE_AR_RX)
204	#define __P110 PAGE_COPY_EXEC
205	#define __P111 PAGE_COPY_EXEC
206
207	#define __S000 PAGE_NONE
208	#define __S001 PAGE_READONLY
209	#define __S010 PAGE_SHARED /* we don't have (and don't need) write-only */
210	#define __S011 PAGE_SHARED
211	#define __S100 __pgprot(__ACCESS_BITS \| _PAGE_PL_3 \| _PAGE_AR_X_RX)
212	#define __S101 __pgprot(__ACCESS_BITS \| _PAGE_PL_3 \| _PAGE_AR_RX)
213	#define __S110 __pgprot(__ACCESS_BITS \| _PAGE_PL_3 \| _PAGE_AR_RWX)
214	#define __S111 __pgprot(__ACCESS_BITS \| _PAGE_PL_3 \| _PAGE_AR_RWX)
215
216	#define pgd_ERROR(e) printk("%s:%d: bad pgd %016lx.\n", __FILE__, __LINE__, pgd_val(e))
217	#define pmd_ERROR(e) printk("%s:%d: bad pmd %016lx.\n", __FILE__, __LINE__, pmd_val(e))
218	#define pte_ERROR(e) printk("%s:%d: bad pte %016lx.\n", __FILE__, __LINE__, pte_val(e))
219
220
221	/*
222	* Some definitions to translate between mem_map, PTEs, and page addresses:
223	*/
224
225
226	/* Quick test to see if ADDR is a (potentially) valid physical address. */
227	static inline long
228	ia64_phys_addr_valid (unsigned long addr)
229	{
230	return (addr & (local_cpu_data->unimpl_pa_mask)) == 0;
231	}
232
233	/*
234	* kern_addr_valid(ADDR) tests if ADDR is pointing to valid kernel
235	* memory. For the return value to be meaningful, ADDR must be >=
236	* PAGE_OFFSET. This operation can be relatively expensive (e.g.,
237	* require a hash-, or multi-level tree-lookup or something of that
238	* sort) but it guarantees to return TRUE only if accessing the page
239	* at that address does not cause an error. Note that there may be
240	* addresses for which kern_addr_valid() returns FALSE even though an
241	* access would not cause an error (e.g., this is typically true for
242	* memory mapped I/O regions.
243	*
244	* XXX Need to implement this for IA-64.
245	*/
246	#define kern_addr_valid(addr) (1)
247
248
249	/*
250	* Now come the defines and routines to manage and access the three-level
251	* page table.
252	*/
253
254	/*
255	* On some architectures, special things need to be done when setting
256	* the PTE in a page table. Nothing special needs to be on IA-64.
257	*/
258	#define set_pte(ptep, pteval) (*(ptep) = (pteval))
259	#define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval)
260	#ifdef XEN
261	static inline void
262	set_pte_rel(volatile pte_t* ptep, pte_t pteval)
263	{
264	#if CONFIG_SMP
265	asm volatile ("st8.rel [%0]=%1" ::
266	"r"(&pte_val(*ptep)), "r"(pte_val(pteval)) :
267	"memory");
268	#else
269	set_pte(ptep, pteval);
270	#endif
271	}
272	#endif
273
274	#define RGN_SIZE (1UL << 61)
275	#define RGN_KERNEL 7
276
277	#define VMALLOC_START 0xa000000200000000UL
278	#ifdef CONFIG_VIRTUAL_MEM_MAP
279	# define VMALLOC_END_INIT (0xa000000000000000UL + (1UL << (4*PAGE_SHIFT - 9)))
280	# define VMALLOC_END vmalloc_end
281	extern unsigned long vmalloc_end;
282	#else
283	# define VMALLOC_END (0xa000000000000000UL + (1UL << (4*PAGE_SHIFT - 9)))
284	#endif
285
286	/* fs/proc/kcore.c */
287	#define kc_vaddr_to_offset(v) ((v) - 0xa000000000000000UL)
288	#define kc_offset_to_vaddr(o) ((o) + 0xa000000000000000UL)
289
290	/*
291	* Conversion functions: convert page frame number (pfn) and a protection value to a page
292	* table entry (pte).
293	*/
294	#define pfn_pte(pfn, pgprot) \
295	({ pte_t __pte; pte_val(__pte) = ((pfn) << PAGE_SHIFT) \| pgprot_val(pgprot); __pte; })
296
297	/* Extract pfn from pte. */
298	#define pte_pfn(_pte) ((pte_val(_pte) & _PFN_MASK) >> PAGE_SHIFT)
299
300	#define mk_pte(page, pgprot) pfn_pte(page_to_mfn(page), (pgprot))
301
302	/* This takes a physical page address that is used by the remapping functions */
303	#define mk_pte_phys(physpage, pgprot) \
304	({ pte_t __pte; pte_val(__pte) = physpage + pgprot_val(pgprot); __pte; })
305
306	#define pte_modify(_pte, newprot) \
307	(__pte((pte_val(_pte) & ~_PAGE_CHG_MASK) \| (pgprot_val(newprot) & _PAGE_CHG_MASK)))
308
309	#define page_pte_prot(page,prot) mk_pte(page, prot)
310	#define page_pte(page) page_pte_prot(page, __pgprot(0))
311
312	#define pte_none(pte) (!pte_val(pte))
313	#define pte_present(pte) (pte_val(pte) & (_PAGE_P \| _PAGE_PROTNONE))
314	#define pte_clear(mm,addr,pte) (pte_val(*(pte)) = 0UL)
315	/* pte_page() returns the "struct page " corresponding to the PTE: /
316	#define pte_page(pte) virt_to_page(((pte_val(pte) & _PFN_MASK) + PAGE_OFFSET))
317
318	#define pmd_none(pmd) (!pmd_val(pmd))
319	#define pmd_bad(pmd) (!ia64_phys_addr_valid(pmd_val(pmd)))
320	#define pmd_present(pmd) (pmd_val(pmd) != 0UL)
321	#define pmd_clear(pmdp) (pmd_val(*(pmdp)) = 0UL)
322	#define pmd_page_kernel(pmd) ((unsigned long) __va(pmd_val(pmd) & _PFN_MASK))
323	#define pmd_page(pmd) virt_to_page((pmd_val(pmd) + PAGE_OFFSET))
324
325	#define pud_none(pud) (!pud_val(pud))
326	#define pud_bad(pud) (!ia64_phys_addr_valid(pud_val(pud)))
327	#define pud_present(pud) (pud_val(pud) != 0UL)
328	#define pud_clear(pudp) (pud_val(*(pudp)) = 0UL)
329
330	#define pud_page(pud) ((unsigned long) __va(pud_val(pud) & _PFN_MASK))
331
332	/*
333	* The following have defined behavior only work if pte_present() is true.
334	*/
335	#define pte_user(pte) ((pte_val(pte) & _PAGE_PL_MASK) == _PAGE_PL_3)
336	#define pte_read(pte) (((pte_val(pte) & _PAGE_AR_MASK) >> _PAGE_AR_SHIFT) < 6)
337	#define pte_write(pte) ((unsigned) (((pte_val(pte) & _PAGE_AR_MASK) >> _PAGE_AR_SHIFT) - 2) <= 4)
338	#define pte_exec(pte) ((pte_val(pte) & _PAGE_AR_RX) != 0)
339	#define pte_dirty(pte) ((pte_val(pte) & _PAGE_D) != 0)
340	#define pte_young(pte) ((pte_val(pte) & _PAGE_A) != 0)
341	#define pte_file(pte) ((pte_val(pte) & _PAGE_FILE) != 0)
342	#ifdef XEN
343	#define pte_pgc_allocated(pte) ((pte_val(pte) & _PAGE_PGC_ALLOCATED) != 0)
344	#define pte_mem(pte) \
345	(!(pte_val(pte) & (GPFN_IO_MASK \| GPFN_INV_MASK)) && !pte_none(pte))
346	#endif
347	/*
348	* Note: we convert AR_RWX to AR_RX and AR_RW to AR_R by clearing the 2nd bit in the
349	* access rights:
350	*/
351	#define pte_wrprotect(pte) (__pte(pte_val(pte) & ~_PAGE_AR_RW))
352	#define pte_mkwrite(pte) (__pte(pte_val(pte) \| _PAGE_AR_RW))
353	#define pte_mkexec(pte) (__pte(pte_val(pte) \| _PAGE_AR_RX))
354	#define pte_mkold(pte) (__pte(pte_val(pte) & ~_PAGE_A))
355	#define pte_mkyoung(pte) (__pte(pte_val(pte) \| _PAGE_A))
356	#define pte_mkclean(pte) (__pte(pte_val(pte) & ~_PAGE_D))
357	#define pte_mkdirty(pte) (__pte(pte_val(pte) \| _PAGE_D))
358	#define pte_mkhuge(pte) (__pte(pte_val(pte) \| _PAGE_P))
359
360	/*
361	* Macro to a page protection value as "uncacheable". Note that "protection" is really a
362	* misnomer here as the protection value contains the memory attribute bits, dirty bits,
363	* and various other bits as well.
364	*/
365	#define pgprot_noncached(prot) __pgprot((pgprot_val(prot) & ~_PAGE_MA_MASK) \| _PAGE_MA_UC)
366
367	/*
368	* Macro to make mark a page protection value as "write-combining".
369	* Note that "protection" is really a misnomer here as the protection
370	* value contains the memory attribute bits, dirty bits, and various
371	* other bits as well. Accesses through a write-combining translation
372	* works bypasses the caches, but does allow for consecutive writes to
373	* be combined into single (but larger) write transactions.
374	*/
375	#define pgprot_writecombine(prot) __pgprot((pgprot_val(prot) & ~_PAGE_MA_MASK) \| _PAGE_MA_WC)
376
377	static inline unsigned long
378	pgd_index (unsigned long address)
379	{
380	unsigned long region = address >> 61;
381	unsigned long l1index = (address >> PGDIR_SHIFT) & ((PTRS_PER_PGD >> 3) - 1);
382
383	return (region << (PAGE_SHIFT - 6)) \| l1index;
384	}
385
386	/* The offset in the 1-level directory is given by the 3 region bits
387	(61..63) and the level-1 bits. */
388	#ifndef XEN
389	static inline pgd_t*
390	#else
391	static inline volatile pgd_t*
392	#endif
393	pgd_offset (struct mm_struct *mm, unsigned long address)
394	{
395	return mm->pgd + pgd_index(address);
396	}
397
398	/* In the kernel's mapped region we completely ignore the region number
399	(since we know it's in region number 5). */
400	#define pgd_offset_k(addr) \
401	(init_mm.pgd + (((addr) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1)))
402
403	/* Look up a pgd entry in the gate area. On IA-64, the gate-area
404	resides in the kernel-mapped segment, hence we use pgd_offset_k()
405	here. */
406	#define pgd_offset_gate(mm, addr) pgd_offset_k(addr)
407
408	/* Find an entry in the second-level page table.. */
409	#ifndef XEN
410	#define pmd_offset(dir,addr) \
411	((pmd_t ) pud_page((dir)) + (((addr) >> PMD_SHIFT) & (PTRS_PER_PMD - 1)))
412	#else
413	#define pmd_offset(dir,addr) \
414	((volatile pmd_t ) pud_page((dir)) + (((addr) >> PMD_SHIFT) & (PTRS_PER_PMD - 1)))
415	#endif
416
417	/*
418	* Find an entry in the third-level page table. This looks more complicated than it
419	* should be because some platforms place page tables in high memory.
420	*/
421	#define pte_index(addr) (((addr) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
422	#ifndef XEN
423	#define pte_offset_kernel(dir,addr) ((pte_t ) pmd_page_kernel((dir)) + pte_index(addr))
424	#else
425	#define pte_offset_kernel(dir,addr) ((volatile pte_t ) pmd_page_kernel((dir)) + pte_index(addr))
426	#endif
427	#define pte_offset_map(dir,addr) pte_offset_kernel(dir, addr)
428	#define pte_offset_map_nested(dir,addr) pte_offset_map(dir, addr)
429	#define pte_unmap(pte) do { } while (0)
430	#define pte_unmap_nested(pte) do { } while (0)
431
432	#ifndef XEN
433	/* atomic versions of the some PTE manipulations: */
434
435	static inline int
436	ptep_test_and_clear_young (struct vm_area_struct vma, unsigned long addr, pte_t ptep)
437	{
438	#ifdef CONFIG_SMP
439	if (!pte_young(*ptep))
440	return 0;
441	return test_and_clear_bit(_PAGE_A_BIT, ptep);
442	#else
443	pte_t pte = *ptep;
444	if (!pte_young(pte))
445	return 0;
446	set_pte_at(vma->vm_mm, addr, ptep, pte_mkold(pte));
447	return 1;
448	#endif
449	}
450
451	static inline int
452	ptep_test_and_clear_dirty (struct vm_area_struct vma, unsigned long addr, pte_t ptep)
453	{
454	#ifdef CONFIG_SMP
455	if (!pte_dirty(*ptep))
456	return 0;
457	return test_and_clear_bit(_PAGE_D_BIT, ptep);
458	#else
459	pte_t pte = *ptep;
460	if (!pte_dirty(pte))
461	return 0;
462	set_pte_at(vma->vm_mm, addr, ptep, pte_mkclean(pte));
463	return 1;
464	#endif
465	}
466	#endif
467
468	#ifdef XEN
469	static inline pte_t
470	ptep_get_and_clear(struct mm_struct *mm, unsigned long addr,
471	volatile pte_t *ptep)
472	#else
473	static inline pte_t
474	ptep_get_and_clear(struct mm_struct mm, unsigned long addr, pte_t ptep)
475	#endif
476	{
477	#ifdef CONFIG_SMP
478	return __pte(xchg((long *) ptep, 0));
479	#else
480	pte_t pte = *ptep;
481	pte_clear(mm, addr, ptep);
482	return pte;
483	#endif
484	}
485
486	#ifdef XEN
487	static inline pte_t
488	ptep_xchg(struct mm_struct *mm, unsigned long addr,
489	volatile pte_t *ptep, pte_t npte)
490	{
491	#ifdef CONFIG_SMP
492	return __pte(xchg((long *) ptep, pte_val(npte)));
493	#else
494	pte_t pte = *ptep;
495	set_pte (ptep, npte);
496	return pte;
497	#endif
498	}
499
500	static inline pte_t
501	ptep_cmpxchg_rel(struct mm_struct *mm, unsigned long addr,
502	volatile pte_t *ptep, pte_t old_pte, pte_t new_pte)
503	{
504	#ifdef CONFIG_SMP
505	return __pte(cmpxchg_rel(&pte_val(*ptep),
506	pte_val(old_pte), pte_val(new_pte)));
507	#else
508	pte_t pte = *ptep;
509	if (pte_val(pte) == pte_val(old_pte)) {
510	set_pte(ptep, new_pte);
511	}
512	return pte;
513	#endif
514	}
515	#endif
516
517	#ifndef XEN
518	static inline void
519	ptep_set_wrprotect(struct mm_struct mm, unsigned long addr, pte_t ptep)
520	{
521	#ifdef CONFIG_SMP
522	unsigned long new, old;
523
524	do {
525	old = pte_val(*ptep);
526	new = pte_val(pte_wrprotect(__pte (old)));
527	} while (cmpxchg((unsigned long *) ptep, old, new) != old);
528	#else
529	pte_t old_pte = *ptep;
530	set_pte_at(mm, addr, ptep, pte_wrprotect(old_pte));
531	#endif
532	}
533
534	static inline int
535	pte_same (pte_t a, pte_t b)
536	{
537	return pte_val(a) == pte_val(b);
538	}
539
540	#define update_mmu_cache(vma, address, pte) do { } while (0)
541	#endif /* XEN */
542
543	extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
544	extern void paging_init (void);
545
546	/*
547	* Note: The macros below rely on the fact that MAX_SWAPFILES_SHIFT <= number of
548	* bits in the swap-type field of the swap pte. It would be nice to
549	* enforce that, but we can't easily include <linux/swap.h> here.
550	* (Of course, better still would be to define MAX_SWAPFILES_SHIFT here...).
551	*
552	* Format of swap pte:
553	* bit 0 : present bit (must be zero)
554	* bit 1 : _PAGE_FILE (must be zero)
555	* bits 2- 8: swap-type
556	* bits 9-62: swap offset
557	* bit 63 : _PAGE_PROTNONE bit
558	*
559	* Format of file pte:
560	* bit 0 : present bit (must be zero)
561	* bit 1 : _PAGE_FILE (must be one)
562	* bits 2-62: file_offset/PAGE_SIZE
563	* bit 63 : _PAGE_PROTNONE bit
564	*/
565	#define __swp_type(entry) (((entry).val >> 2) & 0x7f)
566	#define __swp_offset(entry) (((entry).val << 1) >> 10)
567	#define __swp_entry(type,offset) ((swp_entry_t) { ((type) << 2) \| ((long) (offset) << 9) })
568	#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
569	#define __swp_entry_to_pte(x) ((pte_t) { (x).val })
570
571	#define PTE_FILE_MAX_BITS 61
572	#define pte_to_pgoff(pte) ((pte_val(pte) << 1) >> 3)
573	#define pgoff_to_pte(off) ((pte_t) { ((off) << 2) \| _PAGE_FILE })
574
575	/* XXX is this right? */
576	#define io_remap_page_range(vma, vaddr, paddr, size, prot) \
577	remap_pfn_range(vma, vaddr, (paddr) >> PAGE_SHIFT, size, prot)
578
579	#define io_remap_pfn_range(vma, vaddr, pfn, size, prot) \
580	remap_pfn_range(vma, vaddr, pfn, size, prot)
581
582	#define MK_IOSPACE_PFN(space, pfn) (pfn)
583	#define GET_IOSPACE(pfn) 0
584	#define GET_PFN(pfn) (pfn)
585
586	/*
587	* ZERO_PAGE is a global shared page that is always zero: used
588	* for zero-mapped memory areas etc..
589	*/
590	extern unsigned long empty_zero_page[PAGE_SIZE/sizeof(unsigned long)];
591	#ifndef XEN
592	extern struct page *zero_page_memmap_ptr;
593	#define ZERO_PAGE(vaddr) (zero_page_memmap_ptr)
594	#endif
595
596	/* We provide our own get_unmapped_area to cope with VA holes for userland */
597	#define HAVE_ARCH_UNMAPPED_AREA
598
599	#ifdef CONFIG_HUGETLB_PAGE
600	#define HUGETLB_PGDIR_SHIFT (HPAGE_SHIFT + 2*(PAGE_SHIFT-3))
601	#define HUGETLB_PGDIR_SIZE (__IA64_UL(1) << HUGETLB_PGDIR_SHIFT)
602	#define HUGETLB_PGDIR_MASK (~(HUGETLB_PGDIR_SIZE-1))
603	struct mmu_gather;
604	void hugetlb_free_pgd_range(struct mmu_gather **tlb, unsigned long addr,
605	unsigned long end, unsigned long floor, unsigned long ceiling);
606	#endif
607
608	/*
609	* IA-64 doesn't have any external MMU info: the page tables contain all the necessary
610	* information. However, we use this routine to take care of any (delayed) i-cache
611	* flushing that may be necessary.
612	*/
613	extern void lazy_mmu_prot_update (pte_t pte);
614
615	#define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
616	/*
617	* Update PTEP with ENTRY, which is guaranteed to be a less
618	* restrictive PTE. That is, ENTRY may have the ACCESSED, DIRTY, and
619	* WRITABLE bits turned on, when the value at PTEP did not. The
620	* WRITABLE bit may only be turned if SAFELY_WRITABLE is TRUE.
621	*
622	* SAFELY_WRITABLE is TRUE if we can update the value at PTEP without
623	* having to worry about races. On SMP machines, there are only two
624	* cases where this is true:
625	*
626	* (1) *PTEP has the PRESENT bit turned OFF
627	* (2) ENTRY has the DIRTY bit turned ON
628	*
629	* On ia64, we could implement this routine with a cmpxchg()-loop
630	* which ORs in the _PAGE_A/_PAGE_D bit if they're set in ENTRY.
631	* However, like on x86, we can get a more streamlined version by
632	* observing that it is OK to drop ACCESSED bit updates when
633	* SAFELY_WRITABLE is FALSE. Besides being rare, all that would do is
634	* result in an extra Access-bit fault, which would then turn on the
635	* ACCESSED bit in the low-level fault handler (iaccess_bit or
636	* daccess_bit in ivt.S).
637	*/
638	#ifdef CONFIG_SMP
639	# define ptep_set_access_flags(__vma, __addr, __ptep, __entry, __safely_writable) \
640	do { \
641	if (__safely_writable) { \
642	set_pte(__ptep, __entry); \
643	flush_tlb_page(__vma, __addr); \
644	} \
645	} while (0)
646	#else
647	# define ptep_set_access_flags(__vma, __addr, __ptep, __entry, __safely_writable) \
648	ptep_establish(__vma, __addr, __ptep, __entry)
649	#endif
650
651	# ifdef CONFIG_VIRTUAL_MEM_MAP
652	/* arch mem_map init routine is needed due to holes in a virtual mem_map */
653	# define __HAVE_ARCH_MEMMAP_INIT
654	extern void memmap_init (unsigned long size, int nid, unsigned long zone,
655	unsigned long start_pfn);
656	# endif /* CONFIG_VIRTUAL_MEM_MAP */
657	# endif /* !__ASSEMBLY__ */
658
659	/*
660	* Identity-mapped regions use a large page size. We'll call such large pages
661	* "granules". If you can think of a better name that's unambiguous, let me
662	* know...
663	*/
664	#if defined(CONFIG_IA64_GRANULE_64MB)
665	# define IA64_GRANULE_SHIFT _PAGE_SIZE_64M
666	#elif defined(CONFIG_IA64_GRANULE_16MB)
667	# define IA64_GRANULE_SHIFT _PAGE_SIZE_16M
668	#endif
669	#define IA64_GRANULE_SIZE (1 << IA64_GRANULE_SHIFT)
670	/*
671	* log2() of the page size we use to map the kernel image (IA64_TR_KERNEL):
672	*/
673	#define KERNEL_TR_PAGE_SHIFT _PAGE_SIZE_64M
674	#define KERNEL_TR_PAGE_SIZE (1 << KERNEL_TR_PAGE_SHIFT)
675
676	/*
677	* No page table caches to initialise
678	*/
679	#define pgtable_cache_init() do { } while (0)
680
681	/* These tell get_user_pages() that the first gate page is accessible from user-level. */
682	#define FIXADDR_USER_START GATE_ADDR
683	#ifdef HAVE_BUGGY_SEGREL
684	# define FIXADDR_USER_END (GATE_ADDR + 2*PAGE_SIZE)
685	#else
686	# define FIXADDR_USER_END (GATE_ADDR + 2*PERCPU_PAGE_SIZE)
687	#endif
688
689	#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
690	#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_DIRTY
691	#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
692	#define __HAVE_ARCH_PTEP_SET_WRPROTECT
693	#define __HAVE_ARCH_PTE_SAME
694	#define __HAVE_ARCH_PGD_OFFSET_GATE
695	#define __HAVE_ARCH_LAZY_MMU_PROT_UPDATE
696
697	#include <asm-generic/pgtable-nopud.h>
698	#include <asm-generic/pgtable.h>
699
700	#endif /* _ASM_IA64_PGTABLE_H */

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