1 | #ifndef _ASM_IA64_PCI_H |
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2 | #define _ASM_IA64_PCI_H |
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3 | |
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4 | #include <linux/mm.h> |
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5 | #include <linux/slab.h> |
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6 | #include <linux/spinlock.h> |
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7 | #include <linux/string.h> |
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8 | #include <linux/types.h> |
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9 | #ifdef XEN |
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10 | #include <linux/ioport.h> |
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11 | #endif |
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12 | |
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13 | #include <asm/io.h> |
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14 | #ifndef XEN |
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15 | #include <asm/scatterlist.h> |
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16 | #endif |
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17 | |
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18 | /* |
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19 | * Can be used to override the logic in pci_scan_bus for skipping already-configured bus |
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20 | * numbers - to be used for buggy BIOSes or architectures with incomplete PCI setup by the |
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21 | * loader. |
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22 | */ |
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23 | #define pcibios_assign_all_busses() 0 |
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24 | #define pcibios_scan_all_fns(a, b) 0 |
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25 | |
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26 | #define PCIBIOS_MIN_IO 0x1000 |
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27 | #define PCIBIOS_MIN_MEM 0x10000000 |
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28 | |
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29 | void pcibios_config_init(void); |
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30 | |
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31 | struct pci_dev; |
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32 | |
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33 | /* |
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34 | * PCI_DMA_BUS_IS_PHYS should be set to 1 if there is _necessarily_ a direct correspondence |
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35 | * between device bus addresses and CPU physical addresses. Platforms with a hardware I/O |
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36 | * MMU _must_ turn this off to suppress the bounce buffer handling code in the block and |
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37 | * network device layers. Platforms with separate bus address spaces _must_ turn this off |
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38 | * and provide a device DMA mapping implementation that takes care of the necessary |
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39 | * address translation. |
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40 | * |
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41 | * For now, the ia64 platforms which may have separate/multiple bus address spaces all |
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42 | * have I/O MMUs which support the merging of physically discontiguous buffers, so we can |
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43 | * use that as the sole factor to determine the setting of PCI_DMA_BUS_IS_PHYS. |
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44 | */ |
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45 | extern unsigned long ia64_max_iommu_merge_mask; |
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46 | #define PCI_DMA_BUS_IS_PHYS (ia64_max_iommu_merge_mask == ~0UL) |
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47 | |
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48 | static inline void |
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49 | pcibios_set_master (struct pci_dev *dev) |
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50 | { |
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51 | /* No special bus mastering setup handling */ |
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52 | } |
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53 | |
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54 | static inline void |
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55 | pcibios_penalize_isa_irq (int irq, int active) |
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56 | { |
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57 | /* We don't do dynamic PCI IRQ allocation */ |
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58 | } |
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59 | |
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60 | #define HAVE_ARCH_PCI_MWI 1 |
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61 | extern int pcibios_prep_mwi (struct pci_dev *); |
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62 | |
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63 | #ifndef XEN |
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64 | #include <asm-generic/pci-dma-compat.h> |
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65 | #endif |
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66 | |
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67 | /* pci_unmap_{single,page} is not a nop, thus... */ |
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68 | #define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME) \ |
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69 | dma_addr_t ADDR_NAME; |
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70 | #define DECLARE_PCI_UNMAP_LEN(LEN_NAME) \ |
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71 | __u32 LEN_NAME; |
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72 | #define pci_unmap_addr(PTR, ADDR_NAME) \ |
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73 | ((PTR)->ADDR_NAME) |
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74 | #define pci_unmap_addr_set(PTR, ADDR_NAME, VAL) \ |
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75 | (((PTR)->ADDR_NAME) = (VAL)) |
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76 | #define pci_unmap_len(PTR, LEN_NAME) \ |
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77 | ((PTR)->LEN_NAME) |
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78 | #define pci_unmap_len_set(PTR, LEN_NAME, VAL) \ |
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79 | (((PTR)->LEN_NAME) = (VAL)) |
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80 | |
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81 | /* The ia64 platform always supports 64-bit addressing. */ |
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82 | #define pci_dac_dma_supported(pci_dev, mask) (1) |
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83 | #define pci_dac_page_to_dma(dev,pg,off,dir) ((dma_addr_t) page_to_bus(pg) + (off)) |
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84 | #define pci_dac_dma_to_page(dev,dma_addr) (virt_to_page(bus_to_virt(dma_addr))) |
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85 | #define pci_dac_dma_to_offset(dev,dma_addr) offset_in_page(dma_addr) |
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86 | #define pci_dac_dma_sync_single_for_cpu(dev,dma_addr,len,dir) do { } while (0) |
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87 | #define pci_dac_dma_sync_single_for_device(dev,dma_addr,len,dir) do { mb(); } while (0) |
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88 | |
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89 | #define sg_dma_len(sg) ((sg)->dma_length) |
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90 | #define sg_dma_address(sg) ((sg)->dma_address) |
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91 | |
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92 | #ifdef CONFIG_PCI |
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93 | static inline void pci_dma_burst_advice(struct pci_dev *pdev, |
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94 | enum pci_dma_burst_strategy *strat, |
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95 | unsigned long *strategy_parameter) |
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96 | { |
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97 | unsigned long cacheline_size; |
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98 | u8 byte; |
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99 | |
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100 | pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &byte); |
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101 | if (byte == 0) |
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102 | cacheline_size = 1024; |
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103 | else |
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104 | cacheline_size = (int) byte * 4; |
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105 | |
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106 | *strat = PCI_DMA_BURST_MULTIPLE; |
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107 | *strategy_parameter = cacheline_size; |
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108 | } |
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109 | #endif |
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110 | |
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111 | #define HAVE_PCI_MMAP |
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112 | extern int pci_mmap_page_range (struct pci_dev *dev, struct vm_area_struct *vma, |
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113 | enum pci_mmap_state mmap_state, int write_combine); |
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114 | #define HAVE_PCI_LEGACY |
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115 | extern int pci_mmap_legacy_page_range(struct pci_bus *bus, |
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116 | struct vm_area_struct *vma); |
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117 | #ifndef XEN |
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118 | extern ssize_t pci_read_legacy_io(struct kobject *kobj, char *buf, loff_t off, |
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119 | size_t count); |
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120 | extern ssize_t pci_write_legacy_io(struct kobject *kobj, char *buf, loff_t off, |
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121 | size_t count); |
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122 | extern int pci_mmap_legacy_mem(struct kobject *kobj, |
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123 | struct bin_attribute *attr, |
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124 | struct vm_area_struct *vma); |
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125 | #endif |
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126 | |
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127 | #define pci_get_legacy_mem platform_pci_get_legacy_mem |
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128 | #define pci_legacy_read platform_pci_legacy_read |
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129 | #define pci_legacy_write platform_pci_legacy_write |
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130 | |
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131 | struct pci_window { |
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132 | struct resource resource; |
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133 | u64 offset; |
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134 | }; |
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135 | |
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136 | struct pci_controller { |
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137 | void *acpi_handle; |
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138 | void *iommu; |
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139 | int segment; |
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140 | int node; /* nearest node with memory or -1 for global allocation */ |
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141 | |
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142 | unsigned int windows; |
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143 | struct pci_window *window; |
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144 | |
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145 | void *platform_data; |
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146 | }; |
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147 | |
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148 | #define PCI_CONTROLLER(busdev) ((struct pci_controller *) busdev->sysdata) |
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149 | #define pci_domain_nr(busdev) (PCI_CONTROLLER(busdev)->segment) |
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150 | |
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151 | extern struct pci_ops pci_root_ops; |
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152 | |
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153 | static inline int pci_proc_domain(struct pci_bus *bus) |
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154 | { |
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155 | return (pci_domain_nr(bus) != 0); |
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156 | } |
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157 | |
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158 | static inline void pcibios_add_platform_entries(struct pci_dev *dev) |
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159 | { |
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160 | } |
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161 | |
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162 | extern void pcibios_resource_to_bus(struct pci_dev *dev, |
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163 | struct pci_bus_region *region, struct resource *res); |
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164 | |
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165 | extern void pcibios_bus_to_resource(struct pci_dev *dev, |
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166 | struct resource *res, struct pci_bus_region *region); |
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167 | |
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168 | #ifndef XEN |
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169 | static inline struct resource * |
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170 | pcibios_select_root(struct pci_dev *pdev, struct resource *res) |
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171 | { |
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172 | struct resource *root = NULL; |
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173 | |
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174 | if (res->flags & IORESOURCE_IO) |
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175 | root = &ioport_resource; |
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176 | if (res->flags & IORESOURCE_MEM) |
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177 | root = &iomem_resource; |
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178 | |
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179 | return root; |
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180 | } |
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181 | #endif |
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182 | |
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183 | #define pcibios_scan_all_fns(a, b) 0 |
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184 | |
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185 | #endif /* _ASM_IA64_PCI_H */ |
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