| 1 | /* |
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| 2 | * Athlon/Hammer specific Machine Check Exception Reporting |
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| 3 | * (C) Copyright 2002 Dave Jones <davej@codemonkey.org.uk> |
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| 4 | */ |
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| 5 | |
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| 6 | #include <xen/init.h> |
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| 7 | #include <xen/types.h> |
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| 8 | #include <xen/kernel.h> |
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| 9 | #include <xen/config.h> |
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| 10 | #include <xen/smp.h> |
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| 11 | |
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| 12 | #include <asm/processor.h> |
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| 13 | #include <asm/system.h> |
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| 14 | #include <asm/msr.h> |
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| 15 | |
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| 16 | #include "mce.h" |
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| 17 | |
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| 18 | /* Machine Check Handler For AMD Athlon/Duron */ |
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| 19 | static fastcall void k7_machine_check(struct cpu_user_regs * regs, long error_code) |
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| 20 | { |
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| 21 | int recover=1; |
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| 22 | u32 alow, ahigh, high, low; |
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| 23 | u32 mcgstl, mcgsth; |
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| 24 | int i; |
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| 25 | |
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| 26 | rdmsr (MSR_IA32_MCG_STATUS, mcgstl, mcgsth); |
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| 27 | if (mcgstl & (1<<0)) /* Recoverable ? */ |
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| 28 | recover=0; |
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| 29 | |
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| 30 | printk (KERN_EMERG "CPU %d: Machine Check Exception: %08x%08x\n", |
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| 31 | smp_processor_id(), mcgsth, mcgstl); |
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| 32 | |
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| 33 | for (i=1; i<nr_mce_banks; i++) { |
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| 34 | rdmsr (MSR_IA32_MC0_STATUS+i*4,low, high); |
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| 35 | if (high&(1<<31)) { |
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| 36 | if (high & (1<<29)) |
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| 37 | recover |= 1; |
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| 38 | if (high & (1<<25)) |
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| 39 | recover |= 2; |
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| 40 | printk (KERN_EMERG "Bank %d: %08x%08x", i, high, low); |
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| 41 | high &= ~(1<<31); |
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| 42 | if (high & (1<<27)) { |
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| 43 | rdmsr (MSR_IA32_MC0_MISC+i*4, alow, ahigh); |
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| 44 | printk ("[%08x%08x]", ahigh, alow); |
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| 45 | } |
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| 46 | if (high & (1<<26)) { |
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| 47 | rdmsr (MSR_IA32_MC0_ADDR+i*4, alow, ahigh); |
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| 48 | printk (" at %08x%08x", ahigh, alow); |
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| 49 | } |
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| 50 | printk ("\n"); |
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| 51 | /* Clear it */ |
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| 52 | wrmsr (MSR_IA32_MC0_STATUS+i*4, 0UL, 0UL); |
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| 53 | /* Serialize */ |
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| 54 | wmb(); |
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| 55 | add_taint(TAINT_MACHINE_CHECK); |
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| 56 | } |
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| 57 | } |
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| 58 | |
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| 59 | if (recover&2) |
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| 60 | panic ("CPU context corrupt"); |
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| 61 | if (recover&1) |
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| 62 | panic ("Unable to continue"); |
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| 63 | printk (KERN_EMERG "Attempting to continue.\n"); |
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| 64 | mcgstl &= ~(1<<2); |
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| 65 | wrmsr (MSR_IA32_MCG_STATUS,mcgstl, mcgsth); |
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| 66 | } |
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| 67 | |
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| 68 | |
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| 69 | /* AMD K7 machine check is Intel like */ |
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| 70 | void amd_mcheck_init(struct cpuinfo_x86 *c) |
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| 71 | { |
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| 72 | u32 l, h; |
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| 73 | int i; |
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| 74 | |
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| 75 | machine_check_vector = k7_machine_check; |
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| 76 | wmb(); |
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| 77 | |
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| 78 | printk (KERN_INFO "Intel machine check architecture supported.\n"); |
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| 79 | rdmsr (MSR_IA32_MCG_CAP, l, h); |
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| 80 | if (l & (1<<8)) /* Control register present ? */ |
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| 81 | wrmsr (MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff); |
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| 82 | nr_mce_banks = l & 0xff; |
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| 83 | |
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| 84 | /* Clear status for MC index 0 separately, we don't touch CTL, |
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| 85 | * as some Athlons cause spurious MCEs when its enabled. */ |
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| 86 | wrmsr (MSR_IA32_MC0_STATUS, 0x0, 0x0); |
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| 87 | for (i=1; i<nr_mce_banks; i++) { |
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| 88 | wrmsr (MSR_IA32_MC0_CTL+4*i, 0xffffffff, 0xffffffff); |
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| 89 | wrmsr (MSR_IA32_MC0_STATUS+4*i, 0x0, 0x0); |
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| 90 | } |
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| 91 | |
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| 92 | set_in_cr4 (X86_CR4_MCE); |
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| 93 | printk (KERN_INFO "Intel machine check reporting enabled on CPU#%d.\n", |
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| 94 | smp_processor_id()); |
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| 95 | } |
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