1 | /* |
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2 | * QEMU Sun4m System Emulator |
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3 | * |
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4 | * Copyright (c) 2003-2005 Fabrice Bellard |
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5 | * |
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6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
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7 | * of this software and associated documentation files (the "Software"), to deal |
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8 | * in the Software without restriction, including without limitation the rights |
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9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
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10 | * copies of the Software, and to permit persons to whom the Software is |
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11 | * furnished to do so, subject to the following conditions: |
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12 | * |
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13 | * The above copyright notice and this permission notice shall be included in |
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14 | * all copies or substantial portions of the Software. |
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15 | * |
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16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
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21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
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22 | * THE SOFTWARE. |
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23 | */ |
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24 | #include "vl.h" |
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25 | |
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26 | #define KERNEL_LOAD_ADDR 0x00004000 |
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27 | #define CMDLINE_ADDR 0x007ff000 |
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28 | #define INITRD_LOAD_ADDR 0x00800000 |
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29 | #define PROM_SIZE_MAX (256 * 1024) |
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30 | #define PROM_ADDR 0xffd00000 |
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31 | #define PROM_FILENAME "openbios-sparc32" |
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32 | #define PHYS_JJ_EEPROM 0x71200000 /* m48t08 */ |
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33 | #define PHYS_JJ_IDPROM_OFF 0x1FD8 |
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34 | #define PHYS_JJ_EEPROM_SIZE 0x2000 |
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35 | // IRQs are not PIL ones, but master interrupt controller register |
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36 | // bits |
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37 | #define PHYS_JJ_IOMMU 0x10000000 /* I/O MMU */ |
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38 | #define PHYS_JJ_TCX_FB 0x50000000 /* TCX frame buffer */ |
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39 | #define PHYS_JJ_SLAVIO 0x70000000 /* Slavio base */ |
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40 | #define PHYS_JJ_ESPDMA 0x78400000 /* ESP DMA controller */ |
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41 | #define PHYS_JJ_ESP 0x78800000 /* ESP SCSI */ |
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42 | #define PHYS_JJ_ESP_IRQ 18 |
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43 | #define PHYS_JJ_LEDMA 0x78400010 /* Lance DMA controller */ |
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44 | #define PHYS_JJ_LE 0x78C00000 /* Lance ethernet */ |
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45 | #define PHYS_JJ_LE_IRQ 16 |
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46 | #define PHYS_JJ_CLOCK 0x71D00000 /* Per-CPU timer/counter, L14 */ |
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47 | #define PHYS_JJ_CLOCK_IRQ 7 |
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48 | #define PHYS_JJ_CLOCK1 0x71D10000 /* System timer/counter, L10 */ |
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49 | #define PHYS_JJ_CLOCK1_IRQ 19 |
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50 | #define PHYS_JJ_INTR0 0x71E00000 /* Per-CPU interrupt control registers */ |
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51 | #define PHYS_JJ_INTR_G 0x71E10000 /* Master interrupt control registers */ |
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52 | #define PHYS_JJ_MS_KBD 0x71000000 /* Mouse and keyboard */ |
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53 | #define PHYS_JJ_MS_KBD_IRQ 14 |
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54 | #define PHYS_JJ_SER 0x71100000 /* Serial */ |
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55 | #define PHYS_JJ_SER_IRQ 15 |
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56 | #define PHYS_JJ_FDC 0x71400000 /* Floppy */ |
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57 | #define PHYS_JJ_FLOPPY_IRQ 22 |
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58 | #define PHYS_JJ_ME_IRQ 30 /* Module error, power fail */ |
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59 | #define MAX_CPUS 16 |
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60 | |
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61 | /* TSC handling */ |
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62 | |
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63 | uint64_t cpu_get_tsc() |
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64 | { |
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65 | return qemu_get_clock(vm_clock); |
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66 | } |
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67 | |
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68 | int DMA_get_channel_mode (int nchan) |
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69 | { |
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70 | return 0; |
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71 | } |
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72 | int DMA_read_memory (int nchan, void *buf, int pos, int size) |
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73 | { |
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74 | return 0; |
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75 | } |
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76 | int DMA_write_memory (int nchan, void *buf, int pos, int size) |
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77 | { |
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78 | return 0; |
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79 | } |
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80 | void DMA_hold_DREQ (int nchan) {} |
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81 | void DMA_release_DREQ (int nchan) {} |
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82 | void DMA_schedule(int nchan) {} |
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83 | void DMA_run (void) {} |
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84 | void DMA_init (int high_page_enable) {} |
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85 | void DMA_register_channel (int nchan, |
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86 | DMA_transfer_handler transfer_handler, |
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87 | void *opaque) |
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88 | { |
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89 | } |
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90 | |
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91 | static void nvram_set_word (m48t59_t *nvram, uint32_t addr, uint16_t value) |
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92 | { |
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93 | m48t59_write(nvram, addr++, (value >> 8) & 0xff); |
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94 | m48t59_write(nvram, addr++, value & 0xff); |
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95 | } |
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96 | |
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97 | static void nvram_set_lword (m48t59_t *nvram, uint32_t addr, uint32_t value) |
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98 | { |
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99 | m48t59_write(nvram, addr++, value >> 24); |
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100 | m48t59_write(nvram, addr++, (value >> 16) & 0xff); |
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101 | m48t59_write(nvram, addr++, (value >> 8) & 0xff); |
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102 | m48t59_write(nvram, addr++, value & 0xff); |
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103 | } |
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104 | |
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105 | static void nvram_set_string (m48t59_t *nvram, uint32_t addr, |
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106 | const unsigned char *str, uint32_t max) |
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107 | { |
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108 | unsigned int i; |
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109 | |
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110 | for (i = 0; i < max && str[i] != '\0'; i++) { |
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111 | m48t59_write(nvram, addr + i, str[i]); |
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112 | } |
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113 | m48t59_write(nvram, addr + max - 1, '\0'); |
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114 | } |
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115 | |
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116 | static m48t59_t *nvram; |
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117 | |
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118 | extern int nographic; |
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119 | |
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120 | static void nvram_init(m48t59_t *nvram, uint8_t *macaddr, const char *cmdline, |
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121 | int boot_device, uint32_t RAM_size, |
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122 | uint32_t kernel_size, |
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123 | int width, int height, int depth) |
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124 | { |
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125 | unsigned char tmp = 0; |
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126 | int i, j; |
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127 | |
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128 | // Try to match PPC NVRAM |
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129 | nvram_set_string(nvram, 0x00, "QEMU_BIOS", 16); |
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130 | nvram_set_lword(nvram, 0x10, 0x00000001); /* structure v1 */ |
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131 | // NVRAM_size, arch not applicable |
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132 | m48t59_write(nvram, 0x2D, smp_cpus & 0xff); |
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133 | m48t59_write(nvram, 0x2E, 0); |
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134 | m48t59_write(nvram, 0x2F, nographic & 0xff); |
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135 | nvram_set_lword(nvram, 0x30, RAM_size); |
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136 | m48t59_write(nvram, 0x34, boot_device & 0xff); |
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137 | nvram_set_lword(nvram, 0x38, KERNEL_LOAD_ADDR); |
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138 | nvram_set_lword(nvram, 0x3C, kernel_size); |
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139 | if (cmdline) { |
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140 | strcpy(phys_ram_base + CMDLINE_ADDR, cmdline); |
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141 | nvram_set_lword(nvram, 0x40, CMDLINE_ADDR); |
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142 | nvram_set_lword(nvram, 0x44, strlen(cmdline)); |
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143 | } |
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144 | // initrd_image, initrd_size passed differently |
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145 | nvram_set_word(nvram, 0x54, width); |
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146 | nvram_set_word(nvram, 0x56, height); |
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147 | nvram_set_word(nvram, 0x58, depth); |
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148 | |
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149 | // Sun4m specific use |
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150 | i = 0x1fd8; |
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151 | m48t59_write(nvram, i++, 0x01); |
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152 | m48t59_write(nvram, i++, 0x80); /* Sun4m OBP */ |
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153 | j = 0; |
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154 | m48t59_write(nvram, i++, macaddr[j++]); |
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155 | m48t59_write(nvram, i++, macaddr[j++]); |
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156 | m48t59_write(nvram, i++, macaddr[j++]); |
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157 | m48t59_write(nvram, i++, macaddr[j++]); |
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158 | m48t59_write(nvram, i++, macaddr[j++]); |
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159 | m48t59_write(nvram, i, macaddr[j]); |
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160 | |
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161 | /* Calculate checksum */ |
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162 | for (i = 0x1fd8; i < 0x1fe7; i++) { |
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163 | tmp ^= m48t59_read(nvram, i); |
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164 | } |
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165 | m48t59_write(nvram, 0x1fe7, tmp); |
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166 | } |
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167 | |
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168 | static void *slavio_intctl; |
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169 | |
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170 | void pic_info() |
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171 | { |
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172 | slavio_pic_info(slavio_intctl); |
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173 | } |
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174 | |
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175 | void irq_info() |
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176 | { |
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177 | slavio_irq_info(slavio_intctl); |
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178 | } |
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179 | |
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180 | void pic_set_irq(int irq, int level) |
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181 | { |
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182 | slavio_pic_set_irq(slavio_intctl, irq, level); |
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183 | } |
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184 | |
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185 | void pic_set_irq_new(void *opaque, int irq, int level) |
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186 | { |
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187 | pic_set_irq(irq, level); |
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188 | } |
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189 | |
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190 | void pic_set_irq_cpu(int irq, int level, unsigned int cpu) |
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191 | { |
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192 | slavio_pic_set_irq_cpu(slavio_intctl, irq, level, cpu); |
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193 | } |
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194 | |
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195 | static void *iommu; |
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196 | |
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197 | uint32_t iommu_translate(uint32_t addr) |
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198 | { |
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199 | return iommu_translate_local(iommu, addr); |
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200 | } |
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201 | |
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202 | static void *slavio_misc; |
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203 | |
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204 | void qemu_system_powerdown(void) |
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205 | { |
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206 | slavio_set_power_fail(slavio_misc, 1); |
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207 | } |
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208 | |
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209 | static void main_cpu_reset(void *opaque) |
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210 | { |
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211 | CPUState *env = opaque; |
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212 | cpu_reset(env); |
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213 | } |
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214 | |
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215 | /* Sun4m hardware initialisation */ |
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216 | static void sun4m_init(int ram_size, int vga_ram_size, int boot_device, |
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217 | DisplayState *ds, const char **fd_filename, int snapshot, |
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218 | const char *kernel_filename, const char *kernel_cmdline, |
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219 | const char *initrd_filename) |
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220 | { |
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221 | CPUState *env, *envs[MAX_CPUS]; |
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222 | char buf[1024]; |
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223 | int ret, linux_boot; |
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224 | unsigned int i; |
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225 | long vram_size = 0x100000, prom_offset, initrd_size, kernel_size; |
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226 | |
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227 | linux_boot = (kernel_filename != NULL); |
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228 | |
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229 | /* init CPUs */ |
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230 | for(i = 0; i < smp_cpus; i++) { |
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231 | env = cpu_init(); |
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232 | envs[i] = env; |
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233 | if (i != 0) |
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234 | env->halted = 1; |
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235 | register_savevm("cpu", i, 3, cpu_save, cpu_load, env); |
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236 | qemu_register_reset(main_cpu_reset, env); |
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237 | } |
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238 | /* allocate RAM */ |
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239 | cpu_register_physical_memory(0, ram_size, 0); |
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240 | |
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241 | iommu = iommu_init(PHYS_JJ_IOMMU); |
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242 | slavio_intctl = slavio_intctl_init(PHYS_JJ_INTR0, PHYS_JJ_INTR_G); |
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243 | for(i = 0; i < smp_cpus; i++) { |
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244 | slavio_intctl_set_cpu(slavio_intctl, i, envs[i]); |
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245 | } |
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246 | |
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247 | tcx_init(ds, PHYS_JJ_TCX_FB, phys_ram_base + ram_size, ram_size, vram_size, graphic_width, graphic_height); |
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248 | if (nd_table[0].vlan) { |
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249 | if (nd_table[0].model == NULL |
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250 | || strcmp(nd_table[0].model, "lance") == 0) { |
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251 | lance_init(&nd_table[0], PHYS_JJ_LE_IRQ, PHYS_JJ_LE, PHYS_JJ_LEDMA); |
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252 | } else { |
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253 | fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model); |
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254 | exit (1); |
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255 | } |
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256 | } |
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257 | nvram = m48t59_init(0, PHYS_JJ_EEPROM, 0, PHYS_JJ_EEPROM_SIZE, 8); |
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258 | for (i = 0; i < MAX_CPUS; i++) { |
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259 | slavio_timer_init(PHYS_JJ_CLOCK + i * TARGET_PAGE_SIZE, PHYS_JJ_CLOCK_IRQ, 0, i); |
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260 | } |
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261 | slavio_timer_init(PHYS_JJ_CLOCK1, PHYS_JJ_CLOCK1_IRQ, 2, (unsigned int)-1); |
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262 | slavio_serial_ms_kbd_init(PHYS_JJ_MS_KBD, PHYS_JJ_MS_KBD_IRQ); |
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263 | // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device |
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264 | // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device |
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265 | slavio_serial_init(PHYS_JJ_SER, PHYS_JJ_SER_IRQ, serial_hds[1], serial_hds[0]); |
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266 | fdctrl_init(PHYS_JJ_FLOPPY_IRQ, 0, 1, PHYS_JJ_FDC, fd_table); |
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267 | esp_init(bs_table, PHYS_JJ_ESP_IRQ, PHYS_JJ_ESP, PHYS_JJ_ESPDMA); |
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268 | slavio_misc = slavio_misc_init(PHYS_JJ_SLAVIO, PHYS_JJ_ME_IRQ); |
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269 | |
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270 | prom_offset = ram_size + vram_size; |
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271 | cpu_register_physical_memory(PROM_ADDR, |
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272 | (PROM_SIZE_MAX + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK, |
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273 | prom_offset | IO_MEM_ROM); |
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274 | |
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275 | snprintf(buf, sizeof(buf), "%s/%s", bios_dir, PROM_FILENAME); |
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276 | ret = load_elf(buf, 0, NULL); |
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277 | if (ret < 0) { |
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278 | fprintf(stderr, "qemu: could not load prom '%s'\n", |
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279 | buf); |
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280 | exit(1); |
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281 | } |
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282 | |
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283 | kernel_size = 0; |
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284 | if (linux_boot) { |
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285 | kernel_size = load_elf(kernel_filename, -0xf0000000, NULL); |
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286 | if (kernel_size < 0) |
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287 | kernel_size = load_aout(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR); |
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288 | if (kernel_size < 0) |
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289 | kernel_size = load_image(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR); |
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290 | if (kernel_size < 0) { |
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291 | fprintf(stderr, "qemu: could not load kernel '%s'\n", |
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292 | kernel_filename); |
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293 | exit(1); |
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294 | } |
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295 | |
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296 | /* load initrd */ |
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297 | initrd_size = 0; |
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298 | if (initrd_filename) { |
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299 | initrd_size = load_image(initrd_filename, phys_ram_base + INITRD_LOAD_ADDR); |
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300 | if (initrd_size < 0) { |
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301 | fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", |
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302 | initrd_filename); |
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303 | exit(1); |
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304 | } |
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305 | } |
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306 | if (initrd_size > 0) { |
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307 | for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) { |
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308 | if (ldl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i) |
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309 | == 0x48647253) { // HdrS |
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310 | stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR); |
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311 | stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 20, initrd_size); |
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312 | break; |
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313 | } |
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314 | } |
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315 | } |
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316 | } |
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317 | nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline, boot_device, ram_size, kernel_size, graphic_width, graphic_height, graphic_depth); |
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318 | } |
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319 | |
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320 | QEMUMachine sun4m_machine = { |
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321 | "sun4m", |
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322 | "Sun4m platform", |
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323 | sun4m_init, |
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324 | }; |
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