1 | /* |
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2 | * PIIX4 ACPI controller emulation |
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3 | * |
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4 | * Winston liwen Wang, winston.l.wang@intel.com |
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5 | * Copyright (c) 2006 , Intel Corporation. |
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6 | * |
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7 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
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8 | * of this software and associated documentation files (the "Software"), to deal |
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9 | * in the Software without restriction, including without limitation the rights |
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10 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
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11 | * copies of the Software, and to permit persons to whom the Software is |
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12 | * furnished to do so, subject to the following conditions: |
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13 | * |
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14 | * The above copyright notice and this permission notice shall be included in |
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15 | * all copies or substantial portions of the Software. |
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16 | * |
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17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
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22 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
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23 | * THE SOFTWARE. |
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24 | */ |
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25 | |
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26 | #include "vl.h" |
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27 | #define FREQUENCE_PMTIMER 3579545 |
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28 | /* acpi register bit define here */ |
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29 | |
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30 | /* PM1_STS */ |
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31 | #define TMROF_STS (1 << 0) |
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32 | #define BM_STS (1 << 4) |
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33 | #define GBL_STS (1 << 5) |
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34 | #define PWRBTN_STS (1 << 8) |
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35 | #define RTC_STS (1 << 10) |
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36 | #define PRBTNOR_STS (1 << 11) |
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37 | #define WAK_STS (1 << 15) |
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38 | /* PM1_EN */ |
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39 | #define TMROF_EN (1 << 0) |
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40 | #define GBL_EN (1 << 5) |
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41 | #define PWRBTN_EN (1 << 8) |
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42 | #define RTC_EN (1 << 10) |
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43 | /* PM1_CNT */ |
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44 | #define SCI_EN (1 << 0) |
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45 | #define GBL_RLS (1 << 2) |
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46 | #define SLP_EN (1 << 13) |
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47 | |
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48 | /* Bits of PM1a register define here */ |
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49 | #define SLP_TYP_MASK 0x1C00 |
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50 | #define SLP_VAL 0x1C00 |
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51 | |
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52 | typedef struct AcpiDeviceState AcpiDeviceState; |
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53 | AcpiDeviceState *acpi_device_table; |
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54 | |
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55 | typedef struct PCIAcpiState { |
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56 | PCIDevice dev; |
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57 | uint16_t pm1_control; /* pm1a_ECNT_BLK */ |
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58 | } PCIAcpiState; |
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59 | |
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60 | static void piix4acpi_save(QEMUFile *f, void *opaque) |
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61 | { |
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62 | PCIAcpiState *s = opaque; |
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63 | qemu_put_be16s(f, &s->pm1_control); |
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64 | } |
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65 | |
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66 | static int piix4acpi_load(QEMUFile *f, void *opaque, int version_id) |
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67 | { |
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68 | PCIAcpiState *s = opaque; |
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69 | if (version_id > 1) |
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70 | return -EINVAL; |
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71 | qemu_get_be16s(f, &s->pm1_control); |
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72 | } |
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73 | |
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74 | static void acpiPm1Control_writeb(void *opaque, uint32_t addr, uint32_t val) |
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75 | { |
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76 | PCIAcpiState *s = opaque; |
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77 | |
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78 | s->pm1_control = (s->pm1_control & 0xff00) | (val & 0xff); |
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79 | /* printf("acpiPm1Control_writeb \n addr %x val:%x\n", addr, val); */ |
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80 | |
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81 | } |
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82 | |
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83 | static uint32_t acpiPm1Control_readb(void *opaque, uint32_t addr) |
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84 | { |
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85 | PCIAcpiState *s = opaque; |
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86 | uint32_t val; |
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87 | |
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88 | /* Mask out the write-only bits */ |
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89 | val = s->pm1_control & ~(GBL_RLS|SLP_EN) & 0xff; |
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90 | /* printf("acpiPm1Control_readb \n addr %x val:%x\n", addr, val); */ |
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91 | |
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92 | return val; |
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93 | } |
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94 | |
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95 | static void acpiPm1ControlP1_writeb(void *opaque, uint32_t addr, uint32_t val) |
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96 | { |
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97 | PCIAcpiState *s = opaque; |
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98 | |
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99 | s->pm1_control = (s->pm1_control & 0xff) | (val << 8); |
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100 | /* printf("acpiPm1ControlP1_writeb \n addr %x val:%x\n", addr, val); */ |
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101 | |
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102 | // Check for power off request |
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103 | val <<= 8; |
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104 | if (((val & SLP_EN) != 0) && |
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105 | ((val & SLP_TYP_MASK) == SLP_VAL)) { |
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106 | qemu_system_shutdown_request(); |
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107 | } |
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108 | } |
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109 | |
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110 | static uint32_t acpiPm1ControlP1_readb(void *opaque, uint32_t addr) |
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111 | { |
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112 | PCIAcpiState *s = opaque; |
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113 | uint32_t val; |
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114 | |
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115 | /* Mask out the write-only bits */ |
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116 | val = (s->pm1_control & ~(GBL_RLS|SLP_EN)) >> 8; |
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117 | /* printf("acpiPm1ControlP1_readb \n addr %x val:%x\n", addr, val); */ |
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118 | |
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119 | return val; |
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120 | } |
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121 | |
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122 | |
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123 | /* word access */ |
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124 | |
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125 | static void acpiPm1Control_writew(void *opaque, uint32_t addr, uint32_t val) |
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126 | { |
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127 | PCIAcpiState *s = opaque; |
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128 | |
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129 | s->pm1_control = val; |
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130 | /* printf("acpiPm1Control_writew \n addr %x val:%x\n", addr, val); */ |
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131 | |
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132 | // Check for power off request |
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133 | |
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134 | if (((val & SLP_EN) != 0) && |
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135 | ((val & SLP_TYP_MASK) == SLP_VAL)) { |
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136 | qemu_system_shutdown_request(); |
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137 | } |
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138 | |
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139 | } |
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140 | |
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141 | static uint32_t acpiPm1Control_readw(void *opaque, uint32_t addr) |
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142 | { |
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143 | PCIAcpiState *s = opaque; |
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144 | uint32_t val; |
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145 | |
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146 | /* Mask out the write-only bits */ |
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147 | val = s->pm1_control & ~(GBL_RLS|SLP_EN); |
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148 | /* printf("acpiPm1Control_readw \n addr %x val:%x\n", addr, val); */ |
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149 | |
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150 | return val; |
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151 | } |
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152 | |
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153 | |
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154 | static void acpi_map(PCIDevice *pci_dev, int region_num, |
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155 | uint32_t addr, uint32_t size, int type) |
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156 | { |
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157 | PCIAcpiState *d = (PCIAcpiState *)pci_dev; |
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158 | |
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159 | printf("register acpi io\n"); |
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160 | |
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161 | /* Byte access */ |
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162 | register_ioport_write(addr + 4, 1, 1, acpiPm1Control_writeb, d); |
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163 | register_ioport_read(addr + 4, 1, 1, acpiPm1Control_readb, d); |
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164 | register_ioport_write(addr + 4 + 1, 1, 1, acpiPm1ControlP1_writeb, d); |
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165 | register_ioport_read(addr + 4 +1, 1, 1, acpiPm1ControlP1_readb, d); |
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166 | |
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167 | /* Word access */ |
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168 | register_ioport_write(addr + 4, 2, 2, acpiPm1Control_writew, d); |
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169 | register_ioport_read(addr + 4, 2, 2, acpiPm1Control_readw, d); |
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170 | } |
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171 | |
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172 | /* PIIX4 acpi pci configuration space, func 2 */ |
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173 | void pci_piix4_acpi_init(PCIBus *bus, int devfn) |
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174 | { |
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175 | PCIAcpiState *d; |
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176 | uint8_t *pci_conf; |
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177 | |
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178 | /* register a function 2 of PIIX4 */ |
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179 | d = (PCIAcpiState *)pci_register_device( |
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180 | bus, "PIIX4 ACPI", sizeof(PCIAcpiState), |
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181 | devfn, NULL, NULL); |
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182 | |
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183 | pci_conf = d->dev.config; |
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184 | pci_conf[0x00] = 0x86; /* Intel */ |
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185 | pci_conf[0x01] = 0x80; |
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186 | pci_conf[0x02] = 0x13; |
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187 | pci_conf[0x03] = 0x71; |
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188 | pci_conf[0x08] = 0x01; /* B0 stepping */ |
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189 | pci_conf[0x09] = 0x00; /* base class */ |
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190 | pci_conf[0x0a] = 0x80; /* Sub class */ |
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191 | pci_conf[0x0b] = 0x06; |
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192 | pci_conf[0x0e] = 0x00; |
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193 | pci_conf[0x3d] = 0x01; /* Hardwired to PIRQA is used */ |
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194 | |
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195 | |
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196 | /* PMBA POWER MANAGEMENT BASE ADDRESS, hardcoded to 0x1f40 |
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197 | * to make shutdown work for IPF, due to IPF Guest Firmware |
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198 | * will enumerate pci devices. |
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199 | * |
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200 | * TODO: if Guest Firmware or Guest OS will change this PMBA, |
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201 | * More logic will be added. |
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202 | */ |
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203 | pci_conf[0x40] = 0x41; /* Special device-specific BAR at 0x40 */ |
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204 | pci_conf[0x41] = 0x1f; |
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205 | pci_conf[0x42] = 0x00; |
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206 | pci_conf[0x43] = 0x00; |
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207 | d->pm1_control = SCI_EN; |
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208 | |
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209 | acpi_map(d, 0, 0x1f40, 0x10, PCI_ADDRESS_SPACE_IO); |
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210 | |
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211 | register_savevm("piix4acpi", 0, 1, piix4acpi_save, piix4acpi_load, d); |
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212 | register_savevm("piix4acpi_pci", 0, 1, generic_pci_save, generic_pci_load, |
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213 | &d->dev); |
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214 | } |
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