[34] | 1 | /* |
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| 2 | * CFI parallel flash with AMD command set emulation |
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| 3 | * |
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| 4 | * Copyright (c) 2005 Jocelyn Mayer |
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| 5 | * |
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| 6 | * This library is free software; you can redistribute it and/or |
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| 7 | * modify it under the terms of the GNU Lesser General Public |
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| 8 | * License as published by the Free Software Foundation; either |
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| 9 | * version 2 of the License, or (at your option) any later version. |
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| 10 | * |
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| 11 | * This library is distributed in the hope that it will be useful, |
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| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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| 14 | * Lesser General Public License for more details. |
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| 15 | * |
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| 16 | * You should have received a copy of the GNU Lesser General Public |
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| 17 | * License along with this library; if not, write to the Free Software |
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| 18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
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| 19 | */ |
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| 20 | |
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| 21 | /* |
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| 22 | * For now, this code can emulate flashes of 1, 2 or 4 bytes width. |
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| 23 | * Supported commands/modes are: |
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| 24 | * - flash read |
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| 25 | * - flash write |
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| 26 | * - flash ID read |
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| 27 | * - sector erase |
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| 28 | * - chip erase |
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| 29 | * - unlock bypass command |
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| 30 | * - CFI queries |
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| 31 | * |
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| 32 | * It does not support flash interleaving. |
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| 33 | * It does not implement boot blocs with reduced size |
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| 34 | * It does not implement software data protection as found in many real chips |
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| 35 | * It does not implement erase suspend/resume commands |
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| 36 | * It does not implement multiple sectors erase |
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| 37 | */ |
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| 38 | |
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| 39 | #include "vl.h" |
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| 40 | |
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| 41 | //#define PFLASH_DEBUG |
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| 42 | #ifdef PFLASH_DEBUG |
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| 43 | #define DPRINTF(fmt, args...) \ |
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| 44 | do { \ |
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| 45 | printf("PFLASH: " fmt , ##args); \ |
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| 46 | } while (0) |
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| 47 | #else |
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| 48 | #define DPRINTF(fmt, args...) do { } while (0) |
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| 49 | #endif |
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| 50 | |
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| 51 | struct pflash_t { |
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| 52 | BlockDriverState *bs; |
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| 53 | target_ulong base; |
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| 54 | target_ulong sector_len; |
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| 55 | target_ulong total_len; |
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| 56 | int width; |
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| 57 | int wcycle; /* if 0, the flash is read normally */ |
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| 58 | int bypass; |
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| 59 | int ro; |
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| 60 | uint8_t cmd; |
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| 61 | uint8_t status; |
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| 62 | uint16_t ident[4]; |
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| 63 | uint8_t cfi_len; |
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| 64 | uint8_t cfi_table[0x52]; |
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| 65 | QEMUTimer *timer; |
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| 66 | ram_addr_t off; |
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| 67 | int fl_mem; |
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| 68 | void *storage; |
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| 69 | }; |
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| 70 | |
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| 71 | static void pflash_timer (void *opaque) |
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| 72 | { |
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| 73 | pflash_t *pfl = opaque; |
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| 74 | |
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| 75 | DPRINTF("%s: command %02x done\n", __func__, pfl->cmd); |
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| 76 | /* Reset flash */ |
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| 77 | pfl->status ^= 0x80; |
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| 78 | if (pfl->bypass) { |
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| 79 | pfl->wcycle = 2; |
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| 80 | } else { |
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| 81 | cpu_register_physical_memory(pfl->base, pfl->total_len, |
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| 82 | pfl->off | IO_MEM_ROMD | pfl->fl_mem); |
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| 83 | pfl->wcycle = 0; |
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| 84 | } |
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| 85 | pfl->cmd = 0; |
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| 86 | } |
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| 87 | |
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| 88 | static uint32_t pflash_read (pflash_t *pfl, target_ulong offset, int width) |
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| 89 | { |
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| 90 | target_ulong boff; |
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| 91 | uint32_t ret; |
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| 92 | uint8_t *p; |
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| 93 | |
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| 94 | DPRINTF("%s: offset %08x\n", __func__, offset); |
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| 95 | ret = -1; |
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| 96 | offset -= pfl->base; |
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| 97 | boff = offset & 0xFF; |
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| 98 | if (pfl->width == 2) |
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| 99 | boff = boff >> 1; |
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| 100 | else if (pfl->width == 4) |
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| 101 | boff = boff >> 2; |
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| 102 | switch (pfl->cmd) { |
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| 103 | default: |
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| 104 | /* This should never happen : reset state & treat it as a read*/ |
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| 105 | DPRINTF("%s: unknown command state: %x\n", __func__, pfl->cmd); |
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| 106 | pfl->wcycle = 0; |
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| 107 | pfl->cmd = 0; |
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| 108 | case 0x80: |
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| 109 | /* We accept reads during second unlock sequence... */ |
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| 110 | case 0x00: |
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| 111 | flash_read: |
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| 112 | /* Flash area read */ |
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| 113 | p = pfl->storage; |
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| 114 | switch (width) { |
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| 115 | case 1: |
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| 116 | ret = p[offset]; |
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| 117 | // DPRINTF("%s: data offset %08x %02x\n", __func__, offset, ret); |
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| 118 | break; |
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| 119 | case 2: |
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| 120 | #if defined(TARGET_WORDS_BIGENDIAN) |
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| 121 | ret = p[offset] << 8; |
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| 122 | ret |= p[offset + 1]; |
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| 123 | #else |
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| 124 | ret = p[offset]; |
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| 125 | ret |= p[offset + 1] << 8; |
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| 126 | #endif |
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| 127 | // DPRINTF("%s: data offset %08x %04x\n", __func__, offset, ret); |
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| 128 | break; |
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| 129 | case 4: |
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| 130 | #if defined(TARGET_WORDS_BIGENDIAN) |
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| 131 | ret = p[offset] << 24; |
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| 132 | ret |= p[offset + 1] << 16; |
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| 133 | ret |= p[offset + 2] << 8; |
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| 134 | ret |= p[offset + 3]; |
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| 135 | #else |
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| 136 | ret = p[offset]; |
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| 137 | ret |= p[offset + 1] << 8; |
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| 138 | ret |= p[offset + 1] << 8; |
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| 139 | ret |= p[offset + 2] << 16; |
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| 140 | ret |= p[offset + 3] << 24; |
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| 141 | #endif |
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| 142 | // DPRINTF("%s: data offset %08x %08x\n", __func__, offset, ret); |
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| 143 | break; |
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| 144 | } |
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| 145 | break; |
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| 146 | case 0x90: |
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| 147 | /* flash ID read */ |
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| 148 | switch (boff) { |
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| 149 | case 0x00: |
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| 150 | case 0x01: |
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| 151 | ret = pfl->ident[boff & 0x01]; |
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| 152 | break; |
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| 153 | case 0x02: |
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| 154 | ret = 0x00; /* Pretend all sectors are unprotected */ |
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| 155 | break; |
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| 156 | case 0x0E: |
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| 157 | case 0x0F: |
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| 158 | if (pfl->ident[2 + (boff & 0x01)] == (uint8_t)-1) |
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| 159 | goto flash_read; |
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| 160 | ret = pfl->ident[2 + (boff & 0x01)]; |
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| 161 | break; |
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| 162 | default: |
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| 163 | goto flash_read; |
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| 164 | } |
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| 165 | DPRINTF("%s: ID %d %x\n", __func__, boff, ret); |
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| 166 | break; |
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| 167 | case 0xA0: |
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| 168 | case 0x10: |
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| 169 | case 0x30: |
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| 170 | /* Status register read */ |
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| 171 | ret = pfl->status; |
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| 172 | DPRINTF("%s: status %x\n", __func__, ret); |
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| 173 | /* Toggle bit 6 */ |
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| 174 | pfl->status ^= 0x40; |
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| 175 | break; |
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| 176 | case 0x98: |
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| 177 | /* CFI query mode */ |
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| 178 | if (boff > pfl->cfi_len) |
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| 179 | ret = 0; |
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| 180 | else |
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| 181 | ret = pfl->cfi_table[boff]; |
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| 182 | break; |
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| 183 | } |
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| 184 | |
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| 185 | return ret; |
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| 186 | } |
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| 187 | |
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| 188 | /* update flash content on disk */ |
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| 189 | static void pflash_update(pflash_t *pfl, int offset, |
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| 190 | int size) |
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| 191 | { |
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| 192 | int offset_end; |
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| 193 | if (pfl->bs) { |
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| 194 | offset_end = offset + size; |
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| 195 | /* round to sectors */ |
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| 196 | offset = offset >> 9; |
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| 197 | offset_end = (offset_end + 511) >> 9; |
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| 198 | bdrv_write(pfl->bs, offset, pfl->storage + (offset << 9), |
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| 199 | offset_end - offset); |
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| 200 | } |
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| 201 | } |
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| 202 | |
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| 203 | static void pflash_write (pflash_t *pfl, target_ulong offset, uint32_t value, |
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| 204 | int width) |
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| 205 | { |
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| 206 | target_ulong boff; |
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| 207 | uint8_t *p; |
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| 208 | uint8_t cmd; |
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| 209 | |
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| 210 | /* WARNING: when the memory area is in ROMD mode, the offset is a |
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| 211 | ram offset, not a physical address */ |
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| 212 | if (pfl->wcycle == 0) |
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| 213 | offset -= (target_ulong)(long)pfl->storage; |
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| 214 | else |
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| 215 | offset -= pfl->base; |
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| 216 | |
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| 217 | cmd = value; |
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| 218 | DPRINTF("%s: offset %08x %08x %d\n", __func__, offset, value, width); |
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| 219 | if (pfl->cmd != 0xA0 && cmd == 0xF0) { |
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| 220 | DPRINTF("%s: flash reset asked (%02x %02x)\n", |
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| 221 | __func__, pfl->cmd, cmd); |
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| 222 | goto reset_flash; |
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| 223 | } |
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| 224 | /* Set the device in I/O access mode */ |
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| 225 | cpu_register_physical_memory(pfl->base, pfl->total_len, pfl->fl_mem); |
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| 226 | boff = offset & (pfl->sector_len - 1); |
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| 227 | if (pfl->width == 2) |
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| 228 | boff = boff >> 1; |
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| 229 | else if (pfl->width == 4) |
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| 230 | boff = boff >> 2; |
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| 231 | switch (pfl->wcycle) { |
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| 232 | case 0: |
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| 233 | /* We're in read mode */ |
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| 234 | check_unlock0: |
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| 235 | if (boff == 0x55 && cmd == 0x98) { |
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| 236 | enter_CFI_mode: |
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| 237 | /* Enter CFI query mode */ |
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| 238 | pfl->wcycle = 7; |
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| 239 | pfl->cmd = 0x98; |
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| 240 | return; |
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| 241 | } |
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| 242 | if (boff != 0x555 || cmd != 0xAA) { |
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| 243 | DPRINTF("%s: unlock0 failed %04x %02x %04x\n", |
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| 244 | __func__, boff, cmd, 0x555); |
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| 245 | goto reset_flash; |
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| 246 | } |
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| 247 | DPRINTF("%s: unlock sequence started\n", __func__); |
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| 248 | break; |
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| 249 | case 1: |
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| 250 | /* We started an unlock sequence */ |
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| 251 | check_unlock1: |
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| 252 | if (boff != 0x2AA || cmd != 0x55) { |
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| 253 | DPRINTF("%s: unlock1 failed %04x %02x\n", __func__, boff, cmd); |
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| 254 | goto reset_flash; |
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| 255 | } |
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| 256 | DPRINTF("%s: unlock sequence done\n", __func__); |
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| 257 | break; |
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| 258 | case 2: |
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| 259 | /* We finished an unlock sequence */ |
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| 260 | if (!pfl->bypass && boff != 0x555) { |
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| 261 | DPRINTF("%s: command failed %04x %02x\n", __func__, boff, cmd); |
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| 262 | goto reset_flash; |
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| 263 | } |
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| 264 | switch (cmd) { |
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| 265 | case 0x20: |
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| 266 | pfl->bypass = 1; |
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| 267 | goto do_bypass; |
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| 268 | case 0x80: |
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| 269 | case 0x90: |
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| 270 | case 0xA0: |
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| 271 | pfl->cmd = cmd; |
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| 272 | DPRINTF("%s: starting command %02x\n", __func__, cmd); |
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| 273 | break; |
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| 274 | default: |
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| 275 | DPRINTF("%s: unknown command %02x\n", __func__, cmd); |
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| 276 | goto reset_flash; |
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| 277 | } |
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| 278 | break; |
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| 279 | case 3: |
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| 280 | switch (pfl->cmd) { |
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| 281 | case 0x80: |
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| 282 | /* We need another unlock sequence */ |
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| 283 | goto check_unlock0; |
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| 284 | case 0xA0: |
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| 285 | DPRINTF("%s: write data offset %08x %08x %d\n", |
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| 286 | __func__, offset, value, width); |
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| 287 | p = pfl->storage; |
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| 288 | switch (width) { |
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| 289 | case 1: |
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| 290 | p[offset] &= value; |
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| 291 | pflash_update(pfl, offset, 1); |
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| 292 | break; |
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| 293 | case 2: |
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| 294 | #if defined(TARGET_WORDS_BIGENDIAN) |
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| 295 | p[offset] &= value >> 8; |
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| 296 | p[offset + 1] &= value; |
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| 297 | #else |
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| 298 | p[offset] &= value; |
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| 299 | p[offset + 1] &= value >> 8; |
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| 300 | #endif |
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| 301 | pflash_update(pfl, offset, 2); |
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| 302 | break; |
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| 303 | case 4: |
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| 304 | #if defined(TARGET_WORDS_BIGENDIAN) |
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| 305 | p[offset] &= value >> 24; |
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| 306 | p[offset + 1] &= value >> 16; |
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| 307 | p[offset + 2] &= value >> 8; |
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| 308 | p[offset + 3] &= value; |
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| 309 | #else |
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| 310 | p[offset] &= value; |
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| 311 | p[offset + 1] &= value >> 8; |
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| 312 | p[offset + 2] &= value >> 16; |
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| 313 | p[offset + 3] &= value >> 24; |
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| 314 | #endif |
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| 315 | pflash_update(pfl, offset, 4); |
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| 316 | break; |
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| 317 | } |
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| 318 | pfl->status = 0x00 | ~(value & 0x80); |
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| 319 | /* Let's pretend write is immediate */ |
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| 320 | if (pfl->bypass) |
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| 321 | goto do_bypass; |
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| 322 | goto reset_flash; |
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| 323 | case 0x90: |
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| 324 | if (pfl->bypass && cmd == 0x00) { |
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| 325 | /* Unlock bypass reset */ |
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| 326 | goto reset_flash; |
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| 327 | } |
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| 328 | /* We can enter CFI query mode from autoselect mode */ |
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| 329 | if (boff == 0x55 && cmd == 0x98) |
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| 330 | goto enter_CFI_mode; |
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| 331 | /* No break here */ |
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| 332 | default: |
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| 333 | DPRINTF("%s: invalid write for command %02x\n", |
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| 334 | __func__, pfl->cmd); |
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| 335 | goto reset_flash; |
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| 336 | } |
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| 337 | case 4: |
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| 338 | switch (pfl->cmd) { |
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| 339 | case 0xA0: |
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| 340 | /* Ignore writes while flash data write is occuring */ |
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| 341 | /* As we suppose write is immediate, this should never happen */ |
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| 342 | return; |
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| 343 | case 0x80: |
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| 344 | goto check_unlock1; |
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| 345 | default: |
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| 346 | /* Should never happen */ |
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| 347 | DPRINTF("%s: invalid command state %02x (wc 4)\n", |
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| 348 | __func__, pfl->cmd); |
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| 349 | goto reset_flash; |
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| 350 | } |
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| 351 | break; |
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| 352 | case 5: |
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| 353 | switch (cmd) { |
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| 354 | case 0x10: |
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| 355 | if (boff != 0x555) { |
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| 356 | DPRINTF("%s: chip erase: invalid address %04x\n", |
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| 357 | __func__, offset); |
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| 358 | goto reset_flash; |
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| 359 | } |
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| 360 | /* Chip erase */ |
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| 361 | DPRINTF("%s: start chip erase\n", __func__); |
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| 362 | memset(pfl->storage, 0xFF, pfl->total_len); |
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| 363 | pfl->status = 0x00; |
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| 364 | pflash_update(pfl, 0, pfl->total_len); |
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| 365 | /* Let's wait 5 seconds before chip erase is done */ |
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| 366 | qemu_mod_timer(pfl->timer, |
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| 367 | qemu_get_clock(vm_clock) + (ticks_per_sec * 5)); |
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| 368 | break; |
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| 369 | case 0x30: |
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| 370 | /* Sector erase */ |
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| 371 | p = pfl->storage; |
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| 372 | offset &= ~(pfl->sector_len - 1); |
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| 373 | DPRINTF("%s: start sector erase at %08x\n", __func__, offset); |
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| 374 | memset(p + offset, 0xFF, pfl->sector_len); |
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| 375 | pflash_update(pfl, offset, pfl->sector_len); |
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| 376 | pfl->status = 0x00; |
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| 377 | /* Let's wait 1/2 second before sector erase is done */ |
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| 378 | qemu_mod_timer(pfl->timer, |
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| 379 | qemu_get_clock(vm_clock) + (ticks_per_sec / 2)); |
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| 380 | break; |
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| 381 | default: |
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| 382 | DPRINTF("%s: invalid command %02x (wc 5)\n", __func__, cmd); |
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| 383 | goto reset_flash; |
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| 384 | } |
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| 385 | pfl->cmd = cmd; |
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| 386 | break; |
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| 387 | case 6: |
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| 388 | switch (pfl->cmd) { |
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| 389 | case 0x10: |
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| 390 | /* Ignore writes during chip erase */ |
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| 391 | return; |
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| 392 | case 0x30: |
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| 393 | /* Ignore writes during sector erase */ |
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| 394 | return; |
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| 395 | default: |
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| 396 | /* Should never happen */ |
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| 397 | DPRINTF("%s: invalid command state %02x (wc 6)\n", |
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| 398 | __func__, pfl->cmd); |
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| 399 | goto reset_flash; |
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| 400 | } |
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| 401 | break; |
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| 402 | case 7: /* Special value for CFI queries */ |
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| 403 | DPRINTF("%s: invalid write in CFI query mode\n", __func__); |
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| 404 | goto reset_flash; |
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| 405 | default: |
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| 406 | /* Should never happen */ |
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| 407 | DPRINTF("%s: invalid write state (wc 7)\n", __func__); |
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| 408 | goto reset_flash; |
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| 409 | } |
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| 410 | pfl->wcycle++; |
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| 411 | |
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| 412 | return; |
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| 413 | |
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| 414 | /* Reset flash */ |
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| 415 | reset_flash: |
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| 416 | if (pfl->wcycle != 0) { |
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| 417 | cpu_register_physical_memory(pfl->base, pfl->total_len, |
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| 418 | pfl->off | IO_MEM_ROMD | pfl->fl_mem); |
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| 419 | } |
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| 420 | pfl->bypass = 0; |
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| 421 | pfl->wcycle = 0; |
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| 422 | pfl->cmd = 0; |
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| 423 | return; |
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| 424 | |
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| 425 | do_bypass: |
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| 426 | pfl->wcycle = 2; |
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| 427 | pfl->cmd = 0; |
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| 428 | return; |
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| 429 | } |
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| 430 | |
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| 431 | |
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| 432 | static uint32_t pflash_readb (void *opaque, target_phys_addr_t addr) |
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| 433 | { |
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| 434 | return pflash_read(opaque, addr, 1); |
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| 435 | } |
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| 436 | |
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| 437 | static uint32_t pflash_readw (void *opaque, target_phys_addr_t addr) |
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| 438 | { |
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| 439 | pflash_t *pfl = opaque; |
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| 440 | |
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| 441 | return pflash_read(pfl, addr, 2); |
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| 442 | } |
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| 443 | |
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| 444 | static uint32_t pflash_readl (void *opaque, target_phys_addr_t addr) |
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| 445 | { |
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| 446 | pflash_t *pfl = opaque; |
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| 447 | |
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| 448 | return pflash_read(pfl, addr, 4); |
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| 449 | } |
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| 450 | |
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| 451 | static void pflash_writeb (void *opaque, target_phys_addr_t addr, |
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| 452 | uint32_t value) |
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| 453 | { |
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| 454 | pflash_write(opaque, addr, value, 1); |
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| 455 | } |
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| 456 | |
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| 457 | static void pflash_writew (void *opaque, target_phys_addr_t addr, |
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| 458 | uint32_t value) |
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| 459 | { |
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| 460 | pflash_t *pfl = opaque; |
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| 461 | |
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| 462 | pflash_write(pfl, addr, value, 2); |
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| 463 | } |
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| 464 | |
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| 465 | static void pflash_writel (void *opaque, target_phys_addr_t addr, |
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| 466 | uint32_t value) |
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| 467 | { |
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| 468 | pflash_t *pfl = opaque; |
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| 469 | |
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| 470 | pflash_write(pfl, addr, value, 4); |
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| 471 | } |
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| 472 | |
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| 473 | static CPUWriteMemoryFunc *pflash_write_ops[] = { |
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| 474 | &pflash_writeb, |
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| 475 | &pflash_writew, |
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| 476 | &pflash_writel, |
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| 477 | }; |
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| 478 | |
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| 479 | static CPUReadMemoryFunc *pflash_read_ops[] = { |
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| 480 | &pflash_readb, |
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| 481 | &pflash_readw, |
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| 482 | &pflash_readl, |
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| 483 | }; |
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| 484 | |
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| 485 | /* Count trailing zeroes of a 32 bits quantity */ |
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| 486 | static int ctz32 (uint32_t n) |
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| 487 | { |
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| 488 | int ret; |
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| 489 | |
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| 490 | ret = 0; |
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| 491 | if (!(n & 0xFFFF)) { |
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| 492 | ret += 16; |
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| 493 | n = n >> 16; |
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| 494 | } |
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| 495 | if (!(n & 0xFF)) { |
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| 496 | ret += 8; |
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| 497 | n = n >> 8; |
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| 498 | } |
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| 499 | if (!(n & 0xF)) { |
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| 500 | ret += 4; |
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| 501 | n = n >> 4; |
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| 502 | } |
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| 503 | if (!(n & 0x3)) { |
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| 504 | ret += 2; |
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| 505 | n = n >> 2; |
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| 506 | } |
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| 507 | if (!(n & 0x1)) { |
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| 508 | ret++; |
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| 509 | n = n >> 1; |
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| 510 | } |
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| 511 | #if 0 /* This is not necessary as n is never 0 */ |
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| 512 | if (!n) |
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| 513 | ret++; |
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| 514 | #endif |
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| 515 | |
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| 516 | return ret; |
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| 517 | } |
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| 518 | |
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| 519 | pflash_t *pflash_register (target_ulong base, ram_addr_t off, |
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| 520 | BlockDriverState *bs, |
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| 521 | target_ulong sector_len, int nb_blocs, int width, |
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| 522 | uint16_t id0, uint16_t id1, |
---|
| 523 | uint16_t id2, uint16_t id3) |
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| 524 | { |
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| 525 | pflash_t *pfl; |
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| 526 | target_long total_len; |
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| 527 | |
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| 528 | total_len = sector_len * nb_blocs; |
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| 529 | /* XXX: to be fixed */ |
---|
| 530 | if (total_len != (8 * 1024 * 1024) && total_len != (16 * 1024 * 1024) && |
---|
| 531 | total_len != (32 * 1024 * 1024) && total_len != (64 * 1024 * 1024)) |
---|
| 532 | return NULL; |
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| 533 | pfl = qemu_mallocz(sizeof(pflash_t)); |
---|
| 534 | if (pfl == NULL) |
---|
| 535 | return NULL; |
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| 536 | pfl->storage = phys_ram_base + off; |
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| 537 | pfl->fl_mem = cpu_register_io_memory(0, pflash_read_ops, pflash_write_ops, pfl); |
---|
| 538 | pfl->off = off; |
---|
| 539 | cpu_register_physical_memory(base, total_len, |
---|
| 540 | off | pfl->fl_mem | IO_MEM_ROMD); |
---|
| 541 | pfl->bs = bs; |
---|
| 542 | if (pfl->bs) { |
---|
| 543 | /* read the initial flash content */ |
---|
| 544 | bdrv_read(pfl->bs, 0, pfl->storage, total_len >> 9); |
---|
| 545 | } |
---|
| 546 | #if 0 /* XXX: there should be a bit to set up read-only, |
---|
| 547 | * the same way the hardware does (with WP pin). |
---|
| 548 | */ |
---|
| 549 | pfl->ro = 1; |
---|
| 550 | #else |
---|
| 551 | pfl->ro = 0; |
---|
| 552 | #endif |
---|
| 553 | pfl->timer = qemu_new_timer(vm_clock, pflash_timer, pfl); |
---|
| 554 | pfl->base = base; |
---|
| 555 | pfl->sector_len = sector_len; |
---|
| 556 | pfl->total_len = total_len; |
---|
| 557 | pfl->width = width; |
---|
| 558 | pfl->wcycle = 0; |
---|
| 559 | pfl->cmd = 0; |
---|
| 560 | pfl->status = 0; |
---|
| 561 | pfl->ident[0] = id0; |
---|
| 562 | pfl->ident[1] = id1; |
---|
| 563 | pfl->ident[2] = id2; |
---|
| 564 | pfl->ident[3] = id3; |
---|
| 565 | /* Hardcoded CFI table (mostly from SG29 Spansion flash) */ |
---|
| 566 | pfl->cfi_len = 0x52; |
---|
| 567 | /* Standard "QRY" string */ |
---|
| 568 | pfl->cfi_table[0x10] = 'Q'; |
---|
| 569 | pfl->cfi_table[0x11] = 'R'; |
---|
| 570 | pfl->cfi_table[0x12] = 'Y'; |
---|
| 571 | /* Command set (AMD/Fujitsu) */ |
---|
| 572 | pfl->cfi_table[0x13] = 0x02; |
---|
| 573 | pfl->cfi_table[0x14] = 0x00; |
---|
| 574 | /* Primary extended table address (none) */ |
---|
| 575 | pfl->cfi_table[0x15] = 0x00; |
---|
| 576 | pfl->cfi_table[0x16] = 0x00; |
---|
| 577 | /* Alternate command set (none) */ |
---|
| 578 | pfl->cfi_table[0x17] = 0x00; |
---|
| 579 | pfl->cfi_table[0x18] = 0x00; |
---|
| 580 | /* Alternate extended table (none) */ |
---|
| 581 | pfl->cfi_table[0x19] = 0x00; |
---|
| 582 | pfl->cfi_table[0x1A] = 0x00; |
---|
| 583 | /* Vcc min */ |
---|
| 584 | pfl->cfi_table[0x1B] = 0x27; |
---|
| 585 | /* Vcc max */ |
---|
| 586 | pfl->cfi_table[0x1C] = 0x36; |
---|
| 587 | /* Vpp min (no Vpp pin) */ |
---|
| 588 | pfl->cfi_table[0x1D] = 0x00; |
---|
| 589 | /* Vpp max (no Vpp pin) */ |
---|
| 590 | pfl->cfi_table[0x1E] = 0x00; |
---|
| 591 | /* Reserved */ |
---|
| 592 | pfl->cfi_table[0x1F] = 0x07; |
---|
| 593 | /* Timeout for min size buffer write (16 µs) */ |
---|
| 594 | pfl->cfi_table[0x20] = 0x04; |
---|
| 595 | /* Typical timeout for block erase (512 ms) */ |
---|
| 596 | pfl->cfi_table[0x21] = 0x09; |
---|
| 597 | /* Typical timeout for full chip erase (4096 ms) */ |
---|
| 598 | pfl->cfi_table[0x22] = 0x0C; |
---|
| 599 | /* Reserved */ |
---|
| 600 | pfl->cfi_table[0x23] = 0x01; |
---|
| 601 | /* Max timeout for buffer write */ |
---|
| 602 | pfl->cfi_table[0x24] = 0x04; |
---|
| 603 | /* Max timeout for block erase */ |
---|
| 604 | pfl->cfi_table[0x25] = 0x0A; |
---|
| 605 | /* Max timeout for chip erase */ |
---|
| 606 | pfl->cfi_table[0x26] = 0x0D; |
---|
| 607 | /* Device size */ |
---|
| 608 | pfl->cfi_table[0x27] = ctz32(total_len) + 1; |
---|
| 609 | /* Flash device interface (8 & 16 bits) */ |
---|
| 610 | pfl->cfi_table[0x28] = 0x02; |
---|
| 611 | pfl->cfi_table[0x29] = 0x00; |
---|
| 612 | /* Max number of bytes in multi-bytes write */ |
---|
| 613 | pfl->cfi_table[0x2A] = 0x05; |
---|
| 614 | pfl->cfi_table[0x2B] = 0x00; |
---|
| 615 | /* Number of erase block regions (uniform) */ |
---|
| 616 | pfl->cfi_table[0x2C] = 0x01; |
---|
| 617 | /* Erase block region 1 */ |
---|
| 618 | pfl->cfi_table[0x2D] = nb_blocs - 1; |
---|
| 619 | pfl->cfi_table[0x2E] = (nb_blocs - 1) >> 8; |
---|
| 620 | pfl->cfi_table[0x2F] = sector_len >> 8; |
---|
| 621 | pfl->cfi_table[0x30] = sector_len >> 16; |
---|
| 622 | |
---|
| 623 | return pfl; |
---|
| 624 | } |
---|