| 1 | /****************************************************************************** |
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| 2 | * |
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| 3 | * Name: actbl1.h - ACPI 1.0 tables |
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| 4 | * |
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| 5 | *****************************************************************************/ |
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| 6 | |
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| 7 | /* |
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| 8 | * Copyright (C) 2000 - 2005, R. Byron Moore |
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| 9 | * All rights reserved. |
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| 10 | * |
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| 11 | * Redistribution and use in source and binary forms, with or without |
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| 12 | * modification, are permitted provided that the following conditions |
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| 13 | * are met: |
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| 14 | * 1. Redistributions of source code must retain the above copyright |
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| 15 | * notice, this list of conditions, and the following disclaimer, |
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| 16 | * without modification. |
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| 17 | * 2. Redistributions in binary form must reproduce at minimum a disclaimer |
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| 18 | * substantially similar to the "NO WARRANTY" disclaimer below |
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| 19 | * ("Disclaimer") and any redistribution must be conditioned upon |
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| 20 | * including a substantially similar Disclaimer requirement for further |
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| 21 | * binary redistribution. |
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| 22 | * 3. Neither the names of the above-listed copyright holders nor the names |
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| 23 | * of any contributors may be used to endorse or promote products derived |
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| 24 | * from this software without specific prior written permission. |
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| 25 | * |
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| 26 | * Alternatively, this software may be distributed under the terms of the |
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| 27 | * GNU General Public License ("GPL") version 2 as published by the Free |
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| 28 | * Software Foundation. |
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| 29 | * |
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| 30 | * NO WARRANTY |
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| 31 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
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| 32 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
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| 33 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR |
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| 34 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT |
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| 35 | * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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| 36 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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| 37 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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| 38 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, |
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| 39 | * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING |
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| 40 | * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
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| 41 | * POSSIBILITY OF SUCH DAMAGES. |
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| 42 | */ |
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| 43 | |
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| 44 | #ifndef __ACTBL1_H__ |
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| 45 | #define __ACTBL1_H__ |
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| 46 | |
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| 47 | #pragma pack(1) |
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| 48 | |
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| 49 | /* |
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| 50 | * ACPI 1.0 Root System Description Table (RSDT) |
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| 51 | */ |
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| 52 | struct rsdt_descriptor_rev1 |
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| 53 | { |
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| 54 | ACPI_TABLE_HEADER_DEF /* ACPI common table header */ |
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| 55 | u32 table_offset_entry [1]; /* Array of pointers to other */ |
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| 56 | /* ACPI tables */ |
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| 57 | }; |
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| 58 | |
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| 59 | |
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| 60 | /* |
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| 61 | * ACPI 1.0 Firmware ACPI Control Structure (FACS) |
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| 62 | */ |
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| 63 | struct facs_descriptor_rev1 |
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| 64 | { |
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| 65 | char signature[4]; /* ACPI Signature */ |
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| 66 | u32 length; /* Length of structure, in bytes */ |
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| 67 | u32 hardware_signature; /* Hardware configuration signature */ |
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| 68 | u32 firmware_waking_vector; /* ACPI OS waking vector */ |
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| 69 | u32 global_lock; /* Global Lock */ |
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| 70 | u32 S4bios_f : 1; /* Indicates if S4BIOS support is present */ |
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| 71 | u32 reserved1 : 31; /* Must be 0 */ |
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| 72 | u8 resverved3 [40]; /* Reserved - must be zero */ |
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| 73 | }; |
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| 74 | |
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| 75 | |
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| 76 | /* |
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| 77 | * ACPI 1.0 Fixed ACPI Description Table (FADT) |
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| 78 | */ |
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| 79 | struct fadt_descriptor_rev1 |
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| 80 | { |
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| 81 | ACPI_TABLE_HEADER_DEF /* ACPI common table header */ |
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| 82 | u32 firmware_ctrl; /* Physical address of FACS */ |
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| 83 | u32 dsdt; /* Physical address of DSDT */ |
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| 84 | u8 model; /* System Interrupt Model */ |
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| 85 | u8 reserved1; /* Reserved */ |
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| 86 | u16 sci_int; /* System vector of SCI interrupt */ |
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| 87 | u32 smi_cmd; /* Port address of SMI command port */ |
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| 88 | u8 acpi_enable; /* Value to write to smi_cmd to enable ACPI */ |
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| 89 | u8 acpi_disable; /* Value to write to smi_cmd to disable ACPI */ |
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| 90 | u8 S4bios_req; /* Value to write to SMI CMD to enter S4BIOS state */ |
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| 91 | u8 reserved2; /* Reserved - must be zero */ |
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| 92 | u32 pm1a_evt_blk; /* Port address of Power Mgt 1a acpi_event Reg Blk */ |
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| 93 | u32 pm1b_evt_blk; /* Port address of Power Mgt 1b acpi_event Reg Blk */ |
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| 94 | u32 pm1a_cnt_blk; /* Port address of Power Mgt 1a Control Reg Blk */ |
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| 95 | u32 pm1b_cnt_blk; /* Port address of Power Mgt 1b Control Reg Blk */ |
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| 96 | u32 pm2_cnt_blk; /* Port address of Power Mgt 2 Control Reg Blk */ |
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| 97 | u32 pm_tmr_blk; /* Port address of Power Mgt Timer Ctrl Reg Blk */ |
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| 98 | u32 gpe0_blk; /* Port addr of General Purpose acpi_event 0 Reg Blk */ |
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| 99 | u32 gpe1_blk; /* Port addr of General Purpose acpi_event 1 Reg Blk */ |
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| 100 | u8 pm1_evt_len; /* Byte length of ports at pm1_x_evt_blk */ |
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| 101 | u8 pm1_cnt_len; /* Byte length of ports at pm1_x_cnt_blk */ |
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| 102 | u8 pm2_cnt_len; /* Byte Length of ports at pm2_cnt_blk */ |
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| 103 | u8 pm_tm_len; /* Byte Length of ports at pm_tm_blk */ |
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| 104 | u8 gpe0_blk_len; /* Byte Length of ports at gpe0_blk */ |
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| 105 | u8 gpe1_blk_len; /* Byte Length of ports at gpe1_blk */ |
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| 106 | u8 gpe1_base; /* Offset in gpe model where gpe1 events start */ |
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| 107 | u8 reserved3; /* Reserved */ |
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| 108 | u16 plvl2_lat; /* Worst case HW latency to enter/exit C2 state */ |
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| 109 | u16 plvl3_lat; /* Worst case HW latency to enter/exit C3 state */ |
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| 110 | u16 flush_size; /* Size of area read to flush caches */ |
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| 111 | u16 flush_stride; /* Stride used in flushing caches */ |
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| 112 | u8 duty_offset; /* Bit location of duty cycle field in p_cnt reg */ |
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| 113 | u8 duty_width; /* Bit width of duty cycle field in p_cnt reg */ |
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| 114 | u8 day_alrm; /* Index to day-of-month alarm in RTC CMOS RAM */ |
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| 115 | u8 mon_alrm; /* Index to month-of-year alarm in RTC CMOS RAM */ |
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| 116 | u8 century; /* Index to century in RTC CMOS RAM */ |
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| 117 | u8 reserved4; /* Reserved */ |
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| 118 | u8 reserved4a; /* Reserved */ |
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| 119 | u8 reserved4b; /* Reserved */ |
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| 120 | u32 wb_invd : 1; /* The wbinvd instruction works properly */ |
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| 121 | u32 wb_invd_flush : 1; /* The wbinvd flushes but does not invalidate */ |
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| 122 | u32 proc_c1 : 1; /* All processors support C1 state */ |
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| 123 | u32 plvl2_up : 1; /* C2 state works on MP system */ |
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| 124 | u32 pwr_button : 1; /* Power button is handled as a generic feature */ |
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| 125 | u32 sleep_button : 1; /* Sleep button is handled as a generic feature, or not present */ |
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| 126 | u32 fixed_rTC : 1; /* RTC wakeup stat not in fixed register space */ |
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| 127 | u32 rtcs4 : 1; /* RTC wakeup stat not possible from S4 */ |
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| 128 | u32 tmr_val_ext : 1; /* The tmr_val width is 32 bits (0 = 24 bits) */ |
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| 129 | u32 reserved5 : 23; /* Reserved - must be zero */ |
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| 130 | }; |
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| 131 | |
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| 132 | #pragma pack() |
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| 133 | |
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| 134 | #endif /* __ACTBL1_H__ */ |
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| 135 | |
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| 136 | |
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