1 | /* |
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2 | * Intel Multiprocessor Specification 1.1 and 1.4 |
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3 | * compliant MP-table parsing routines. |
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4 | * |
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5 | * (c) 1995 Alan Cox, Building #3 <alan@redhat.com> |
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6 | * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com> |
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7 | * |
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8 | * Fixes |
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9 | * Erich Boleyn : MP v1.4 and additional changes. |
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10 | * Alan Cox : Added EBDA scanning |
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11 | * Ingo Molnar : various cleanups and rewrites |
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12 | * Maciej W. Rozycki: Bits for default MP configurations |
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13 | * Paul Diefenbaugh: Added full ACPI support |
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14 | */ |
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15 | |
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16 | #include <xen/config.h> |
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17 | #include <xen/types.h> |
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18 | #include <xen/irq.h> |
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19 | #include <xen/init.h> |
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20 | #include <xen/acpi.h> |
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21 | #include <xen/delay.h> |
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22 | #include <xen/sched.h> |
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23 | |
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24 | #include <asm/mc146818rtc.h> |
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25 | #include <asm/bitops.h> |
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26 | #include <asm/smp.h> |
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27 | #include <asm/acpi.h> |
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28 | #include <asm/mtrr.h> |
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29 | #include <asm/mpspec.h> |
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30 | #include <asm/io_apic.h> |
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31 | |
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32 | #include <mach_apic.h> |
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33 | #include <mach_mpparse.h> |
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34 | #include <bios_ebda.h> |
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35 | |
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36 | /* Have we found an MP table */ |
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37 | int smp_found_config; |
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38 | unsigned int __initdata maxcpus = NR_CPUS; |
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39 | |
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40 | /* |
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41 | * Various Linux-internal data structures created from the |
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42 | * MP-table. |
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43 | */ |
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44 | int apic_version [MAX_APICS]; |
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45 | int mp_bus_id_to_type [MAX_MP_BUSSES]; |
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46 | int mp_bus_id_to_node [MAX_MP_BUSSES]; |
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47 | int mp_bus_id_to_local [MAX_MP_BUSSES]; |
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48 | int quad_local_to_mp_bus_id [NR_CPUS/4][4]; |
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49 | int mp_bus_id_to_pci_bus [MAX_MP_BUSSES] = { [0 ... MAX_MP_BUSSES-1] = -1 }; |
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50 | static int mp_current_pci_id; |
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51 | |
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52 | /* I/O APIC entries */ |
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53 | struct mpc_config_ioapic mp_ioapics[MAX_IO_APICS]; |
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54 | |
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55 | /* # of MP IRQ source entries */ |
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56 | struct mpc_config_intsrc mp_irqs[MAX_IRQ_SOURCES]; |
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57 | |
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58 | /* MP IRQ source entries */ |
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59 | int mp_irq_entries; |
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60 | |
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61 | int nr_ioapics; |
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62 | |
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63 | int pic_mode; |
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64 | unsigned long mp_lapic_addr; |
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65 | |
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66 | unsigned int def_to_bigsmp = 0; |
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67 | |
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68 | /* Processor that is doing the boot up */ |
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69 | unsigned int boot_cpu_physical_apicid = -1U; |
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70 | /* Internal processor count */ |
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71 | static unsigned int __devinitdata num_processors; |
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72 | |
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73 | /* Bitmask of physically existing CPUs */ |
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74 | physid_mask_t phys_cpu_present_map; |
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75 | |
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76 | u8 bios_cpu_apicid[NR_CPUS] = { [0 ... NR_CPUS-1] = BAD_APICID }; |
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77 | |
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78 | /* |
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79 | * Intel MP BIOS table parsing routines: |
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80 | */ |
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81 | |
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82 | |
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83 | /* |
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84 | * Checksum an MP configuration block. |
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85 | */ |
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86 | |
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87 | static int __init mpf_checksum(unsigned char *mp, int len) |
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88 | { |
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89 | int sum = 0; |
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90 | |
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91 | while (len--) |
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92 | sum += *mp++; |
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93 | |
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94 | return sum & 0xFF; |
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95 | } |
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96 | |
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97 | /* |
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98 | * Have to match translation table entries to main table entries by counter |
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99 | * hence the mpc_record variable .... can't see a less disgusting way of |
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100 | * doing this .... |
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101 | */ |
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102 | |
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103 | static int mpc_record; |
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104 | static struct mpc_config_translation *translation_table[MAX_MPC_ENTRY] __initdata; |
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105 | |
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106 | static void __devinit MP_processor_info (struct mpc_config_processor *m) |
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107 | { |
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108 | int ver, apicid; |
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109 | physid_mask_t phys_cpu; |
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110 | |
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111 | if (!(m->mpc_cpuflag & CPU_ENABLED)) |
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112 | return; |
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113 | |
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114 | apicid = mpc_apic_id(m, translation_table[mpc_record]); |
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115 | |
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116 | if (m->mpc_featureflag&(1<<0)) |
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117 | Dprintk(" Floating point unit present.\n"); |
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118 | if (m->mpc_featureflag&(1<<7)) |
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119 | Dprintk(" Machine Exception supported.\n"); |
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120 | if (m->mpc_featureflag&(1<<8)) |
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121 | Dprintk(" 64 bit compare & exchange supported.\n"); |
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122 | if (m->mpc_featureflag&(1<<9)) |
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123 | Dprintk(" Internal APIC present.\n"); |
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124 | if (m->mpc_featureflag&(1<<11)) |
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125 | Dprintk(" SEP present.\n"); |
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126 | if (m->mpc_featureflag&(1<<12)) |
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127 | Dprintk(" MTRR present.\n"); |
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128 | if (m->mpc_featureflag&(1<<13)) |
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129 | Dprintk(" PGE present.\n"); |
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130 | if (m->mpc_featureflag&(1<<14)) |
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131 | Dprintk(" MCA present.\n"); |
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132 | if (m->mpc_featureflag&(1<<15)) |
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133 | Dprintk(" CMOV present.\n"); |
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134 | if (m->mpc_featureflag&(1<<16)) |
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135 | Dprintk(" PAT present.\n"); |
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136 | if (m->mpc_featureflag&(1<<17)) |
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137 | Dprintk(" PSE present.\n"); |
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138 | if (m->mpc_featureflag&(1<<18)) |
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139 | Dprintk(" PSN present.\n"); |
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140 | if (m->mpc_featureflag&(1<<19)) |
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141 | Dprintk(" Cache Line Flush Instruction present.\n"); |
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142 | /* 20 Reserved */ |
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143 | if (m->mpc_featureflag&(1<<21)) |
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144 | Dprintk(" Debug Trace and EMON Store present.\n"); |
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145 | if (m->mpc_featureflag&(1<<22)) |
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146 | Dprintk(" ACPI Thermal Throttle Registers present.\n"); |
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147 | if (m->mpc_featureflag&(1<<23)) |
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148 | Dprintk(" MMX present.\n"); |
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149 | if (m->mpc_featureflag&(1<<24)) |
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150 | Dprintk(" FXSR present.\n"); |
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151 | if (m->mpc_featureflag&(1<<25)) |
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152 | Dprintk(" XMM present.\n"); |
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153 | if (m->mpc_featureflag&(1<<26)) |
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154 | Dprintk(" Willamette New Instructions present.\n"); |
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155 | if (m->mpc_featureflag&(1<<27)) |
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156 | Dprintk(" Self Snoop present.\n"); |
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157 | if (m->mpc_featureflag&(1<<28)) |
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158 | Dprintk(" HT present.\n"); |
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159 | if (m->mpc_featureflag&(1<<29)) |
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160 | Dprintk(" Thermal Monitor present.\n"); |
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161 | /* 30, 31 Reserved */ |
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162 | |
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163 | |
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164 | if (m->mpc_cpuflag & CPU_BOOTPROCESSOR) { |
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165 | Dprintk(" Bootup CPU\n"); |
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166 | boot_cpu_physical_apicid = m->mpc_apicid; |
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167 | } |
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168 | |
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169 | ver = m->mpc_apicver; |
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170 | |
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171 | /* |
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172 | * Validate version |
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173 | */ |
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174 | if (ver == 0x0) { |
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175 | printk(KERN_WARNING "BIOS bug, APIC version is 0 for CPU#%d! " |
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176 | "fixing up to 0x10. (tell your hw vendor)\n", |
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177 | m->mpc_apicid); |
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178 | ver = 0x10; |
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179 | } |
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180 | apic_version[m->mpc_apicid] = ver; |
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181 | |
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182 | phys_cpu = apicid_to_cpu_present(apicid); |
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183 | physids_or(phys_cpu_present_map, phys_cpu_present_map, phys_cpu); |
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184 | |
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185 | if (num_processors >= NR_CPUS) { |
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186 | printk(KERN_WARNING "WARNING: NR_CPUS limit of %i reached." |
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187 | " Processor ignored.\n", NR_CPUS); |
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188 | return; |
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189 | } |
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190 | |
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191 | if (num_processors >= maxcpus) { |
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192 | printk(KERN_WARNING "WARNING: maxcpus limit of %i reached." |
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193 | " Processor ignored.\n", maxcpus); |
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194 | return; |
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195 | } |
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196 | |
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197 | cpu_set(num_processors, cpu_possible_map); |
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198 | num_processors++; |
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199 | |
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200 | if (num_processors > 8) { |
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201 | /* |
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202 | * No need for processor or APIC checks: physical delivery |
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203 | * (bigsmp) mode should always work. |
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204 | */ |
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205 | def_to_bigsmp = 1; |
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206 | } |
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207 | bios_cpu_apicid[num_processors - 1] = m->mpc_apicid; |
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208 | } |
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209 | |
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210 | static void __init MP_bus_info (struct mpc_config_bus *m) |
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211 | { |
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212 | char str[7]; |
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213 | |
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214 | memcpy(str, m->mpc_bustype, 6); |
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215 | str[6] = 0; |
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216 | |
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217 | mpc_oem_bus_info(m, str, translation_table[mpc_record]); |
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218 | |
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219 | #if 0 /* size of mpc_busid (8 bits) makes this check unnecessary */ |
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220 | if (m->mpc_busid >= MAX_MP_BUSSES) { |
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221 | printk(KERN_WARNING "MP table busid value (%d) for bustype %s " |
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222 | " is too large, max. supported is %d\n", |
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223 | m->mpc_busid, str, MAX_MP_BUSSES - 1); |
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224 | return; |
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225 | } |
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226 | #endif |
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227 | |
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228 | if (strncmp(str, BUSTYPE_ISA, sizeof(BUSTYPE_ISA)-1) == 0) { |
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229 | mp_bus_id_to_type[m->mpc_busid] = MP_BUS_ISA; |
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230 | } else if (strncmp(str, BUSTYPE_EISA, sizeof(BUSTYPE_EISA)-1) == 0) { |
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231 | mp_bus_id_to_type[m->mpc_busid] = MP_BUS_EISA; |
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232 | } else if (strncmp(str, BUSTYPE_PCI, sizeof(BUSTYPE_PCI)-1) == 0) { |
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233 | mpc_oem_pci_bus(m, translation_table[mpc_record]); |
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234 | mp_bus_id_to_type[m->mpc_busid] = MP_BUS_PCI; |
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235 | mp_bus_id_to_pci_bus[m->mpc_busid] = mp_current_pci_id; |
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236 | mp_current_pci_id++; |
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237 | } else if (strncmp(str, BUSTYPE_MCA, sizeof(BUSTYPE_MCA)-1) == 0) { |
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238 | mp_bus_id_to_type[m->mpc_busid] = MP_BUS_MCA; |
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239 | } else if (strncmp(str, BUSTYPE_NEC98, sizeof(BUSTYPE_NEC98)-1) == 0) { |
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240 | mp_bus_id_to_type[m->mpc_busid] = MP_BUS_NEC98; |
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241 | } else { |
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242 | printk(KERN_WARNING "Unknown bustype %s - ignoring\n", str); |
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243 | } |
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244 | } |
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245 | |
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246 | static void __init MP_ioapic_info (struct mpc_config_ioapic *m) |
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247 | { |
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248 | if (!(m->mpc_flags & MPC_APIC_USABLE)) |
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249 | return; |
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250 | |
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251 | printk(KERN_INFO "I/O APIC #%d Version %d at 0x%X.\n", |
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252 | m->mpc_apicid, m->mpc_apicver, m->mpc_apicaddr); |
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253 | if (nr_ioapics >= MAX_IO_APICS) { |
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254 | printk(KERN_CRIT "Max # of I/O APICs (%d) exceeded (found %d).\n", |
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255 | MAX_IO_APICS, nr_ioapics); |
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256 | panic("Recompile kernel with bigger MAX_IO_APICS!.\n"); |
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257 | } |
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258 | if (!m->mpc_apicaddr) { |
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259 | printk(KERN_ERR "WARNING: bogus zero I/O APIC address" |
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260 | " found in MP table, skipping!\n"); |
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261 | return; |
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262 | } |
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263 | mp_ioapics[nr_ioapics] = *m; |
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264 | nr_ioapics++; |
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265 | } |
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266 | |
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267 | static void __init MP_intsrc_info (struct mpc_config_intsrc *m) |
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268 | { |
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269 | mp_irqs [mp_irq_entries] = *m; |
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270 | Dprintk("Int: type %d, pol %d, trig %d, bus %d," |
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271 | " IRQ %02x, APIC ID %x, APIC INT %02x\n", |
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272 | m->mpc_irqtype, m->mpc_irqflag & 3, |
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273 | (m->mpc_irqflag >> 2) & 3, m->mpc_srcbus, |
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274 | m->mpc_srcbusirq, m->mpc_dstapic, m->mpc_dstirq); |
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275 | if (++mp_irq_entries == MAX_IRQ_SOURCES) |
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276 | panic("Max # of irq sources exceeded!!\n"); |
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277 | } |
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278 | |
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279 | static void __init MP_lintsrc_info (struct mpc_config_lintsrc *m) |
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280 | { |
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281 | Dprintk("Lint: type %d, pol %d, trig %d, bus %d," |
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282 | " IRQ %02x, APIC ID %x, APIC LINT %02x\n", |
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283 | m->mpc_irqtype, m->mpc_irqflag & 3, |
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284 | (m->mpc_irqflag >> 2) &3, m->mpc_srcbusid, |
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285 | m->mpc_srcbusirq, m->mpc_destapic, m->mpc_destapiclint); |
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286 | /* |
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287 | * Well it seems all SMP boards in existence |
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288 | * use ExtINT/LVT1 == LINT0 and |
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289 | * NMI/LVT2 == LINT1 - the following check |
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290 | * will show us if this assumptions is false. |
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291 | * Until then we do not have to add baggage. |
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292 | */ |
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293 | if ((m->mpc_irqtype == mp_ExtINT) && |
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294 | (m->mpc_destapiclint != 0)) |
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295 | BUG(); |
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296 | if ((m->mpc_irqtype == mp_NMI) && |
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297 | (m->mpc_destapiclint != 1)) |
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298 | BUG(); |
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299 | } |
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300 | |
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301 | #ifdef CONFIG_X86_NUMAQ |
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302 | static void __init MP_translation_info (struct mpc_config_translation *m) |
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303 | { |
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304 | printk(KERN_INFO "Translation: record %d, type %d, quad %d, global %d, local %d\n", mpc_record, m->trans_type, m->trans_quad, m->trans_global, m->trans_local); |
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305 | |
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306 | if (mpc_record >= MAX_MPC_ENTRY) |
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307 | printk(KERN_ERR "MAX_MPC_ENTRY exceeded!\n"); |
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308 | else |
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309 | translation_table[mpc_record] = m; /* stash this for later */ |
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310 | if (m->trans_quad < MAX_NUMNODES && !node_online(m->trans_quad)) |
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311 | node_set_online(m->trans_quad); |
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312 | } |
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313 | |
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314 | /* |
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315 | * Read/parse the MPC oem tables |
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316 | */ |
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317 | |
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318 | static void __init smp_read_mpc_oem(struct mp_config_oemtable *oemtable, \ |
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319 | unsigned short oemsize) |
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320 | { |
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321 | int count = sizeof (*oemtable); /* the header size */ |
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322 | unsigned char *oemptr = ((unsigned char *)oemtable)+count; |
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323 | |
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324 | mpc_record = 0; |
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325 | printk(KERN_INFO "Found an OEM MPC table at %8p - parsing it ... \n", oemtable); |
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326 | if (memcmp(oemtable->oem_signature,MPC_OEM_SIGNATURE,4)) |
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327 | { |
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328 | printk(KERN_WARNING "SMP mpc oemtable: bad signature [%c%c%c%c]!\n", |
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329 | oemtable->oem_signature[0], |
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330 | oemtable->oem_signature[1], |
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331 | oemtable->oem_signature[2], |
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332 | oemtable->oem_signature[3]); |
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333 | return; |
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334 | } |
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335 | if (mpf_checksum((unsigned char *)oemtable,oemtable->oem_length)) |
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336 | { |
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337 | printk(KERN_WARNING "SMP oem mptable: checksum error!\n"); |
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338 | return; |
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339 | } |
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340 | while (count < oemtable->oem_length) { |
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341 | switch (*oemptr) { |
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342 | case MP_TRANSLATION: |
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343 | { |
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344 | struct mpc_config_translation *m= |
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345 | (struct mpc_config_translation *)oemptr; |
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346 | MP_translation_info(m); |
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347 | oemptr += sizeof(*m); |
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348 | count += sizeof(*m); |
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349 | ++mpc_record; |
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350 | break; |
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351 | } |
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352 | default: |
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353 | { |
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354 | printk(KERN_WARNING "Unrecognised OEM table entry type! - %d\n", (int) *oemptr); |
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355 | return; |
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356 | } |
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357 | } |
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358 | } |
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359 | } |
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360 | |
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361 | static inline void mps_oem_check(struct mp_config_table *mpc, char *oem, |
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362 | char *productid) |
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363 | { |
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364 | if (strncmp(oem, "IBM NUMA", 8)) |
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365 | printk("Warning! May not be a NUMA-Q system!\n"); |
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366 | if (mpc->mpc_oemptr) |
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367 | smp_read_mpc_oem((struct mp_config_oemtable *) mpc->mpc_oemptr, |
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368 | mpc->mpc_oemsize); |
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369 | } |
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370 | #endif /* CONFIG_X86_NUMAQ */ |
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371 | |
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372 | /* |
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373 | * Read/parse the MPC |
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374 | */ |
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375 | |
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376 | static int __init smp_read_mpc(struct mp_config_table *mpc) |
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377 | { |
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378 | char str[16]; |
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379 | char oem[10]; |
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380 | int count=sizeof(*mpc); |
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381 | unsigned char *mpt=((unsigned char *)mpc)+count; |
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382 | |
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383 | if (memcmp(mpc->mpc_signature,MPC_SIGNATURE,4)) { |
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384 | printk(KERN_ERR "SMP mptable: bad signature [0x%x]!\n", |
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385 | *(u32 *)mpc->mpc_signature); |
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386 | return 0; |
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387 | } |
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388 | if (mpf_checksum((unsigned char *)mpc,mpc->mpc_length)) { |
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389 | printk(KERN_ERR "SMP mptable: checksum error!\n"); |
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390 | return 0; |
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391 | } |
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392 | if (mpc->mpc_spec!=0x01 && mpc->mpc_spec!=0x04) { |
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393 | printk(KERN_ERR "SMP mptable: bad table version (%d)!!\n", |
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394 | mpc->mpc_spec); |
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395 | return 0; |
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396 | } |
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397 | if (!mpc->mpc_lapic) { |
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398 | printk(KERN_ERR "SMP mptable: null local APIC address!\n"); |
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399 | return 0; |
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400 | } |
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401 | memcpy(oem,mpc->mpc_oem,8); |
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402 | oem[8]=0; |
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403 | printk(KERN_INFO "OEM ID: %s ",oem); |
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404 | |
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405 | memcpy(str,mpc->mpc_productid,12); |
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406 | str[12]=0; |
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407 | printk("Product ID: %s ",str); |
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408 | |
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409 | mps_oem_check(mpc, oem, str); |
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410 | |
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411 | printk("APIC at: 0x%X\n",mpc->mpc_lapic); |
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412 | |
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413 | /* |
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414 | * Save the local APIC address (it might be non-default) -- but only |
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415 | * if we're not using ACPI. |
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416 | */ |
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417 | if (!acpi_lapic) |
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418 | mp_lapic_addr = mpc->mpc_lapic; |
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419 | |
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420 | /* |
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421 | * Now process the configuration blocks. |
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422 | */ |
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423 | mpc_record = 0; |
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424 | while (count < mpc->mpc_length) { |
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425 | switch(*mpt) { |
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426 | case MP_PROCESSOR: |
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427 | { |
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428 | struct mpc_config_processor *m= |
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429 | (struct mpc_config_processor *)mpt; |
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430 | /* ACPI may have already provided this data */ |
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431 | if (!acpi_lapic) |
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432 | MP_processor_info(m); |
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433 | mpt += sizeof(*m); |
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434 | count += sizeof(*m); |
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435 | break; |
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436 | } |
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437 | case MP_BUS: |
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438 | { |
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439 | struct mpc_config_bus *m= |
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440 | (struct mpc_config_bus *)mpt; |
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441 | MP_bus_info(m); |
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442 | mpt += sizeof(*m); |
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443 | count += sizeof(*m); |
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444 | break; |
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445 | } |
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446 | case MP_IOAPIC: |
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447 | { |
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448 | struct mpc_config_ioapic *m= |
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449 | (struct mpc_config_ioapic *)mpt; |
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450 | MP_ioapic_info(m); |
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451 | mpt+=sizeof(*m); |
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452 | count+=sizeof(*m); |
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453 | break; |
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454 | } |
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455 | case MP_INTSRC: |
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456 | { |
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457 | struct mpc_config_intsrc *m= |
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458 | (struct mpc_config_intsrc *)mpt; |
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459 | |
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460 | MP_intsrc_info(m); |
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461 | mpt+=sizeof(*m); |
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462 | count+=sizeof(*m); |
---|
463 | break; |
---|
464 | } |
---|
465 | case MP_LINTSRC: |
---|
466 | { |
---|
467 | struct mpc_config_lintsrc *m= |
---|
468 | (struct mpc_config_lintsrc *)mpt; |
---|
469 | MP_lintsrc_info(m); |
---|
470 | mpt+=sizeof(*m); |
---|
471 | count+=sizeof(*m); |
---|
472 | break; |
---|
473 | } |
---|
474 | default: |
---|
475 | { |
---|
476 | count = mpc->mpc_length; |
---|
477 | break; |
---|
478 | } |
---|
479 | } |
---|
480 | ++mpc_record; |
---|
481 | } |
---|
482 | clustered_apic_check(); |
---|
483 | if (!num_processors) |
---|
484 | printk(KERN_ERR "SMP mptable: no processors registered!\n"); |
---|
485 | return num_processors; |
---|
486 | } |
---|
487 | |
---|
488 | static int __init ELCR_trigger(unsigned int irq) |
---|
489 | { |
---|
490 | unsigned int port; |
---|
491 | |
---|
492 | port = 0x4d0 + (irq >> 3); |
---|
493 | return (inb(port) >> (irq & 7)) & 1; |
---|
494 | } |
---|
495 | |
---|
496 | static void __init construct_default_ioirq_mptable(int mpc_default_type) |
---|
497 | { |
---|
498 | struct mpc_config_intsrc intsrc; |
---|
499 | int i; |
---|
500 | int ELCR_fallback = 0; |
---|
501 | |
---|
502 | intsrc.mpc_type = MP_INTSRC; |
---|
503 | intsrc.mpc_irqflag = 0; /* conforming */ |
---|
504 | intsrc.mpc_srcbus = 0; |
---|
505 | intsrc.mpc_dstapic = mp_ioapics[0].mpc_apicid; |
---|
506 | |
---|
507 | intsrc.mpc_irqtype = mp_INT; |
---|
508 | |
---|
509 | /* |
---|
510 | * If true, we have an ISA/PCI system with no IRQ entries |
---|
511 | * in the MP table. To prevent the PCI interrupts from being set up |
---|
512 | * incorrectly, we try to use the ELCR. The sanity check to see if |
---|
513 | * there is good ELCR data is very simple - IRQ0, 1, 2 and 13 can |
---|
514 | * never be level sensitive, so we simply see if the ELCR agrees. |
---|
515 | * If it does, we assume it's valid. |
---|
516 | */ |
---|
517 | if (mpc_default_type == 5) { |
---|
518 | printk(KERN_INFO "ISA/PCI bus type with no IRQ information... falling back to ELCR\n"); |
---|
519 | |
---|
520 | if (ELCR_trigger(0) || ELCR_trigger(1) || ELCR_trigger(2) || ELCR_trigger(13)) |
---|
521 | printk(KERN_WARNING "ELCR contains invalid data... not using ELCR\n"); |
---|
522 | else { |
---|
523 | printk(KERN_INFO "Using ELCR to identify PCI interrupts\n"); |
---|
524 | ELCR_fallback = 1; |
---|
525 | } |
---|
526 | } |
---|
527 | |
---|
528 | for (i = 0; i < 16; i++) { |
---|
529 | switch (mpc_default_type) { |
---|
530 | case 2: |
---|
531 | if (i == 0 || i == 13) |
---|
532 | continue; /* IRQ0 & IRQ13 not connected */ |
---|
533 | /* fall through */ |
---|
534 | default: |
---|
535 | if (i == 2) |
---|
536 | continue; /* IRQ2 is never connected */ |
---|
537 | } |
---|
538 | |
---|
539 | if (ELCR_fallback) { |
---|
540 | /* |
---|
541 | * If the ELCR indicates a level-sensitive interrupt, we |
---|
542 | * copy that information over to the MP table in the |
---|
543 | * irqflag field (level sensitive, active high polarity). |
---|
544 | */ |
---|
545 | if (ELCR_trigger(i)) |
---|
546 | intsrc.mpc_irqflag = 13; |
---|
547 | else |
---|
548 | intsrc.mpc_irqflag = 0; |
---|
549 | } |
---|
550 | |
---|
551 | intsrc.mpc_srcbusirq = i; |
---|
552 | intsrc.mpc_dstirq = i ? i : 2; /* IRQ0 to INTIN2 */ |
---|
553 | MP_intsrc_info(&intsrc); |
---|
554 | } |
---|
555 | |
---|
556 | intsrc.mpc_irqtype = mp_ExtINT; |
---|
557 | intsrc.mpc_srcbusirq = 0; |
---|
558 | intsrc.mpc_dstirq = 0; /* 8259A to INTIN0 */ |
---|
559 | MP_intsrc_info(&intsrc); |
---|
560 | } |
---|
561 | |
---|
562 | static inline void __init construct_default_ISA_mptable(int mpc_default_type) |
---|
563 | { |
---|
564 | struct mpc_config_processor processor; |
---|
565 | struct mpc_config_bus bus; |
---|
566 | struct mpc_config_ioapic ioapic; |
---|
567 | struct mpc_config_lintsrc lintsrc; |
---|
568 | int linttypes[2] = { mp_ExtINT, mp_NMI }; |
---|
569 | int i; |
---|
570 | |
---|
571 | /* |
---|
572 | * local APIC has default address |
---|
573 | */ |
---|
574 | mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; |
---|
575 | |
---|
576 | /* |
---|
577 | * 2 CPUs, numbered 0 & 1. |
---|
578 | */ |
---|
579 | processor.mpc_type = MP_PROCESSOR; |
---|
580 | /* Either an integrated APIC or a discrete 82489DX. */ |
---|
581 | processor.mpc_apicver = mpc_default_type > 4 ? 0x10 : 0x01; |
---|
582 | processor.mpc_cpuflag = CPU_ENABLED; |
---|
583 | processor.mpc_cpufeature = (boot_cpu_data.x86 << 8) | |
---|
584 | (boot_cpu_data.x86_model << 4) | |
---|
585 | boot_cpu_data.x86_mask; |
---|
586 | processor.mpc_featureflag = boot_cpu_data.x86_capability[0]; |
---|
587 | processor.mpc_reserved[0] = 0; |
---|
588 | processor.mpc_reserved[1] = 0; |
---|
589 | for (i = 0; i < 2; i++) { |
---|
590 | processor.mpc_apicid = i; |
---|
591 | MP_processor_info(&processor); |
---|
592 | } |
---|
593 | |
---|
594 | bus.mpc_type = MP_BUS; |
---|
595 | bus.mpc_busid = 0; |
---|
596 | switch (mpc_default_type) { |
---|
597 | default: |
---|
598 | printk("???\n"); |
---|
599 | printk(KERN_ERR "Unknown standard configuration %d\n", |
---|
600 | mpc_default_type); |
---|
601 | /* fall through */ |
---|
602 | case 1: |
---|
603 | case 5: |
---|
604 | memcpy(bus.mpc_bustype, "ISA ", 6); |
---|
605 | break; |
---|
606 | case 2: |
---|
607 | case 6: |
---|
608 | case 3: |
---|
609 | memcpy(bus.mpc_bustype, "EISA ", 6); |
---|
610 | break; |
---|
611 | case 4: |
---|
612 | case 7: |
---|
613 | memcpy(bus.mpc_bustype, "MCA ", 6); |
---|
614 | } |
---|
615 | MP_bus_info(&bus); |
---|
616 | if (mpc_default_type > 4) { |
---|
617 | bus.mpc_busid = 1; |
---|
618 | memcpy(bus.mpc_bustype, "PCI ", 6); |
---|
619 | MP_bus_info(&bus); |
---|
620 | } |
---|
621 | |
---|
622 | ioapic.mpc_type = MP_IOAPIC; |
---|
623 | ioapic.mpc_apicid = 2; |
---|
624 | ioapic.mpc_apicver = mpc_default_type > 4 ? 0x10 : 0x01; |
---|
625 | ioapic.mpc_flags = MPC_APIC_USABLE; |
---|
626 | ioapic.mpc_apicaddr = 0xFEC00000; |
---|
627 | MP_ioapic_info(&ioapic); |
---|
628 | |
---|
629 | /* |
---|
630 | * We set up most of the low 16 IO-APIC pins according to MPS rules. |
---|
631 | */ |
---|
632 | construct_default_ioirq_mptable(mpc_default_type); |
---|
633 | |
---|
634 | lintsrc.mpc_type = MP_LINTSRC; |
---|
635 | lintsrc.mpc_irqflag = 0; /* conforming */ |
---|
636 | lintsrc.mpc_srcbusid = 0; |
---|
637 | lintsrc.mpc_srcbusirq = 0; |
---|
638 | lintsrc.mpc_destapic = MP_APIC_ALL; |
---|
639 | for (i = 0; i < 2; i++) { |
---|
640 | lintsrc.mpc_irqtype = linttypes[i]; |
---|
641 | lintsrc.mpc_destapiclint = i; |
---|
642 | MP_lintsrc_info(&lintsrc); |
---|
643 | } |
---|
644 | } |
---|
645 | |
---|
646 | static struct intel_mp_floating *mpf_found; |
---|
647 | |
---|
648 | /* |
---|
649 | * Scan the memory blocks for an SMP configuration block. |
---|
650 | */ |
---|
651 | void __init get_smp_config (void) |
---|
652 | { |
---|
653 | struct intel_mp_floating *mpf = mpf_found; |
---|
654 | |
---|
655 | /* |
---|
656 | * ACPI supports both logical (e.g. Hyper-Threading) and physical |
---|
657 | * processors, where MPS only supports physical. |
---|
658 | */ |
---|
659 | if (acpi_lapic && acpi_ioapic) { |
---|
660 | printk(KERN_INFO "Using ACPI (MADT) for SMP configuration information\n"); |
---|
661 | return; |
---|
662 | } |
---|
663 | else if (acpi_lapic) |
---|
664 | printk(KERN_INFO "Using ACPI for processor (LAPIC) configuration information\n"); |
---|
665 | |
---|
666 | printk(KERN_INFO "Intel MultiProcessor Specification v1.%d\n", mpf->mpf_specification); |
---|
667 | if (mpf->mpf_feature2 & (1<<7)) { |
---|
668 | printk(KERN_INFO " IMCR and PIC compatibility mode.\n"); |
---|
669 | pic_mode = 1; |
---|
670 | } else { |
---|
671 | printk(KERN_INFO " Virtual Wire compatibility mode.\n"); |
---|
672 | pic_mode = 0; |
---|
673 | } |
---|
674 | |
---|
675 | /* |
---|
676 | * Now see if we need to read further. |
---|
677 | */ |
---|
678 | if (mpf->mpf_feature1 != 0) { |
---|
679 | |
---|
680 | printk(KERN_INFO "Default MP configuration #%d\n", mpf->mpf_feature1); |
---|
681 | construct_default_ISA_mptable(mpf->mpf_feature1); |
---|
682 | |
---|
683 | } else if (mpf->mpf_physptr) { |
---|
684 | |
---|
685 | /* |
---|
686 | * Read the physical hardware table. Anything here will |
---|
687 | * override the defaults. |
---|
688 | */ |
---|
689 | if (!smp_read_mpc((void *)(unsigned long)mpf->mpf_physptr)) { |
---|
690 | smp_found_config = 0; |
---|
691 | printk(KERN_ERR "BIOS bug, MP table errors detected!...\n"); |
---|
692 | printk(KERN_ERR "... disabling SMP support. (tell your hw vendor)\n"); |
---|
693 | return; |
---|
694 | } |
---|
695 | /* |
---|
696 | * If there are no explicit MP IRQ entries, then we are |
---|
697 | * broken. We set up most of the low 16 IO-APIC pins to |
---|
698 | * ISA defaults and hope it will work. |
---|
699 | */ |
---|
700 | if (!mp_irq_entries) { |
---|
701 | struct mpc_config_bus bus; |
---|
702 | |
---|
703 | printk(KERN_ERR "BIOS bug, no explicit IRQ entries, using default mptable. (tell your hw vendor)\n"); |
---|
704 | |
---|
705 | bus.mpc_type = MP_BUS; |
---|
706 | bus.mpc_busid = 0; |
---|
707 | memcpy(bus.mpc_bustype, "ISA ", 6); |
---|
708 | MP_bus_info(&bus); |
---|
709 | |
---|
710 | construct_default_ioirq_mptable(0); |
---|
711 | } |
---|
712 | |
---|
713 | } else |
---|
714 | BUG(); |
---|
715 | |
---|
716 | printk(KERN_INFO "Processors: %d\n", num_processors); |
---|
717 | /* |
---|
718 | * Only use the first configuration found. |
---|
719 | */ |
---|
720 | } |
---|
721 | |
---|
722 | static int __init smp_scan_config (unsigned long base, unsigned long length) |
---|
723 | { |
---|
724 | unsigned int *bp = maddr_to_virt(base); |
---|
725 | struct intel_mp_floating *mpf; |
---|
726 | |
---|
727 | Dprintk("Scan SMP from %p for %ld bytes.\n", bp,length); |
---|
728 | if (sizeof(*mpf) != 16) |
---|
729 | printk("Error: MPF size\n"); |
---|
730 | |
---|
731 | while (length > 0) { |
---|
732 | mpf = (struct intel_mp_floating *)bp; |
---|
733 | if ((*bp == SMP_MAGIC_IDENT) && |
---|
734 | (mpf->mpf_length == 1) && |
---|
735 | !mpf_checksum((unsigned char *)bp, 16) && |
---|
736 | ((mpf->mpf_specification == 1) |
---|
737 | || (mpf->mpf_specification == 4)) ) { |
---|
738 | |
---|
739 | smp_found_config = 1; |
---|
740 | printk(KERN_INFO "found SMP MP-table at %08lx\n", |
---|
741 | virt_to_maddr(mpf)); |
---|
742 | #if 0 |
---|
743 | reserve_bootmem(virt_to_maddr(mpf), PAGE_SIZE); |
---|
744 | if (mpf->mpf_physptr) { |
---|
745 | /* |
---|
746 | * We cannot access to MPC table to compute |
---|
747 | * table size yet, as only few megabytes from |
---|
748 | * the bottom is mapped now. |
---|
749 | * PC-9800's MPC table places on the very last |
---|
750 | * of physical memory; so that simply reserving |
---|
751 | * PAGE_SIZE from mpg->mpf_physptr yields BUG() |
---|
752 | * in reserve_bootmem. |
---|
753 | */ |
---|
754 | unsigned long size = PAGE_SIZE; |
---|
755 | unsigned long end = max_low_pfn * PAGE_SIZE; |
---|
756 | if (mpf->mpf_physptr + size > end) |
---|
757 | size = end - mpf->mpf_physptr; |
---|
758 | reserve_bootmem(mpf->mpf_physptr, size); |
---|
759 | } |
---|
760 | #endif |
---|
761 | mpf_found = mpf; |
---|
762 | return 1; |
---|
763 | } |
---|
764 | bp += 4; |
---|
765 | length -= 16; |
---|
766 | } |
---|
767 | return 0; |
---|
768 | } |
---|
769 | |
---|
770 | void __init find_smp_config (void) |
---|
771 | { |
---|
772 | unsigned int address; |
---|
773 | |
---|
774 | /* |
---|
775 | * FIXME: Linux assumes you have 640K of base ram.. |
---|
776 | * this continues the error... |
---|
777 | * |
---|
778 | * 1) Scan the bottom 1K for a signature |
---|
779 | * 2) Scan the top 1K of base RAM |
---|
780 | * 3) Scan the 64K of bios |
---|
781 | */ |
---|
782 | if (smp_scan_config(0x0,0x400) || |
---|
783 | smp_scan_config(639*0x400,0x400) || |
---|
784 | smp_scan_config(0xF0000,0x10000)) |
---|
785 | return; |
---|
786 | /* |
---|
787 | * If it is an SMP machine we should know now, unless the |
---|
788 | * configuration is in an EISA/MCA bus machine with an |
---|
789 | * extended bios data area. |
---|
790 | * |
---|
791 | * there is a real-mode segmented pointer pointing to the |
---|
792 | * 4K EBDA area at 0x40E, calculate and scan it here. |
---|
793 | * |
---|
794 | * NOTE! There are Linux loaders that will corrupt the EBDA |
---|
795 | * area, and as such this kind of SMP config may be less |
---|
796 | * trustworthy, simply because the SMP table may have been |
---|
797 | * stomped on during early boot. These loaders are buggy and |
---|
798 | * should be fixed. |
---|
799 | * |
---|
800 | * MP1.4 SPEC states to only scan first 1K of 4K EBDA. |
---|
801 | */ |
---|
802 | |
---|
803 | address = get_bios_ebda(); |
---|
804 | if (address) |
---|
805 | smp_scan_config(address, 0x400); |
---|
806 | } |
---|
807 | |
---|
808 | /* -------------------------------------------------------------------------- |
---|
809 | ACPI-based MP Configuration |
---|
810 | -------------------------------------------------------------------------- */ |
---|
811 | |
---|
812 | #ifdef CONFIG_ACPI |
---|
813 | |
---|
814 | void __init mp_register_lapic_address ( |
---|
815 | u64 address) |
---|
816 | { |
---|
817 | mp_lapic_addr = (unsigned long) address; |
---|
818 | |
---|
819 | set_fixmap_nocache(FIX_APIC_BASE, mp_lapic_addr); |
---|
820 | |
---|
821 | if (boot_cpu_physical_apicid == -1U) |
---|
822 | boot_cpu_physical_apicid = GET_APIC_ID(apic_read(APIC_ID)); |
---|
823 | |
---|
824 | Dprintk("Boot CPU = %d\n", boot_cpu_physical_apicid); |
---|
825 | } |
---|
826 | |
---|
827 | |
---|
828 | void __devinit mp_register_lapic ( |
---|
829 | u8 id, |
---|
830 | u8 enabled) |
---|
831 | { |
---|
832 | struct mpc_config_processor processor; |
---|
833 | int boot_cpu = 0; |
---|
834 | |
---|
835 | if (MAX_APICS - id <= 0) { |
---|
836 | printk(KERN_WARNING "Processor #%d invalid (max %d)\n", |
---|
837 | id, MAX_APICS); |
---|
838 | return; |
---|
839 | } |
---|
840 | |
---|
841 | if (id == boot_cpu_physical_apicid) |
---|
842 | boot_cpu = 1; |
---|
843 | |
---|
844 | processor.mpc_type = MP_PROCESSOR; |
---|
845 | processor.mpc_apicid = id; |
---|
846 | processor.mpc_apicver = GET_APIC_VERSION(apic_read(APIC_LVR)); |
---|
847 | processor.mpc_cpuflag = (enabled ? CPU_ENABLED : 0); |
---|
848 | processor.mpc_cpuflag |= (boot_cpu ? CPU_BOOTPROCESSOR : 0); |
---|
849 | processor.mpc_cpufeature = (boot_cpu_data.x86 << 8) | |
---|
850 | (boot_cpu_data.x86_model << 4) | boot_cpu_data.x86_mask; |
---|
851 | processor.mpc_featureflag = boot_cpu_data.x86_capability[0]; |
---|
852 | processor.mpc_reserved[0] = 0; |
---|
853 | processor.mpc_reserved[1] = 0; |
---|
854 | |
---|
855 | MP_processor_info(&processor); |
---|
856 | } |
---|
857 | |
---|
858 | #ifdef CONFIG_X86_IO_APIC |
---|
859 | |
---|
860 | #define MP_ISA_BUS 0 |
---|
861 | #define MP_MAX_IOAPIC_PIN 127 |
---|
862 | |
---|
863 | static struct mp_ioapic_routing { |
---|
864 | int apic_id; |
---|
865 | int gsi_base; |
---|
866 | int gsi_end; |
---|
867 | u32 pin_programmed[4]; |
---|
868 | } mp_ioapic_routing[MAX_IO_APICS]; |
---|
869 | |
---|
870 | |
---|
871 | static int mp_find_ioapic ( |
---|
872 | int gsi) |
---|
873 | { |
---|
874 | int i = 0; |
---|
875 | |
---|
876 | /* Find the IOAPIC that manages this GSI. */ |
---|
877 | for (i = 0; i < nr_ioapics; i++) { |
---|
878 | if ((gsi >= mp_ioapic_routing[i].gsi_base) |
---|
879 | && (gsi <= mp_ioapic_routing[i].gsi_end)) |
---|
880 | return i; |
---|
881 | } |
---|
882 | |
---|
883 | printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi); |
---|
884 | |
---|
885 | return -1; |
---|
886 | } |
---|
887 | |
---|
888 | |
---|
889 | void __init mp_register_ioapic ( |
---|
890 | u8 id, |
---|
891 | u32 address, |
---|
892 | u32 gsi_base) |
---|
893 | { |
---|
894 | int idx = 0; |
---|
895 | int tmpid; |
---|
896 | |
---|
897 | if (nr_ioapics >= MAX_IO_APICS) { |
---|
898 | printk(KERN_ERR "ERROR: Max # of I/O APICs (%d) exceeded " |
---|
899 | "(found %d)\n", MAX_IO_APICS, nr_ioapics); |
---|
900 | panic("Recompile kernel with bigger MAX_IO_APICS!\n"); |
---|
901 | } |
---|
902 | if (!address) { |
---|
903 | printk(KERN_ERR "WARNING: Bogus (zero) I/O APIC address" |
---|
904 | " found in MADT table, skipping!\n"); |
---|
905 | return; |
---|
906 | } |
---|
907 | |
---|
908 | idx = nr_ioapics++; |
---|
909 | |
---|
910 | mp_ioapics[idx].mpc_type = MP_IOAPIC; |
---|
911 | mp_ioapics[idx].mpc_flags = MPC_APIC_USABLE; |
---|
912 | mp_ioapics[idx].mpc_apicaddr = address; |
---|
913 | |
---|
914 | set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address); |
---|
915 | if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) |
---|
916 | && !APIC_XAPIC(apic_version[boot_cpu_physical_apicid])) |
---|
917 | tmpid = io_apic_get_unique_id(idx, id); |
---|
918 | else |
---|
919 | tmpid = id; |
---|
920 | if (tmpid == -1) { |
---|
921 | nr_ioapics--; |
---|
922 | return; |
---|
923 | } |
---|
924 | mp_ioapics[idx].mpc_apicid = tmpid; |
---|
925 | mp_ioapics[idx].mpc_apicver = io_apic_get_version(idx); |
---|
926 | |
---|
927 | /* |
---|
928 | * Build basic GSI lookup table to facilitate gsi->io_apic lookups |
---|
929 | * and to prevent reprogramming of IOAPIC pins (PCI GSIs). |
---|
930 | */ |
---|
931 | mp_ioapic_routing[idx].apic_id = mp_ioapics[idx].mpc_apicid; |
---|
932 | mp_ioapic_routing[idx].gsi_base = gsi_base; |
---|
933 | mp_ioapic_routing[idx].gsi_end = gsi_base + |
---|
934 | io_apic_get_redir_entries(idx); |
---|
935 | |
---|
936 | printk("IOAPIC[%d]: apic_id %d, version %d, address 0x%x, " |
---|
937 | "GSI %d-%d\n", idx, mp_ioapics[idx].mpc_apicid, |
---|
938 | mp_ioapics[idx].mpc_apicver, mp_ioapics[idx].mpc_apicaddr, |
---|
939 | mp_ioapic_routing[idx].gsi_base, |
---|
940 | mp_ioapic_routing[idx].gsi_end); |
---|
941 | |
---|
942 | return; |
---|
943 | } |
---|
944 | |
---|
945 | |
---|
946 | void __init mp_override_legacy_irq ( |
---|
947 | u8 bus_irq, |
---|
948 | u8 polarity, |
---|
949 | u8 trigger, |
---|
950 | u32 gsi) |
---|
951 | { |
---|
952 | struct mpc_config_intsrc intsrc; |
---|
953 | int ioapic = -1; |
---|
954 | int pin = -1; |
---|
955 | |
---|
956 | /* |
---|
957 | * Convert 'gsi' to 'ioapic.pin'. |
---|
958 | */ |
---|
959 | ioapic = mp_find_ioapic(gsi); |
---|
960 | if (ioapic < 0) |
---|
961 | return; |
---|
962 | pin = gsi - mp_ioapic_routing[ioapic].gsi_base; |
---|
963 | |
---|
964 | /* |
---|
965 | * TBD: This check is for faulty timer entries, where the override |
---|
966 | * erroneously sets the trigger to level, resulting in a HUGE |
---|
967 | * increase of timer interrupts! |
---|
968 | */ |
---|
969 | if ((bus_irq == 0) && (trigger == 3)) |
---|
970 | trigger = 1; |
---|
971 | |
---|
972 | intsrc.mpc_type = MP_INTSRC; |
---|
973 | intsrc.mpc_irqtype = mp_INT; |
---|
974 | intsrc.mpc_irqflag = (trigger << 2) | polarity; |
---|
975 | intsrc.mpc_srcbus = MP_ISA_BUS; |
---|
976 | intsrc.mpc_srcbusirq = bus_irq; /* IRQ */ |
---|
977 | intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid; /* APIC ID */ |
---|
978 | intsrc.mpc_dstirq = pin; /* INTIN# */ |
---|
979 | |
---|
980 | Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, %d-%d\n", |
---|
981 | intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3, |
---|
982 | (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus, |
---|
983 | intsrc.mpc_srcbusirq, intsrc.mpc_dstapic, intsrc.mpc_dstirq); |
---|
984 | |
---|
985 | mp_irqs[mp_irq_entries] = intsrc; |
---|
986 | if (++mp_irq_entries == MAX_IRQ_SOURCES) |
---|
987 | panic("Max # of irq sources exceeded!\n"); |
---|
988 | |
---|
989 | return; |
---|
990 | } |
---|
991 | |
---|
992 | void __init mp_config_acpi_legacy_irqs (void) |
---|
993 | { |
---|
994 | struct mpc_config_intsrc intsrc; |
---|
995 | int i = 0; |
---|
996 | int ioapic = -1; |
---|
997 | |
---|
998 | /* |
---|
999 | * Fabricate the legacy ISA bus (bus #31). |
---|
1000 | */ |
---|
1001 | mp_bus_id_to_type[MP_ISA_BUS] = MP_BUS_ISA; |
---|
1002 | Dprintk("Bus #%d is ISA\n", MP_ISA_BUS); |
---|
1003 | |
---|
1004 | /* |
---|
1005 | * Older generations of ES7000 have no legacy identity mappings |
---|
1006 | */ |
---|
1007 | if (es7000_plat == 1) |
---|
1008 | return; |
---|
1009 | |
---|
1010 | /* |
---|
1011 | * Locate the IOAPIC that manages the ISA IRQs (0-15). |
---|
1012 | */ |
---|
1013 | ioapic = mp_find_ioapic(0); |
---|
1014 | if (ioapic < 0) |
---|
1015 | return; |
---|
1016 | |
---|
1017 | intsrc.mpc_type = MP_INTSRC; |
---|
1018 | intsrc.mpc_irqflag = 0; /* Conforming */ |
---|
1019 | intsrc.mpc_srcbus = MP_ISA_BUS; |
---|
1020 | intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid; |
---|
1021 | |
---|
1022 | /* |
---|
1023 | * Use the default configuration for the IRQs 0-15. Unless |
---|
1024 | * overriden by (MADT) interrupt source override entries. |
---|
1025 | */ |
---|
1026 | for (i = 0; i < 16; i++) { |
---|
1027 | int idx; |
---|
1028 | |
---|
1029 | for (idx = 0; idx < mp_irq_entries; idx++) { |
---|
1030 | struct mpc_config_intsrc *irq = mp_irqs + idx; |
---|
1031 | |
---|
1032 | /* Do we already have a mapping for this ISA IRQ? */ |
---|
1033 | if (irq->mpc_srcbus == MP_ISA_BUS && irq->mpc_srcbusirq == i) |
---|
1034 | break; |
---|
1035 | |
---|
1036 | /* Do we already have a mapping for this IOAPIC pin */ |
---|
1037 | if ((irq->mpc_dstapic == intsrc.mpc_dstapic) && |
---|
1038 | (irq->mpc_dstirq == i)) |
---|
1039 | break; |
---|
1040 | } |
---|
1041 | |
---|
1042 | if (idx != mp_irq_entries) { |
---|
1043 | printk(KERN_DEBUG "ACPI: IRQ%d used by override.\n", i); |
---|
1044 | continue; /* IRQ already used */ |
---|
1045 | } |
---|
1046 | |
---|
1047 | intsrc.mpc_irqtype = mp_INT; |
---|
1048 | intsrc.mpc_srcbusirq = i; /* Identity mapped */ |
---|
1049 | intsrc.mpc_dstirq = i; |
---|
1050 | |
---|
1051 | Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, " |
---|
1052 | "%d-%d\n", intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3, |
---|
1053 | (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus, |
---|
1054 | intsrc.mpc_srcbusirq, intsrc.mpc_dstapic, |
---|
1055 | intsrc.mpc_dstirq); |
---|
1056 | |
---|
1057 | mp_irqs[mp_irq_entries] = intsrc; |
---|
1058 | if (++mp_irq_entries == MAX_IRQ_SOURCES) |
---|
1059 | panic("Max # of irq sources exceeded!\n"); |
---|
1060 | } |
---|
1061 | } |
---|
1062 | |
---|
1063 | #define MAX_GSI_NUM 4096 |
---|
1064 | |
---|
1065 | int mp_register_gsi (u32 gsi, int triggering, int polarity) |
---|
1066 | { |
---|
1067 | int ioapic = -1; |
---|
1068 | int ioapic_pin = 0; |
---|
1069 | int idx, bit = 0; |
---|
1070 | static int pci_irq = 16; |
---|
1071 | /* |
---|
1072 | * Mapping between Global System Interrups, which |
---|
1073 | * represent all possible interrupts, and IRQs |
---|
1074 | * assigned to actual devices. |
---|
1075 | */ |
---|
1076 | static int gsi_to_irq[MAX_GSI_NUM]; |
---|
1077 | |
---|
1078 | #ifdef CONFIG_ACPI_BUS |
---|
1079 | /* Don't set up the ACPI SCI because it's already set up */ |
---|
1080 | if (acpi_fadt.sci_int == gsi) |
---|
1081 | return gsi; |
---|
1082 | #endif |
---|
1083 | |
---|
1084 | ioapic = mp_find_ioapic(gsi); |
---|
1085 | if (ioapic < 0) { |
---|
1086 | printk(KERN_WARNING "No IOAPIC for GSI %u\n", gsi); |
---|
1087 | return gsi; |
---|
1088 | } |
---|
1089 | |
---|
1090 | ioapic_pin = gsi - mp_ioapic_routing[ioapic].gsi_base; |
---|
1091 | |
---|
1092 | if (ioapic_renumber_irq) |
---|
1093 | gsi = ioapic_renumber_irq(ioapic, gsi); |
---|
1094 | |
---|
1095 | /* |
---|
1096 | * Avoid pin reprogramming. PRTs typically include entries |
---|
1097 | * with redundant pin->gsi mappings (but unique PCI devices); |
---|
1098 | * we only program the IOAPIC on the first. |
---|
1099 | */ |
---|
1100 | bit = ioapic_pin % 32; |
---|
1101 | idx = (ioapic_pin < 32) ? 0 : (ioapic_pin / 32); |
---|
1102 | if (idx > 3) { |
---|
1103 | printk(KERN_ERR "Invalid reference to IOAPIC pin " |
---|
1104 | "%d-%d\n", mp_ioapic_routing[ioapic].apic_id, |
---|
1105 | ioapic_pin); |
---|
1106 | return gsi; |
---|
1107 | } |
---|
1108 | if ((1<<bit) & mp_ioapic_routing[ioapic].pin_programmed[idx]) { |
---|
1109 | Dprintk(KERN_DEBUG "Pin %d-%d already programmed\n", |
---|
1110 | mp_ioapic_routing[ioapic].apic_id, ioapic_pin); |
---|
1111 | return gsi_to_irq[gsi]; |
---|
1112 | } |
---|
1113 | |
---|
1114 | mp_ioapic_routing[ioapic].pin_programmed[idx] |= (1<<bit); |
---|
1115 | |
---|
1116 | if (triggering == ACPI_LEVEL_SENSITIVE) { |
---|
1117 | /* |
---|
1118 | * For PCI devices assign IRQs in order, avoiding gaps |
---|
1119 | * due to unused I/O APIC pins. |
---|
1120 | */ |
---|
1121 | int irq = gsi; |
---|
1122 | if (gsi < MAX_GSI_NUM) { |
---|
1123 | /* |
---|
1124 | * Retain the VIA chipset work-around (gsi > 15), but |
---|
1125 | * avoid a problem where the 8254 timer (IRQ0) is setup |
---|
1126 | * via an override (so it's not on pin 0 of the ioapic), |
---|
1127 | * and at the same time, the pin 0 interrupt is a PCI |
---|
1128 | * type. The gsi > 15 test could cause these two pins |
---|
1129 | * to be shared as IRQ0, and they are not shareable. |
---|
1130 | * So test for this condition, and if necessary, avoid |
---|
1131 | * the pin collision. |
---|
1132 | */ |
---|
1133 | if (gsi > 15 || (gsi == 0 && !timer_uses_ioapic_pin_0)) |
---|
1134 | gsi = pci_irq++; |
---|
1135 | #ifdef CONFIG_ACPI_BUS |
---|
1136 | /* |
---|
1137 | * Don't assign IRQ used by ACPI SCI |
---|
1138 | */ |
---|
1139 | if (gsi == acpi_fadt.sci_int) |
---|
1140 | gsi = pci_irq++; |
---|
1141 | #endif |
---|
1142 | gsi_to_irq[irq] = gsi; |
---|
1143 | } else { |
---|
1144 | printk(KERN_ERR "GSI %u is too high\n", gsi); |
---|
1145 | return gsi; |
---|
1146 | } |
---|
1147 | } |
---|
1148 | |
---|
1149 | io_apic_set_pci_routing(ioapic, ioapic_pin, gsi, |
---|
1150 | triggering == ACPI_EDGE_SENSITIVE ? 0 : 1, |
---|
1151 | polarity == ACPI_ACTIVE_HIGH ? 0 : 1); |
---|
1152 | return gsi; |
---|
1153 | } |
---|
1154 | |
---|
1155 | #endif /* CONFIG_X86_IO_APIC */ |
---|
1156 | #endif /* CONFIG_ACPI */ |
---|