1 | /****************************************************************************** |
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2 | * arch/x86/irq.c |
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3 | * |
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4 | * Portions of this file are: |
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5 | * Copyright (C) 1992, 1998 Linus Torvalds, Ingo Molnar |
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6 | */ |
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7 | |
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8 | #include <xen/config.h> |
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9 | #include <xen/init.h> |
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10 | #include <xen/errno.h> |
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11 | #include <xen/event.h> |
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12 | #include <xen/irq.h> |
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13 | #include <xen/perfc.h> |
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14 | #include <xen/sched.h> |
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15 | #include <xen/keyhandler.h> |
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16 | #include <xen/compat.h> |
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17 | #include <asm/current.h> |
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18 | #include <asm/smpboot.h> |
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19 | |
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20 | /* opt_noirqbalance: If true, software IRQ balancing/affinity is disabled. */ |
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21 | int opt_noirqbalance = 0; |
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22 | boolean_param("noirqbalance", opt_noirqbalance); |
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23 | |
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24 | irq_desc_t irq_desc[NR_IRQS]; |
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25 | |
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26 | static void __do_IRQ_guest(int vector); |
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27 | |
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28 | void no_action(int cpl, void *dev_id, struct cpu_user_regs *regs) { } |
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29 | |
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30 | static void enable_none(unsigned int vector) { } |
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31 | static unsigned int startup_none(unsigned int vector) { return 0; } |
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32 | static void disable_none(unsigned int vector) { } |
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33 | static void ack_none(unsigned int vector) |
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34 | { |
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35 | ack_bad_irq(vector); |
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36 | } |
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37 | |
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38 | #define shutdown_none disable_none |
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39 | #define end_none enable_none |
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40 | |
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41 | struct hw_interrupt_type no_irq_type = { |
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42 | "none", |
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43 | startup_none, |
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44 | shutdown_none, |
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45 | enable_none, |
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46 | disable_none, |
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47 | ack_none, |
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48 | end_none |
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49 | }; |
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50 | |
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51 | atomic_t irq_err_count; |
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52 | |
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53 | asmlinkage void do_IRQ(struct cpu_user_regs *regs) |
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54 | { |
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55 | unsigned int vector = regs->entry_vector; |
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56 | irq_desc_t *desc = &irq_desc[vector]; |
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57 | struct irqaction *action; |
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58 | |
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59 | perfc_incr(irqs); |
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60 | |
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61 | spin_lock(&desc->lock); |
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62 | desc->handler->ack(vector); |
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63 | |
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64 | if ( likely(desc->status & IRQ_GUEST) ) |
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65 | { |
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66 | __do_IRQ_guest(vector); |
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67 | spin_unlock(&desc->lock); |
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68 | return; |
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69 | } |
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70 | |
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71 | desc->status &= ~IRQ_REPLAY; |
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72 | desc->status |= IRQ_PENDING; |
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73 | |
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74 | /* |
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75 | * Since we set PENDING, if another processor is handling a different |
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76 | * instance of this same irq, the other processor will take care of it. |
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77 | */ |
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78 | if ( desc->status & (IRQ_DISABLED | IRQ_INPROGRESS) ) |
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79 | goto out; |
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80 | |
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81 | desc->status |= IRQ_INPROGRESS; |
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82 | |
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83 | action = desc->action; |
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84 | while ( desc->status & IRQ_PENDING ) |
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85 | { |
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86 | desc->status &= ~IRQ_PENDING; |
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87 | irq_enter(); |
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88 | spin_unlock_irq(&desc->lock); |
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89 | action->handler(vector_to_irq(vector), action->dev_id, regs); |
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90 | spin_lock_irq(&desc->lock); |
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91 | irq_exit(); |
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92 | } |
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93 | |
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94 | desc->status &= ~IRQ_INPROGRESS; |
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95 | |
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96 | out: |
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97 | desc->handler->end(vector); |
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98 | spin_unlock(&desc->lock); |
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99 | } |
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100 | |
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101 | void free_irq(unsigned int irq) |
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102 | { |
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103 | unsigned int vector = irq_to_vector(irq); |
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104 | irq_desc_t *desc = &irq_desc[vector]; |
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105 | unsigned long flags; |
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106 | |
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107 | spin_lock_irqsave(&desc->lock,flags); |
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108 | desc->action = NULL; |
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109 | desc->depth = 1; |
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110 | desc->status |= IRQ_DISABLED; |
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111 | desc->handler->shutdown(irq); |
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112 | spin_unlock_irqrestore(&desc->lock,flags); |
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113 | |
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114 | /* Wait to make sure it's not being used on another CPU */ |
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115 | do { smp_mb(); } while ( desc->status & IRQ_INPROGRESS ); |
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116 | } |
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117 | |
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118 | int setup_irq(unsigned int irq, struct irqaction *new) |
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119 | { |
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120 | unsigned int vector = irq_to_vector(irq); |
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121 | irq_desc_t *desc = &irq_desc[vector]; |
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122 | unsigned long flags; |
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123 | |
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124 | spin_lock_irqsave(&desc->lock,flags); |
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125 | |
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126 | if ( desc->action != NULL ) |
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127 | { |
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128 | spin_unlock_irqrestore(&desc->lock,flags); |
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129 | return -EBUSY; |
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130 | } |
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131 | |
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132 | desc->action = new; |
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133 | desc->depth = 0; |
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134 | desc->status &= ~IRQ_DISABLED; |
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135 | desc->handler->startup(vector); |
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136 | |
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137 | spin_unlock_irqrestore(&desc->lock,flags); |
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138 | |
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139 | return 0; |
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140 | } |
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141 | |
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142 | |
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143 | /* |
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144 | * HANDLING OF GUEST-BOUND PHYSICAL IRQS |
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145 | */ |
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146 | |
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147 | #define IRQ_MAX_GUESTS 7 |
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148 | typedef struct { |
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149 | u8 nr_guests; |
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150 | u8 in_flight; |
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151 | u8 shareable; |
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152 | u8 ack_type; |
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153 | #define ACKTYPE_NONE 0 /* No final acknowledgement is required */ |
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154 | #define ACKTYPE_UNMASK 1 /* Unmask PIC hardware (from any CPU) */ |
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155 | #define ACKTYPE_EOI 2 /* EOI on the CPU that was interrupted */ |
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156 | cpumask_t cpu_eoi_map; /* CPUs that need to EOI this interrupt */ |
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157 | struct domain *guest[IRQ_MAX_GUESTS]; |
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158 | } irq_guest_action_t; |
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159 | |
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160 | /* |
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161 | * Stack of interrupts awaiting EOI on each CPU. These must be popped in |
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162 | * order, as only the current highest-priority pending irq can be EOIed. |
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163 | */ |
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164 | struct pending_eoi { |
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165 | u8 vector; /* Vector awaiting EOI */ |
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166 | u8 ready; /* Ready for EOI now? */ |
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167 | }; |
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168 | static DEFINE_PER_CPU(struct pending_eoi, pending_eoi[NR_VECTORS]); |
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169 | #define pending_eoi_sp(p) ((p)[NR_VECTORS-1].vector) |
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170 | |
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171 | static void __do_IRQ_guest(int vector) |
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172 | { |
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173 | unsigned int irq = vector_to_irq(vector); |
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174 | irq_desc_t *desc = &irq_desc[vector]; |
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175 | irq_guest_action_t *action = (irq_guest_action_t *)desc->action; |
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176 | struct domain *d; |
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177 | int i, sp; |
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178 | struct pending_eoi *peoi = this_cpu(pending_eoi); |
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179 | |
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180 | if ( unlikely(action->nr_guests == 0) ) |
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181 | { |
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182 | /* An interrupt may slip through while freeing an ACKTYPE_EOI irq. */ |
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183 | ASSERT(action->ack_type == ACKTYPE_EOI); |
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184 | ASSERT(desc->status & IRQ_DISABLED); |
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185 | desc->handler->end(vector); |
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186 | return; |
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187 | } |
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188 | |
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189 | if ( action->ack_type == ACKTYPE_EOI ) |
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190 | { |
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191 | sp = pending_eoi_sp(peoi); |
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192 | ASSERT((sp == 0) || (peoi[sp-1].vector < vector)); |
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193 | ASSERT(sp < (NR_VECTORS-1)); |
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194 | peoi[sp].vector = vector; |
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195 | peoi[sp].ready = 0; |
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196 | pending_eoi_sp(peoi) = sp+1; |
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197 | cpu_set(smp_processor_id(), action->cpu_eoi_map); |
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198 | } |
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199 | |
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200 | for ( i = 0; i < action->nr_guests; i++ ) |
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201 | { |
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202 | d = action->guest[i]; |
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203 | if ( (action->ack_type != ACKTYPE_NONE) && |
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204 | !test_and_set_bit(irq, d->pirq_mask) ) |
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205 | action->in_flight++; |
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206 | send_guest_pirq(d, irq); |
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207 | } |
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208 | } |
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209 | |
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210 | /* Flush all ready EOIs from the top of this CPU's pending-EOI stack. */ |
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211 | static void flush_ready_eoi(void *unused) |
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212 | { |
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213 | struct pending_eoi *peoi = this_cpu(pending_eoi); |
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214 | irq_desc_t *desc; |
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215 | int vector, sp; |
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216 | |
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217 | ASSERT(!local_irq_is_enabled()); |
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218 | |
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219 | sp = pending_eoi_sp(peoi); |
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220 | |
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221 | while ( (--sp >= 0) && peoi[sp].ready ) |
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222 | { |
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223 | vector = peoi[sp].vector; |
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224 | desc = &irq_desc[vector]; |
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225 | spin_lock(&desc->lock); |
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226 | desc->handler->end(vector); |
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227 | spin_unlock(&desc->lock); |
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228 | } |
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229 | |
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230 | pending_eoi_sp(peoi) = sp+1; |
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231 | } |
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232 | |
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233 | static void __set_eoi_ready(irq_desc_t *desc) |
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234 | { |
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235 | irq_guest_action_t *action = (irq_guest_action_t *)desc->action; |
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236 | struct pending_eoi *peoi = this_cpu(pending_eoi); |
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237 | int vector, sp; |
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238 | |
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239 | vector = desc - irq_desc; |
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240 | |
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241 | if ( !(desc->status & IRQ_GUEST) || |
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242 | (action->in_flight != 0) || |
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243 | !cpu_test_and_clear(smp_processor_id(), action->cpu_eoi_map) ) |
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244 | return; |
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245 | |
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246 | sp = pending_eoi_sp(peoi); |
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247 | do { |
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248 | ASSERT(sp > 0); |
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249 | } while ( peoi[--sp].vector != vector ); |
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250 | ASSERT(!peoi[sp].ready); |
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251 | peoi[sp].ready = 1; |
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252 | } |
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253 | |
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254 | /* Mark specified IRQ as ready-for-EOI (if it really is) and attempt to EOI. */ |
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255 | static void set_eoi_ready(void *data) |
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256 | { |
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257 | irq_desc_t *desc = data; |
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258 | |
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259 | ASSERT(!local_irq_is_enabled()); |
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260 | |
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261 | spin_lock(&desc->lock); |
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262 | __set_eoi_ready(desc); |
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263 | spin_unlock(&desc->lock); |
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264 | |
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265 | flush_ready_eoi(NULL); |
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266 | } |
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267 | |
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268 | static void __pirq_guest_eoi(struct domain *d, int irq) |
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269 | { |
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270 | irq_desc_t *desc; |
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271 | irq_guest_action_t *action; |
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272 | cpumask_t cpu_eoi_map; |
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273 | |
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274 | desc = &irq_desc[irq_to_vector(irq)]; |
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275 | action = (irq_guest_action_t *)desc->action; |
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276 | |
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277 | spin_lock_irq(&desc->lock); |
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278 | |
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279 | ASSERT(!test_bit(irq, d->pirq_mask) || |
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280 | (action->ack_type != ACKTYPE_NONE)); |
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281 | |
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282 | if ( unlikely(!test_and_clear_bit(irq, d->pirq_mask)) || |
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283 | unlikely(--action->in_flight != 0) ) |
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284 | { |
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285 | spin_unlock_irq(&desc->lock); |
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286 | return; |
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287 | } |
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288 | |
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289 | if ( action->ack_type == ACKTYPE_UNMASK ) |
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290 | { |
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291 | ASSERT(cpus_empty(action->cpu_eoi_map)); |
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292 | desc->handler->end(irq_to_vector(irq)); |
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293 | spin_unlock_irq(&desc->lock); |
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294 | return; |
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295 | } |
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296 | |
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297 | ASSERT(action->ack_type == ACKTYPE_EOI); |
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298 | |
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299 | cpu_eoi_map = action->cpu_eoi_map; |
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300 | |
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301 | if ( cpu_test_and_clear(smp_processor_id(), cpu_eoi_map) ) |
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302 | { |
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303 | __set_eoi_ready(desc); |
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304 | spin_unlock(&desc->lock); |
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305 | flush_ready_eoi(NULL); |
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306 | local_irq_enable(); |
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307 | } |
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308 | else |
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309 | { |
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310 | spin_unlock_irq(&desc->lock); |
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311 | } |
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312 | |
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313 | if ( !cpus_empty(cpu_eoi_map) ) |
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314 | on_selected_cpus(cpu_eoi_map, set_eoi_ready, desc, 1, 0); |
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315 | } |
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316 | |
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317 | int pirq_guest_eoi(struct domain *d, int irq) |
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318 | { |
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319 | if ( (irq < 0) || (irq >= NR_IRQS) ) |
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320 | return -EINVAL; |
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321 | |
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322 | __pirq_guest_eoi(d, irq); |
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323 | |
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324 | return 0; |
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325 | } |
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326 | |
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327 | int pirq_guest_unmask(struct domain *d) |
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328 | { |
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329 | unsigned int irq; |
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330 | shared_info_t *s = d->shared_info; |
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331 | |
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332 | for ( irq = find_first_bit(d->pirq_mask, NR_IRQS); |
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333 | irq < NR_IRQS; |
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334 | irq = find_next_bit(d->pirq_mask, NR_IRQS, irq+1) ) |
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335 | { |
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336 | if ( !test_bit(d->pirq_to_evtchn[irq], __shared_info_addr(d, s, evtchn_mask)) ) |
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337 | __pirq_guest_eoi(d, irq); |
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338 | } |
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339 | |
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340 | return 0; |
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341 | } |
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342 | |
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343 | extern int ioapic_ack_new; |
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344 | int pirq_acktype(int irq) |
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345 | { |
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346 | irq_desc_t *desc; |
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347 | unsigned int vector; |
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348 | |
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349 | vector = irq_to_vector(irq); |
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350 | if ( vector == 0 ) |
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351 | return ACKTYPE_NONE; |
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352 | |
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353 | desc = &irq_desc[vector]; |
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354 | |
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355 | if ( desc->handler == &no_irq_type ) |
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356 | return ACKTYPE_NONE; |
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357 | |
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358 | /* |
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359 | * Edge-triggered IO-APIC and LAPIC interrupts need no final |
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360 | * acknowledgement: we ACK early during interrupt processing. |
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361 | */ |
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362 | if ( !strcmp(desc->handler->typename, "IO-APIC-edge") || |
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363 | !strcmp(desc->handler->typename, "local-APIC-edge") ) |
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364 | return ACKTYPE_NONE; |
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365 | |
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366 | /* |
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367 | * Level-triggered IO-APIC interrupts need to be acknowledged on the CPU |
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368 | * on which they were received. This is because we tickle the LAPIC to EOI. |
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369 | */ |
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370 | if ( !strcmp(desc->handler->typename, "IO-APIC-level") ) |
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371 | return ioapic_ack_new ? ACKTYPE_EOI : ACKTYPE_UNMASK; |
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372 | |
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373 | /* Legacy PIC interrupts can be acknowledged from any CPU. */ |
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374 | if ( !strcmp(desc->handler->typename, "XT-PIC") ) |
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375 | return ACKTYPE_UNMASK; |
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376 | |
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377 | if ( strstr(desc->handler->typename, "MPIC") ) |
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378 | { |
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379 | if ( desc->status & IRQ_LEVEL ) |
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380 | return (desc->status & IRQ_PER_CPU) ? ACKTYPE_EOI : ACKTYPE_UNMASK; |
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381 | return ACKTYPE_NONE; /* edge-triggered => no final EOI */ |
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382 | } |
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383 | |
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384 | printk("Unknown PIC type '%s' for IRQ %d\n", desc->handler->typename, irq); |
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385 | BUG(); |
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386 | |
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387 | return 0; |
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388 | } |
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389 | |
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390 | int pirq_shared(int irq) |
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391 | { |
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392 | unsigned int vector; |
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393 | irq_desc_t *desc; |
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394 | irq_guest_action_t *action; |
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395 | unsigned long flags; |
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396 | int shared; |
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397 | |
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398 | vector = irq_to_vector(irq); |
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399 | if ( vector == 0 ) |
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400 | return 0; |
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401 | |
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402 | desc = &irq_desc[vector]; |
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403 | |
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404 | spin_lock_irqsave(&desc->lock, flags); |
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405 | action = (irq_guest_action_t *)desc->action; |
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406 | shared = ((desc->status & IRQ_GUEST) && (action->nr_guests > 1)); |
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407 | spin_unlock_irqrestore(&desc->lock, flags); |
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408 | |
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409 | return shared; |
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410 | } |
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411 | |
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412 | int pirq_guest_bind(struct vcpu *v, int irq, int will_share) |
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413 | { |
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414 | unsigned int vector; |
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415 | irq_desc_t *desc; |
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416 | irq_guest_action_t *action; |
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417 | unsigned long flags; |
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418 | int rc = 0; |
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419 | cpumask_t cpumask = CPU_MASK_NONE; |
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420 | |
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421 | retry: |
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422 | vector = irq_to_vector(irq); |
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423 | if ( vector == 0 ) |
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424 | return -EINVAL; |
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425 | |
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426 | desc = &irq_desc[vector]; |
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427 | |
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428 | spin_lock_irqsave(&desc->lock, flags); |
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429 | |
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430 | action = (irq_guest_action_t *)desc->action; |
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431 | |
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432 | if ( !(desc->status & IRQ_GUEST) ) |
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433 | { |
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434 | if ( desc->action != NULL ) |
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435 | { |
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436 | gdprintk(XENLOG_INFO, |
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437 | "Cannot bind IRQ %d to guest. In use by '%s'.\n", |
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438 | irq, desc->action->name); |
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439 | rc = -EBUSY; |
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440 | goto out; |
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441 | } |
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442 | |
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443 | action = xmalloc(irq_guest_action_t); |
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444 | if ( (desc->action = (struct irqaction *)action) == NULL ) |
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445 | { |
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446 | gdprintk(XENLOG_INFO, |
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447 | "Cannot bind IRQ %d to guest. Out of memory.\n", |
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448 | irq); |
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449 | rc = -ENOMEM; |
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450 | goto out; |
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451 | } |
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452 | |
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453 | action->nr_guests = 0; |
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454 | action->in_flight = 0; |
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455 | action->shareable = will_share; |
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456 | action->ack_type = pirq_acktype(irq); |
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457 | cpus_clear(action->cpu_eoi_map); |
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458 | |
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459 | desc->depth = 0; |
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460 | desc->status |= IRQ_GUEST; |
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461 | desc->status &= ~IRQ_DISABLED; |
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462 | desc->handler->startup(vector); |
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463 | |
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464 | /* Attempt to bind the interrupt target to the correct CPU. */ |
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465 | cpu_set(v->processor, cpumask); |
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466 | if ( !opt_noirqbalance && (desc->handler->set_affinity != NULL) ) |
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467 | desc->handler->set_affinity(vector, cpumask); |
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468 | } |
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469 | else if ( !will_share || !action->shareable ) |
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470 | { |
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471 | gdprintk(XENLOG_INFO, "Cannot bind IRQ %d to guest. " |
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472 | "Will not share with others.\n", |
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473 | irq); |
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474 | rc = -EBUSY; |
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475 | goto out; |
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476 | } |
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477 | else if ( action->nr_guests == 0 ) |
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478 | { |
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479 | /* |
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480 | * Indicates that an ACKTYPE_EOI interrupt is being released. |
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481 | * Wait for that to happen before continuing. |
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482 | */ |
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483 | ASSERT(action->ack_type == ACKTYPE_EOI); |
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484 | ASSERT(desc->status & IRQ_DISABLED); |
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485 | spin_unlock_irqrestore(&desc->lock, flags); |
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486 | cpu_relax(); |
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487 | goto retry; |
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488 | } |
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489 | |
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490 | if ( action->nr_guests == IRQ_MAX_GUESTS ) |
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491 | { |
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492 | gdprintk(XENLOG_INFO, "Cannot bind IRQ %d to guest. " |
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493 | "Already at max share.\n", irq); |
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494 | rc = -EBUSY; |
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495 | goto out; |
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496 | } |
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497 | |
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498 | action->guest[action->nr_guests++] = v->domain; |
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499 | |
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500 | out: |
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501 | spin_unlock_irqrestore(&desc->lock, flags); |
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502 | return rc; |
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503 | } |
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504 | |
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505 | int pirq_guest_unbind(struct domain *d, int irq) |
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506 | { |
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507 | unsigned int vector = irq_to_vector(irq); |
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508 | irq_desc_t *desc = &irq_desc[vector]; |
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509 | irq_guest_action_t *action; |
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510 | cpumask_t cpu_eoi_map; |
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511 | unsigned long flags; |
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512 | int i; |
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513 | |
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514 | BUG_ON(vector == 0); |
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515 | |
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516 | spin_lock_irqsave(&desc->lock, flags); |
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517 | |
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518 | action = (irq_guest_action_t *)desc->action; |
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519 | |
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520 | i = 0; |
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521 | while ( action->guest[i] && (action->guest[i] != d) ) |
---|
522 | i++; |
---|
523 | memmove(&action->guest[i], &action->guest[i+1], IRQ_MAX_GUESTS-i-1); |
---|
524 | action->nr_guests--; |
---|
525 | |
---|
526 | switch ( action->ack_type ) |
---|
527 | { |
---|
528 | case ACKTYPE_UNMASK: |
---|
529 | if ( test_and_clear_bit(irq, d->pirq_mask) && |
---|
530 | (--action->in_flight == 0) ) |
---|
531 | desc->handler->end(vector); |
---|
532 | break; |
---|
533 | case ACKTYPE_EOI: |
---|
534 | /* NB. If #guests == 0 then we clear the eoi_map later on. */ |
---|
535 | if ( test_and_clear_bit(irq, d->pirq_mask) && |
---|
536 | (--action->in_flight == 0) && |
---|
537 | (action->nr_guests != 0) ) |
---|
538 | { |
---|
539 | cpu_eoi_map = action->cpu_eoi_map; |
---|
540 | spin_unlock_irqrestore(&desc->lock, flags); |
---|
541 | on_selected_cpus(cpu_eoi_map, set_eoi_ready, desc, 1, 0); |
---|
542 | spin_lock_irqsave(&desc->lock, flags); |
---|
543 | } |
---|
544 | break; |
---|
545 | } |
---|
546 | |
---|
547 | /* |
---|
548 | * The guest cannot re-bind to this IRQ until this function returns. So, |
---|
549 | * when we have flushed this IRQ from pirq_mask, it should remain flushed. |
---|
550 | */ |
---|
551 | BUG_ON(test_bit(irq, d->pirq_mask)); |
---|
552 | |
---|
553 | if ( action->nr_guests != 0 ) |
---|
554 | goto out; |
---|
555 | |
---|
556 | BUG_ON(action->in_flight != 0); |
---|
557 | |
---|
558 | /* Disabling IRQ before releasing the desc_lock avoids an IRQ storm. */ |
---|
559 | desc->depth = 1; |
---|
560 | desc->status |= IRQ_DISABLED; |
---|
561 | desc->handler->disable(vector); |
---|
562 | |
---|
563 | /* |
---|
564 | * Mark any remaining pending EOIs as ready to flush. |
---|
565 | * NOTE: We will need to make this a stronger barrier if in future we allow |
---|
566 | * an interrupt vectors to be re-bound to a different PIC. In that case we |
---|
567 | * would need to flush all ready EOIs before returning as otherwise the |
---|
568 | * desc->handler could change and we would call the wrong 'end' hook. |
---|
569 | */ |
---|
570 | cpu_eoi_map = action->cpu_eoi_map; |
---|
571 | if ( !cpus_empty(cpu_eoi_map) ) |
---|
572 | { |
---|
573 | BUG_ON(action->ack_type != ACKTYPE_EOI); |
---|
574 | spin_unlock_irqrestore(&desc->lock, flags); |
---|
575 | on_selected_cpus(cpu_eoi_map, set_eoi_ready, desc, 1, 1); |
---|
576 | spin_lock_irqsave(&desc->lock, flags); |
---|
577 | } |
---|
578 | |
---|
579 | BUG_ON(!cpus_empty(action->cpu_eoi_map)); |
---|
580 | |
---|
581 | desc->action = NULL; |
---|
582 | xfree(action); |
---|
583 | desc->status &= ~IRQ_GUEST; |
---|
584 | desc->handler->shutdown(vector); |
---|
585 | |
---|
586 | out: |
---|
587 | spin_unlock_irqrestore(&desc->lock, flags); |
---|
588 | return 0; |
---|
589 | } |
---|
590 | |
---|
591 | extern void dump_ioapic_irq_info(void); |
---|
592 | |
---|
593 | static void dump_irqs(unsigned char key) |
---|
594 | { |
---|
595 | int i, irq, vector; |
---|
596 | irq_desc_t *desc; |
---|
597 | irq_guest_action_t *action; |
---|
598 | struct domain *d; |
---|
599 | unsigned long flags; |
---|
600 | |
---|
601 | printk("Guest interrupt information:\n"); |
---|
602 | |
---|
603 | for ( irq = 0; irq < NR_IRQS; irq++ ) |
---|
604 | { |
---|
605 | vector = irq_to_vector(irq); |
---|
606 | if ( vector == 0 ) |
---|
607 | continue; |
---|
608 | |
---|
609 | desc = &irq_desc[vector]; |
---|
610 | |
---|
611 | spin_lock_irqsave(&desc->lock, flags); |
---|
612 | |
---|
613 | if ( desc->status & IRQ_GUEST ) |
---|
614 | { |
---|
615 | action = (irq_guest_action_t *)desc->action; |
---|
616 | |
---|
617 | printk(" IRQ%3d Vec%3d: type=%-15s status=%08x " |
---|
618 | "in-flight=%d domain-list=", |
---|
619 | irq, vector, desc->handler->typename, |
---|
620 | desc->status, action->in_flight); |
---|
621 | |
---|
622 | for ( i = 0; i < action->nr_guests; i++ ) |
---|
623 | { |
---|
624 | d = action->guest[i]; |
---|
625 | printk("%u(%c%c%c%c)", |
---|
626 | d->domain_id, |
---|
627 | (test_bit(d->pirq_to_evtchn[irq], |
---|
628 | shared_info_addr(d, evtchn_pending)) ? |
---|
629 | 'P' : '-'), |
---|
630 | (test_bit(d->pirq_to_evtchn[irq]/BITS_PER_GUEST_LONG(d), |
---|
631 | vcpu_info_addr(d->vcpu[0], evtchn_pending_sel)) ? |
---|
632 | 'S' : '-'), |
---|
633 | (test_bit(d->pirq_to_evtchn[irq], |
---|
634 | shared_info_addr(d, evtchn_mask)) ? |
---|
635 | 'M' : '-'), |
---|
636 | (test_bit(irq, d->pirq_mask) ? |
---|
637 | 'M' : '-')); |
---|
638 | if ( i != action->nr_guests ) |
---|
639 | printk(","); |
---|
640 | } |
---|
641 | |
---|
642 | printk("\n"); |
---|
643 | } |
---|
644 | |
---|
645 | spin_unlock_irqrestore(&desc->lock, flags); |
---|
646 | } |
---|
647 | |
---|
648 | dump_ioapic_irq_info(); |
---|
649 | } |
---|
650 | |
---|
651 | static int __init setup_dump_irqs(void) |
---|
652 | { |
---|
653 | register_keyhandler('i', dump_irqs, "dump interrupt bindings"); |
---|
654 | return 0; |
---|
655 | } |
---|
656 | __initcall(setup_dump_irqs); |
---|