1 | /* |
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2 | * hvm/pmtimer.c: emulation of the ACPI PM timer |
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3 | * |
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4 | * Copyright (c) 2007, XenSource inc. |
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5 | * Copyright (c) 2006, Intel Corporation. |
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6 | * |
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7 | * This program is free software; you can redistribute it and/or modify it |
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8 | * under the terms and conditions of the GNU General Public License, |
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9 | * version 2, as published by the Free Software Foundation. |
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10 | * |
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11 | * This program is distributed in the hope it will be useful, but WITHOUT |
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12 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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13 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
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14 | * more details. |
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15 | * |
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16 | * You should have received a copy of the GNU General Public License along with |
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17 | * this program; if not, write to the Free Software Foundation, Inc., 59 Temple |
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18 | * Place - Suite 330, Boston, MA 02111-1307 USA. |
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19 | */ |
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20 | |
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21 | #include <asm/hvm/vpt.h> |
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22 | #include <asm/hvm/io.h> |
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23 | #include <asm/hvm/support.h> |
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24 | |
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25 | /* Slightly more readable port I/O addresses for the registers we intercept */ |
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26 | #define PM1a_STS_ADDR (ACPI_PM1A_EVT_BLK_ADDRESS) |
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27 | #define PM1a_EN_ADDR (ACPI_PM1A_EVT_BLK_ADDRESS + 2) |
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28 | #define TMR_VAL_ADDR (ACPI_PM_TMR_BLK_ADDRESS) |
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29 | |
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30 | /* The interesting bits of the PM1a_STS register */ |
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31 | #define TMR_STS (1 << 0) |
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32 | #define PWRBTN_STS (1 << 5) |
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33 | #define GBL_STS (1 << 8) |
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34 | |
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35 | /* The same in PM1a_EN */ |
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36 | #define TMR_EN (1 << 0) |
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37 | #define PWRBTN_EN (1 << 5) |
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38 | #define GBL_EN (1 << 8) |
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39 | |
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40 | /* Mask of bits in PM1a_STS that can generate an SCI. Although the ACPI |
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41 | * spec lists other bits, the PIIX4, which we are emulating, only |
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42 | * supports these three. For now, we only use TMR_STS; in future we |
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43 | * will let qemu set the other bits */ |
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44 | #define SCI_MASK (TMR_STS|PWRBTN_STS|GBL_STS) |
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45 | |
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46 | /* SCI IRQ number (must match SCI_INT number in ACPI FADT in hvmloader) */ |
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47 | #define SCI_IRQ 9 |
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48 | |
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49 | /* We provide a 32-bit counter (must match the TMR_VAL_EXT bit in the FADT) */ |
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50 | #define TMR_VAL_MASK (0xffffffff) |
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51 | #define TMR_VAL_MSB (0x80000000) |
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52 | |
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53 | |
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54 | /* Dispatch SCIs based on the PM1a_STS and PM1a_EN registers */ |
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55 | static void pmt_update_sci(PMTState *s) |
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56 | { |
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57 | if ( s->pm.pm1a_en & s->pm.pm1a_sts & SCI_MASK ) |
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58 | hvm_isa_irq_assert(s->vcpu->domain, SCI_IRQ); |
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59 | else |
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60 | hvm_isa_irq_deassert(s->vcpu->domain, SCI_IRQ); |
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61 | } |
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62 | |
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63 | /* Set the correct value in the timer, accounting for time elapsed |
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64 | * since the last time we did that. */ |
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65 | static void pmt_update_time(PMTState *s) |
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66 | { |
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67 | uint64_t curr_gtime; |
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68 | uint32_t msb = s->pm.tmr_val & TMR_VAL_MSB; |
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69 | |
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70 | /* Update the timer */ |
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71 | curr_gtime = hvm_get_guest_time(s->vcpu); |
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72 | s->pm.tmr_val += ((curr_gtime - s->last_gtime) * s->scale) >> 32; |
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73 | s->pm.tmr_val &= TMR_VAL_MASK; |
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74 | s->last_gtime = curr_gtime; |
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75 | |
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76 | /* If the counter's MSB has changed, set the status bit */ |
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77 | if ( (s->pm.tmr_val & TMR_VAL_MSB) != msb ) |
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78 | { |
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79 | s->pm.pm1a_sts |= TMR_STS; |
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80 | pmt_update_sci(s); |
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81 | } |
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82 | } |
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83 | |
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84 | /* This function should be called soon after each time the MSB of the |
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85 | * pmtimer register rolls over, to make sure we update the status |
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86 | * registers and SCI at least once per rollover */ |
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87 | static void pmt_timer_callback(void *opaque) |
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88 | { |
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89 | PMTState *s = opaque; |
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90 | uint32_t pmt_cycles_until_flip; |
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91 | uint64_t time_until_flip; |
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92 | |
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93 | /* Recalculate the timer and make sure we get an SCI if we need one */ |
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94 | pmt_update_time(s); |
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95 | |
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96 | /* How close are we to the next MSB flip? */ |
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97 | pmt_cycles_until_flip = TMR_VAL_MSB - (s->pm.tmr_val & (TMR_VAL_MSB - 1)); |
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98 | |
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99 | /* Overall time between MSB flips */ |
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100 | time_until_flip = (1000000000ULL << 31) / FREQUENCE_PMTIMER; |
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101 | |
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102 | /* Reduced appropriately */ |
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103 | time_until_flip = (time_until_flip * pmt_cycles_until_flip) / (1ULL<<31); |
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104 | |
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105 | /* Wake up again near the next bit-flip */ |
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106 | set_timer(&s->timer, NOW() + time_until_flip + MILLISECS(1)); |
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107 | } |
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108 | |
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109 | |
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110 | /* Handle port I/O to the PM1a_STS and PM1a_EN registers */ |
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111 | static int handle_evt_io(ioreq_t *p) |
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112 | { |
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113 | struct vcpu *v = current; |
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114 | PMTState *s = &v->domain->arch.hvm_domain.pl_time.vpmt; |
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115 | uint32_t addr, data, byte; |
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116 | int i; |
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117 | |
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118 | if ( p->dir == 0 ) /* Write */ |
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119 | { |
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120 | /* Handle this I/O one byte at a time */ |
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121 | for ( i = p->size, addr = p->addr, data = p->data; |
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122 | i > 0; |
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123 | i--, addr++, data >>= 8 ) |
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124 | { |
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125 | byte = data & 0xff; |
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126 | switch(addr) |
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127 | { |
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128 | /* PM1a_STS register bits are write-to-clear */ |
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129 | case PM1a_STS_ADDR: |
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130 | s->pm.pm1a_sts &= ~byte; |
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131 | break; |
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132 | case PM1a_STS_ADDR + 1: |
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133 | s->pm.pm1a_sts &= ~(byte << 8); |
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134 | break; |
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135 | |
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136 | case PM1a_EN_ADDR: |
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137 | s->pm.pm1a_en = (s->pm.pm1a_en & 0xff00) | byte; |
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138 | break; |
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139 | case PM1a_EN_ADDR + 1: |
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140 | s->pm.pm1a_en = (s->pm.pm1a_en & 0xff) | (byte << 8); |
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141 | break; |
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142 | |
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143 | default: |
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144 | gdprintk(XENLOG_WARNING, |
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145 | "Bad ACPI PM register write: %"PRIu64 |
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146 | " bytes (%#"PRIx64") at %"PRIx64"\n", |
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147 | p->size, p->data, p->addr); |
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148 | } |
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149 | } |
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150 | /* Fix up the SCI state to match the new register state */ |
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151 | pmt_update_sci(s); |
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152 | } |
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153 | else /* Read */ |
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154 | { |
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155 | data = s->pm.pm1a_sts | (((uint32_t) s->pm.pm1a_en) << 16); |
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156 | data >>= 8 * (p->addr - PM1a_STS_ADDR); |
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157 | if ( p->size == 1 ) data &= 0xff; |
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158 | else if ( p->size == 2 ) data &= 0xffff; |
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159 | p->data = data; |
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160 | } |
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161 | return 1; |
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162 | } |
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163 | |
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164 | |
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165 | /* Handle port I/O to the TMR_VAL register */ |
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166 | static int handle_pmt_io(ioreq_t *p) |
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167 | { |
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168 | struct vcpu *v = current; |
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169 | PMTState *s = &v->domain->arch.hvm_domain.pl_time.vpmt; |
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170 | |
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171 | if (p->size != 4 || |
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172 | p->data_is_ptr || |
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173 | p->type != IOREQ_TYPE_PIO){ |
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174 | printk("HVM_PMT: wrong PM timer IO\n"); |
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175 | return 1; |
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176 | } |
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177 | |
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178 | if (p->dir == 0) { /* write */ |
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179 | /* PM_TMR_BLK is read-only */ |
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180 | return 1; |
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181 | } else if (p->dir == 1) { /* read */ |
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182 | pmt_update_time(s); |
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183 | p->data = s->pm.tmr_val; |
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184 | return 1; |
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185 | } |
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186 | return 0; |
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187 | } |
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188 | |
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189 | static int pmtimer_save(struct domain *d, hvm_domain_context_t *h) |
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190 | { |
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191 | PMTState *s = &d->arch.hvm_domain.pl_time.vpmt; |
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192 | uint32_t msb = s->pm.tmr_val & TMR_VAL_MSB; |
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193 | uint32_t x; |
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194 | |
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195 | /* Update the counter to the guest's current time. We always save |
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196 | * with the domain paused, so the saved time should be after the |
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197 | * last_gtime, but just in case, make sure we only go forwards */ |
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198 | x = ((s->vcpu->arch.hvm_vcpu.guest_time - s->last_gtime) * s->scale) >> 32; |
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199 | if ( x < 1UL<<31 ) |
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200 | s->pm.tmr_val += x; |
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201 | if ( (s->pm.tmr_val & TMR_VAL_MSB) != msb ) |
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202 | s->pm.pm1a_sts |= TMR_STS; |
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203 | /* No point in setting the SCI here because we'll already have saved the |
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204 | * IRQ and *PIC state; we'll fix it up when we restore the domain */ |
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205 | |
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206 | return hvm_save_entry(PMTIMER, 0, h, &s->pm); |
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207 | } |
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208 | |
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209 | static int pmtimer_load(struct domain *d, hvm_domain_context_t *h) |
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210 | { |
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211 | PMTState *s = &d->arch.hvm_domain.pl_time.vpmt; |
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212 | |
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213 | /* Reload the registers */ |
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214 | if ( hvm_load_entry(PMTIMER, h, &s->pm) ) |
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215 | return -EINVAL; |
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216 | |
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217 | /* Calculate future counter values from now. */ |
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218 | s->last_gtime = hvm_get_guest_time(s->vcpu); |
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219 | |
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220 | /* Set the SCI state from the registers */ |
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221 | pmt_update_sci(s); |
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222 | |
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223 | return 0; |
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224 | } |
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225 | |
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226 | HVM_REGISTER_SAVE_RESTORE(PMTIMER, pmtimer_save, pmtimer_load, |
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227 | 1, HVMSR_PER_DOM); |
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228 | |
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229 | |
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230 | void pmtimer_init(struct vcpu *v) |
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231 | { |
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232 | PMTState *s = &v->domain->arch.hvm_domain.pl_time.vpmt; |
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233 | |
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234 | s->pm.tmr_val = 0; |
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235 | s->pm.pm1a_sts = 0; |
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236 | s->pm.pm1a_en = 0; |
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237 | |
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238 | s->scale = ((uint64_t)FREQUENCE_PMTIMER << 32) / ticks_per_sec(v); |
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239 | s->vcpu = v; |
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240 | |
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241 | /* Intercept port I/O (need two handlers because PM1a_CNT is between |
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242 | * PM1a_EN and TMR_VAL and is handled by qemu) */ |
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243 | register_portio_handler(v->domain, TMR_VAL_ADDR, 4, handle_pmt_io); |
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244 | register_portio_handler(v->domain, PM1a_STS_ADDR, 4, handle_evt_io); |
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245 | |
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246 | /* Set up callback to fire SCIs when the MSB of TMR_VAL changes */ |
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247 | init_timer(&s->timer, pmt_timer_callback, s, v->processor); |
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248 | pmt_timer_callback(s); |
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249 | } |
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250 | |
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251 | |
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252 | void pmtimer_deinit(struct domain *d) |
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253 | { |
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254 | PMTState *s = &d->arch.hvm_domain.pl_time.vpmt; |
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255 | kill_timer(&s->timer); |
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256 | } |
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