1 | /* |
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2 | * This program is free software; you can redistribute it and/or modify |
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3 | * it under the terms of the GNU General Public License as published by |
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4 | * the Free Software Foundation; either version 2 of the License, or |
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5 | * (at your option) any later version. |
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6 | * |
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7 | * This program is distributed in the hope that it will be useful, |
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8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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10 | * GNU General Public License for more details. |
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11 | * |
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12 | * You should have received a copy of the GNU General Public License |
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13 | * along with this program; if not, write to the Free Software |
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14 | * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. |
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15 | * |
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16 | * Copyright (C) IBM Corp. 2005 |
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17 | * |
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18 | * Authors: Jimi Xenidis <jimix@watson.ibm.com> |
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19 | */ |
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20 | |
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21 | #undef DEBUG |
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22 | #undef DEBUG_LOW |
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23 | |
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24 | #include <xen/config.h> |
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25 | #include <xen/types.h> |
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26 | #include <xen/sched.h> |
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27 | #include <xen/init.h> |
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28 | #include <public/xen.h> |
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29 | #include <asm/current.h> |
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30 | #include <asm/papr.h> |
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31 | #include <asm/hcalls.h> |
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32 | #include <asm/platform.h> |
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33 | |
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34 | #ifdef DEBUG |
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35 | #define DBG(fmt...) printk(fmt) |
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36 | #else |
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37 | #define DBG(fmt...) |
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38 | #endif |
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39 | #ifdef DEBUG_LOW |
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40 | #define DBG_LOW(fmt...) printk(fmt) |
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41 | #else |
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42 | #define DBG_LOW(fmt...) |
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43 | #endif |
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44 | |
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45 | #ifdef USE_PTE_INSERT |
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46 | static inline void pte_insert(union pte volatile *pte, |
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47 | ulong vsid, ulong rpn, ulong lrpn) |
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48 | { |
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49 | /* |
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50 | * It's required that external locking be done to provide |
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51 | * exclusion between the choices of insertion points. Any valid |
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52 | * choice of pte requires that the pte be invalid upon entry to |
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53 | * this function. |
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54 | */ |
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55 | |
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56 | ASSERT( (pte->bits.v == 0) ); |
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57 | |
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58 | /* Set shadow word. */ |
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59 | (void)lrpn; |
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60 | |
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61 | /* Set the second word first so the valid bit is the last thing set */ |
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62 | pte->words.rpn = rpn; |
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63 | |
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64 | /* Guarantee the second word is visible before the valid bit */ |
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65 | __asm__ __volatile__("eieio" : : : "memory"); |
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66 | |
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67 | /* Now set the first word including the valid bit */ |
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68 | pte->words.vsid = vsid; |
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69 | /* Architecturally this instruction will cause a heavier operation |
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70 | * if this one is not supported. note: on come machines like Cell |
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71 | * this coul dbe a nop */ |
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72 | __asm__ __volatile__("ptesync" : : : "memory"); |
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73 | } |
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74 | #endif |
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75 | |
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76 | /* |
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77 | * POWER Arch 2.03 Sec 4.12.1 (Yes 970 is one) |
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78 | * |
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79 | * when a tlbsync instruction has been executed by a processor in a |
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80 | * given partition, a ptesync instruction must be executed by that |
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81 | * processor before a tlbie or tlbsync instruction is executed by |
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82 | * another processor in that partition. |
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83 | * |
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84 | * So for now, here is a BFLock to deal with it, the lock should be per-domain. |
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85 | * |
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86 | * XXX Will need to audit all tlb usege soon enough. |
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87 | */ |
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88 | |
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89 | static DEFINE_SPINLOCK(native_tlbie_lock); |
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90 | static void pte_tlbie(union pte volatile *pte, ulong ptex) |
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91 | { |
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92 | ulong va; |
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93 | ulong vsid; |
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94 | ulong group; |
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95 | ulong pi; |
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96 | ulong pi_high; |
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97 | |
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98 | vsid = pte->bits.avpn >> 5; |
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99 | group = ptex >> 3; |
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100 | if (pte->bits.h) { |
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101 | group = ~group; |
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102 | } |
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103 | pi = (vsid ^ group) & 0x7ff; |
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104 | pi_high = (pte->bits.avpn & 0x1f) << 11; |
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105 | pi |= pi_high; |
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106 | va = (pi << 12) | (vsid << 28); |
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107 | va &= ~(0xffffULL << 48); |
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108 | |
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109 | spin_lock(&native_tlbie_lock); |
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110 | #ifndef FLUSH_THE_WHOLE_THING |
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111 | if (pte->bits.l) { |
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112 | va |= (pte->bits.rpn & 1); |
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113 | asm volatile("ptesync ;tlbie %0,1" : : "r"(va) : "memory"); |
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114 | } else { |
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115 | asm volatile("ptesync; tlbie %0,0" : : "r"(va) : "memory"); |
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116 | } |
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117 | asm volatile("eieio; tlbsync; ptesync" : : : "memory"); |
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118 | #else |
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119 | { |
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120 | unsigned i; |
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121 | ulong rb; |
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122 | |
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123 | for (i = 0; i < 256; i++) { |
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124 | rb = i; |
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125 | rb <<= 12; |
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126 | asm volatile("ptesync; tlbie %0,0; eieio; tlbsync; ptesync; isync" |
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127 | : "=r" (rb): : "memory"); |
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128 | asm volatile("ptesync; tlbie %0,1; eieio; tlbsync; ptesync; isync" |
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129 | : "=r" (rb): : "memory"); |
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130 | } |
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131 | } |
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132 | #endif |
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133 | spin_unlock(&native_tlbie_lock); |
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134 | } |
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135 | |
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136 | long pte_enter(ulong flags, ulong ptex, ulong vsid, ulong rpn) |
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137 | { |
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138 | union pte pte; |
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139 | union pte volatile *ppte; |
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140 | struct domain_htab *htab; |
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141 | int lp_bits = 0; |
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142 | int pgshift = PAGE_SHIFT; |
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143 | ulong idx; |
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144 | int limit = 0; /* how many PTEs to examine in the PTEG */ |
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145 | ulong pfn; |
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146 | ulong mfn; |
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147 | struct vcpu *v = get_current(); |
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148 | struct domain *d = v->domain; |
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149 | int mtype; |
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150 | struct page_info *pg = NULL; |
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151 | struct domain *f = NULL; |
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152 | |
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153 | |
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154 | htab = &d->arch.htab; |
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155 | if (ptex > (1UL << htab->log_num_ptes)) { |
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156 | DBG("%s: bad ptex: 0x%lx\n", __func__, ptex); |
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157 | return H_Parameter; |
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158 | } |
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159 | |
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160 | /* use local HPTE to avoid manual shifting & masking */ |
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161 | pte.words.vsid = vsid; |
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162 | pte.words.rpn = rpn; |
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163 | |
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164 | if ( pte.bits.l ) { /* large page? */ |
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165 | /* figure out the page size for the selected large page */ |
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166 | ulong lp_rpn = pte.bits.rpn; |
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167 | uint lp_size = 0; |
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168 | |
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169 | while ( lp_rpn & 0x1 ) { |
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170 | lp_rpn >>= 1; |
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171 | lp_bits = ((lp_bits << 1) | 0x1); |
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172 | lp_size++; |
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173 | } |
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174 | |
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175 | if ( lp_size >= d->arch.large_page_sizes ) { |
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176 | DBG("%s: attempt to use unsupported lp_size %d\n", |
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177 | __func__, lp_size); |
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178 | return H_Parameter; |
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179 | } |
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180 | |
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181 | /* get correct pgshift value */ |
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182 | pgshift = d->arch.large_page_order[lp_size] + PAGE_SHIFT; |
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183 | } |
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184 | |
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185 | /* get the correct logical RPN in terms of 4K pages need to mask |
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186 | * off lp bits and unused arpn bits if this is a large page */ |
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187 | |
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188 | pfn = ~0ULL << (pgshift - PAGE_SHIFT); |
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189 | pfn = pte.bits.rpn & pfn; |
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190 | |
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191 | mfn = pfn2mfn(d, pfn, &mtype); |
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192 | if (mfn == INVALID_MFN) { |
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193 | DBG("%s: Bad PFN: 0x%lx\n", __func__, pfn); |
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194 | return H_Parameter; |
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195 | } |
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196 | |
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197 | if (mtype == PFN_TYPE_IO && !d->is_privileged) { |
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198 | /* only a privilaged dom can access outside IO space */ |
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199 | DBG("%s: unprivileged access to physical page: 0x%lx\n", |
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200 | __func__, pfn); |
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201 | return H_Privilege; |
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202 | } |
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203 | if (mtype == PFN_TYPE_IO) { |
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204 | if ( !((pte.bits.w == 0) |
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205 | && (pte.bits.i == 1) |
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206 | && (pte.bits.g == 1)) ) { |
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207 | DBG("%s: expecting an IO WIMG " |
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208 | "w=%x i=%d m=%d, g=%d\n word 0x%lx\n", __func__, |
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209 | pte.bits.w, pte.bits.i, pte.bits.m, pte.bits.g, |
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210 | pte.words.rpn); |
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211 | return H_Parameter; |
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212 | } |
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213 | } |
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214 | if (mtype == PFN_TYPE_GNTTAB) { |
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215 | DBG("%s: Dom[%d] mapping grant table: 0x%lx\n", |
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216 | __func__, d->domain_id, pfn << PAGE_SHIFT); |
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217 | pte.bits.i = 0; |
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218 | pte.bits.g = 0; |
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219 | } |
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220 | /* fixup the RPN field of our local PTE copy */ |
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221 | pte.bits.rpn = mfn | lp_bits; |
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222 | |
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223 | /* clear reserved bits in high word */ |
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224 | pte.bits.lock = 0x0; |
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225 | pte.bits.res = 0x0; |
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226 | |
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227 | /* clear reserved bits in low word */ |
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228 | pte.bits.pp0 = 0x0; |
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229 | pte.bits.ts = 0x0; |
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230 | pte.bits.res2 = 0x0; |
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231 | |
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232 | if (mtype == PFN_TYPE_FOREIGN) { |
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233 | pg = mfn_to_page(mfn); |
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234 | f = page_get_owner(pg); |
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235 | |
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236 | BUG_ON(f == d); |
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237 | |
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238 | if (unlikely(!get_domain(f))) { |
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239 | DBG("%s: Rescinded, no domain: 0x%lx\n", __func__, pfn); |
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240 | return H_Rescinded; |
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241 | } |
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242 | if (unlikely(!get_page(pg, f))) { |
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243 | put_domain(f); |
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244 | DBG("%s: Rescinded, no page: 0x%lx\n", __func__, pfn); |
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245 | return H_Rescinded; |
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246 | } |
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247 | } |
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248 | |
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249 | if ( !(flags & H_EXACT) ) { |
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250 | /* PTEG (not specific PTE); clear 3 lowest bits */ |
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251 | ptex &= ~0x7UL; |
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252 | limit = 7; |
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253 | } |
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254 | |
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255 | /* data manipulations should be done prior to the pte insertion. */ |
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256 | if ( flags & H_ZERO_PAGE ) { |
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257 | ulong pg = mfn << PAGE_SHIFT; |
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258 | ulong pgs = 1UL << pgshift; |
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259 | |
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260 | while (pgs > 0) { |
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261 | clear_page((void *)pg); |
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262 | pg += PAGE_SIZE; |
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263 | --pgs; |
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264 | } |
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265 | } |
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266 | |
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267 | if ( flags & H_ICACHE_INVALIDATE ) { |
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268 | ulong k; |
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269 | ulong addr = mfn << PAGE_SHIFT; |
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270 | |
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271 | for (k = 0; k < (1UL << pgshift); k += L1_CACHE_BYTES) { |
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272 | dcbst(addr + k); |
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273 | sync(); |
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274 | icbi(addr + k); |
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275 | sync(); |
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276 | isync(); |
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277 | } |
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278 | } |
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279 | |
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280 | if ( flags & H_ICACHE_SYNCHRONIZE ) { |
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281 | ulong k; |
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282 | ulong addr = mfn << PAGE_SHIFT; |
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283 | for (k = 0; k < (1UL << pgshift); k += L1_CACHE_BYTES) { |
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284 | icbi(addr + k); |
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285 | sync(); |
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286 | isync(); |
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287 | } |
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288 | } |
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289 | |
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290 | for (idx = ptex; idx <= ptex + limit; idx++) { |
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291 | ppte = &htab->map[idx]; |
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292 | |
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293 | if ( ppte->bits.v == 0 && ppte->bits.lock == 0) { |
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294 | /* got it */ |
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295 | |
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296 | asm volatile( |
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297 | "std %1, 8(%0); eieio; std %2, 0(%0); ptesync" |
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298 | : |
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299 | : "b" (ppte), "r" (pte.words.rpn), "r" (pte.words.vsid) |
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300 | : "memory"); |
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301 | |
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302 | return idx; |
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303 | } |
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304 | } |
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305 | |
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306 | /* If the PTEG is full then no additional values are returned. */ |
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307 | DBG("%s: PTEG FULL\n", __func__); |
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308 | |
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309 | if (pg != NULL) |
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310 | put_page(pg); |
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311 | |
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312 | if (f != NULL) |
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313 | put_domain(f); |
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314 | |
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315 | return H_PTEG_Full; |
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316 | } |
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317 | |
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318 | static void h_enter(struct cpu_user_regs *regs) |
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319 | { |
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320 | ulong flags = regs->gprs[4]; |
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321 | ulong ptex = regs->gprs[5]; |
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322 | ulong vsid = regs->gprs[6]; |
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323 | ulong rpn = regs->gprs[7]; |
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324 | long ret; |
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325 | |
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326 | ret = pte_enter(flags, ptex, vsid, rpn); |
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327 | |
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328 | if (ret >= 0) { |
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329 | regs->gprs[3] = H_Success; |
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330 | regs->gprs[4] = ret; |
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331 | } else |
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332 | regs->gprs[3] = ret; |
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333 | } |
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334 | |
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335 | static void h_protect(struct cpu_user_regs *regs) |
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336 | { |
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337 | ulong flags = regs->gprs[4]; |
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338 | ulong ptex = regs->gprs[5]; |
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339 | ulong avpn = regs->gprs[6]; |
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340 | struct vcpu *v = get_current(); |
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341 | struct domain *d = v->domain; |
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342 | struct domain_htab *htab = &d->arch.htab; |
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343 | union pte volatile *ppte; |
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344 | union pte lpte; |
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345 | |
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346 | DBG_LOW("%s: flags: 0x%lx ptex: 0x%lx avpn: 0x%lx\n", __func__, |
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347 | flags, ptex, avpn); |
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348 | if ( ptex > (1UL << htab->log_num_ptes) ) { |
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349 | DBG("%s: bad ptex: 0x%lx\n", __func__, ptex); |
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350 | regs->gprs[3] = H_Parameter; |
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351 | return; |
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352 | } |
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353 | ppte = &htab->map[ptex]; |
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354 | |
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355 | lpte.words.vsid = ppte->words.vsid; |
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356 | lpte.words.rpn = ppte->words.rpn; |
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357 | |
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358 | /* the AVPN param occupies the bit-space of the word */ |
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359 | if ( (flags & H_AVPN) && lpte.bits.avpn != avpn >> 7 ) { |
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360 | DBG_LOW("%s: %p: AVPN check failed: 0x%lx, 0x%lx\n", __func__, |
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361 | ppte, lpte.words.vsid, lpte.words.rpn); |
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362 | regs->gprs[3] = H_Not_Found; |
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363 | return; |
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364 | } |
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365 | |
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366 | if (lpte.bits.v == 0) { |
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367 | /* the PAPR does not specify what to do here, this is because |
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368 | * we invalidate entires where the PAPR says to 0 the whole hi |
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369 | * dword, so the AVPN should catch this first */ |
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370 | |
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371 | DBG("%s: pte invalid\n", __func__); |
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372 | regs->gprs[3] = H_Not_Found; |
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373 | return; |
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374 | } |
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375 | |
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376 | lpte.bits.v = 0; |
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377 | |
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378 | /* ppte->words.vsid = lpte.words.vsid; */ |
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379 | asm volatile( |
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380 | "eieio; std %1, 0(%0); ptesync" |
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381 | : |
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382 | : "b" (ppte), "r" (0) |
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383 | : "memory"); |
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384 | |
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385 | pte_tlbie(&lpte, ptex); |
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386 | |
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387 | /* We never touch pp0, and PP bits in flags are in the right |
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388 | * order */ |
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389 | lpte.bits.pp1 = flags & (H_PP1 | H_PP2); |
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390 | lpte.bits.n = (flags & H_N) ? 1 : 0; |
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391 | |
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392 | lpte.bits.v = 1; |
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393 | lpte.bits.r = 0; |
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394 | |
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395 | asm volatile( |
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396 | "std %1, 8(%0); eieio; std %2, 0(%0); ptesync" |
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397 | : |
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398 | : "b" (ppte), "r" (lpte.words.rpn), "r" (lpte.words.vsid) |
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399 | : "memory"); |
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400 | |
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401 | regs->gprs[3] = H_Success; |
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402 | } |
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403 | |
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404 | static void h_clear_ref(struct cpu_user_regs *regs) |
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405 | { |
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406 | ulong ptex = regs->gprs[5]; |
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407 | struct vcpu *v = get_current(); |
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408 | struct domain *d = v->domain; |
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409 | struct domain_htab *htab = &d->arch.htab; |
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410 | union pte volatile *pte; |
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411 | union pte lpte; |
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412 | |
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413 | DBG_LOW("%s: flags: 0x%lx ptex: 0x%lx\n", __func__, |
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414 | regs->gprs[4], ptex); |
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415 | |
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416 | #ifdef DEBUG |
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417 | if (regs->gprs[4] != 0) { |
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418 | DBG("WARNING: %s: " |
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419 | "flags are undefined and should be 0: 0x%lx\n", |
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420 | __func__, regs->gprs[4]); |
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421 | } |
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422 | #endif |
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423 | |
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424 | if (ptex > (1UL << htab->log_num_ptes)) { |
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425 | DBG("%s: bad ptex: 0x%lx\n", __func__, ptex); |
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426 | regs->gprs[3] = H_Parameter; |
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427 | return; |
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428 | } |
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429 | pte = &htab->map[ptex]; |
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430 | lpte.words.rpn = pte->words.rpn; |
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431 | |
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432 | regs->gprs[4] = lpte.words.rpn; |
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433 | |
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434 | if (lpte.bits.r != 0) { |
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435 | lpte.bits.r = 0; |
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436 | |
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437 | asm volatile("std %1, 8(%0); eieio; ptesync" |
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438 | : |
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439 | : "b" (pte), "r" (lpte.words.rpn) : "memory"); |
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440 | |
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441 | pte_tlbie(&lpte, ptex); |
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442 | } |
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443 | regs->gprs[3] = H_Success; |
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444 | } |
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445 | |
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446 | static void h_clear_mod(struct cpu_user_regs *regs) |
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447 | { |
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448 | ulong ptex = regs->gprs[5]; |
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449 | struct vcpu *v = get_current(); |
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450 | struct domain *d = v->domain; |
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451 | struct domain_htab *htab = &d->arch.htab; |
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452 | union pte volatile *pte; |
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453 | union pte lpte; |
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454 | |
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455 | DBG_LOW("%s: flags: 0x%lx ptex: 0x%lx\n", __func__, |
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456 | regs->gprs[4], ptex); |
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457 | |
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458 | #ifdef DEBUG |
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459 | if (regs->gprs[4] != 0) { |
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460 | DBG("WARNING: %s: " |
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461 | "flags are undefined and should be 0: 0x%lx\n", |
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462 | __func__, regs->gprs[4]); |
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463 | } |
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464 | #endif |
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465 | |
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466 | if (ptex > (1UL << htab->log_num_ptes)) { |
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467 | DBG("%s: bad ptex: 0x%lx\n", __func__, ptex); |
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468 | regs->gprs[3] = H_Parameter; |
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469 | return; |
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470 | } |
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471 | pte = &htab->map[ptex]; |
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472 | lpte.words.vsid = pte->words.vsid; |
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473 | lpte.words.rpn = pte->words.rpn; |
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474 | |
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475 | regs->gprs[3] = H_Success; |
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476 | regs->gprs[4] = lpte.words.rpn; |
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477 | |
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478 | if (lpte.bits.c != 0) { |
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479 | /* invalidate */ |
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480 | asm volatile( |
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481 | "eieio; std %1, 0(%0); ptesync" |
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482 | : |
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483 | : "b" (pte), "r" (0) |
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484 | : "memory"); |
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485 | |
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486 | pte_tlbie(&lpte, ptex); |
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487 | |
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488 | lpte.bits.c = 0; |
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489 | asm volatile( |
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490 | "std %1, 8(%0); eieio; std %2, 0(%0); ptesync" |
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491 | : |
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492 | : "b" (pte), "r" (lpte.words.rpn), "r" (lpte.words.vsid) |
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493 | : "memory"); |
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494 | } |
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495 | } |
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496 | |
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497 | long pte_remove(ulong flags, ulong ptex, ulong avpn, ulong *hi, ulong *lo) |
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498 | { |
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499 | struct vcpu *v = get_current(); |
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500 | struct domain *d = v->domain; |
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501 | struct domain_htab *htab = &d->arch.htab; |
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502 | union pte volatile *pte; |
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503 | union pte lpte; |
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504 | |
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505 | DBG_LOW("%s: flags: 0x%lx ptex: 0x%lx avpn: 0x%lx\n", __func__, |
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506 | flags, ptex, avpn); |
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507 | |
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508 | if ( ptex > (1UL << htab->log_num_ptes) ) { |
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509 | DBG("%s: bad ptex: 0x%lx\n", __func__, ptex); |
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510 | return H_Parameter; |
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511 | } |
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512 | pte = &htab->map[ptex]; |
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513 | lpte.words.vsid = pte->words.vsid; |
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514 | lpte.words.rpn = pte->words.rpn; |
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515 | |
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516 | if ((flags & H_AVPN) && lpte.bits.avpn != (avpn >> 7)) { |
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517 | DBG_LOW("%s: AVPN does not match\n", __func__); |
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518 | return H_Not_Found; |
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519 | } |
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520 | |
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521 | if ((flags & H_ANDCOND) && ((avpn & pte->words.vsid) != 0)) { |
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522 | DBG("%s: andcond does not match\n", __func__); |
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523 | return H_Not_Found; |
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524 | } |
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525 | |
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526 | /* return old PTE in regs 4 and 5 */ |
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527 | *hi = lpte.words.vsid; |
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528 | *lo = lpte.words.rpn; |
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529 | |
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530 | #ifdef DEBUG_LOW |
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531 | /* XXX - I'm very skeptical of doing ANYTHING if not bits.v */ |
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532 | /* XXX - I think the spec should be questioned in this case (MFM) */ |
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533 | if (lpte.bits.v == 0) { |
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534 | DBG_LOW("%s: removing invalid entry\n", __func__); |
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535 | } |
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536 | #endif |
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537 | |
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538 | if (lpte.bits.v) { |
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539 | ulong mfn = lpte.bits.rpn; |
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540 | if (!platform_io_mfn(mfn)) { |
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541 | struct page_info *pg = mfn_to_page(mfn); |
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542 | struct domain *f = page_get_owner(pg); |
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543 | |
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544 | if (f != d) { |
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545 | put_domain(f); |
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546 | put_page(pg); |
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547 | } |
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548 | } |
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549 | } |
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550 | |
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551 | asm volatile("eieio; std %1, 0(%0); ptesync" |
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552 | : |
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553 | : "b" (pte), "r" (0) |
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554 | : "memory"); |
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555 | |
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556 | pte_tlbie(&lpte, ptex); |
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557 | |
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558 | return H_Success; |
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559 | } |
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560 | |
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561 | static void h_remove(struct cpu_user_regs *regs) |
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562 | { |
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563 | ulong flags = regs->gprs[4]; |
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564 | ulong ptex = regs->gprs[5]; |
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565 | ulong avpn = regs->gprs[6]; |
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566 | ulong hi, lo; |
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567 | long ret; |
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568 | |
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569 | ret = pte_remove(flags, ptex, avpn, &hi, &lo); |
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570 | |
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571 | regs->gprs[3] = ret; |
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572 | |
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573 | if (ret == H_Success) { |
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574 | regs->gprs[4] = hi; |
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575 | regs->gprs[5] = lo; |
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576 | } |
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577 | return; |
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578 | } |
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579 | |
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580 | static void h_read(struct cpu_user_regs *regs) |
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581 | { |
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582 | ulong flags = regs->gprs[4]; |
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583 | ulong ptex = regs->gprs[5]; |
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584 | struct vcpu *v = get_current(); |
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585 | struct domain *d = v->domain; |
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586 | struct domain_htab *htab = &d->arch.htab; |
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587 | union pte volatile *pte; |
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588 | |
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589 | if (flags & H_READ_4) |
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590 | ptex &= ~0x3UL; |
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591 | |
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592 | if (ptex > (1UL << htab->log_num_ptes)) { |
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593 | DBG("%s: bad ptex: 0x%lx\n", __func__, ptex); |
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594 | regs->gprs[3] = H_Parameter; |
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595 | return; |
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596 | } |
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597 | pte = &htab->map[ptex]; |
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598 | regs->gprs[4] = pte[0].words.vsid; |
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599 | regs->gprs[5] = pte[0].words.rpn; |
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600 | |
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601 | if (!(flags & H_READ_4)) { |
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602 | /* dump another 3 PTEs */ |
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603 | regs->gprs[6] = pte[1].words.vsid; |
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604 | regs->gprs[7] = pte[1].words.rpn; |
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605 | regs->gprs[8] = pte[2].words.vsid; |
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606 | regs->gprs[9] = pte[2].words.rpn; |
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607 | regs->gprs[10] = pte[3].words.vsid; |
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608 | regs->gprs[11] = pte[3].words.rpn; |
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609 | } |
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610 | |
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611 | regs->gprs[3] = H_Success; |
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612 | } |
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613 | |
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614 | __init_papr_hcall(H_ENTER, h_enter); |
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615 | __init_papr_hcall(H_READ, h_read); |
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616 | __init_papr_hcall(H_REMOVE, h_remove); |
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617 | __init_papr_hcall(H_CLEAR_MOD, h_clear_mod); |
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618 | __init_papr_hcall(H_CLEAR_REF, h_clear_ref); |
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619 | __init_papr_hcall(H_PROTECT, h_protect); |
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