1 | /* -*- Mode:C; c-basic-offset:4; tab-width:4; indent-tabs-mode:nil -*- */ |
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2 | /* |
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3 | * vmx_minstate.h: |
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4 | * Copyright (c) 2005, Intel Corporation. |
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5 | * |
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6 | * This program is free software; you can redistribute it and/or modify it |
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7 | * under the terms and conditions of the GNU General Public License, |
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8 | * version 2, as published by the Free Software Foundation. |
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9 | * |
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10 | * This program is distributed in the hope it will be useful, but WITHOUT |
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11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
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13 | * more details. |
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14 | * |
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15 | * You should have received a copy of the GNU General Public License along with |
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16 | * this program; if not, write to the Free Software Foundation, Inc., 59 Temple |
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17 | * Place - Suite 330, Boston, MA 02111-1307 USA. |
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18 | * |
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19 | * Xuefei Xu (Anthony Xu) (Anthony.xu@intel.com) |
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20 | */ |
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21 | |
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22 | #include <linux/config.h> |
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23 | |
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24 | #include <asm/asmmacro.h> |
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25 | #include <asm/fpu.h> |
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26 | #include <asm/mmu_context.h> |
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27 | #include <asm/offsets.h> |
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28 | #include <asm/pal.h> |
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29 | #include <asm/pgtable.h> |
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30 | #include <asm/processor.h> |
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31 | #include <asm/ptrace.h> |
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32 | #include <asm/system.h> |
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33 | #include <asm/vmx_pal_vsa.h> |
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34 | #include <asm/vmx_vpd.h> |
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35 | #include <asm/cache.h> |
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36 | #include "entry.h" |
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37 | |
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38 | #define VMX_MINSTATE_START_SAVE_MIN \ |
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39 | mov ar.rsc=0; /* set enforced lazy mode, pl 0, little-endian, loadrs=0 */ \ |
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40 | ;; \ |
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41 | mov.m r28=ar.rnat; \ |
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42 | addl r22=IA64_RBS_OFFSET,r1; /* compute base of RBS */ \ |
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43 | ;; \ |
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44 | lfetch.fault.excl.nt1 [r22]; \ |
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45 | addl r1=IA64_STK_OFFSET-IA64_PT_REGS_SIZE,r1; /* compute base of memory stack */ \ |
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46 | mov r23=ar.bspstore; /* save ar.bspstore */ \ |
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47 | ;; \ |
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48 | mov ar.bspstore=r22; /* switch to kernel RBS */ \ |
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49 | ;; \ |
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50 | mov r18=ar.bsp; \ |
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51 | mov ar.rsc=0x3; /* set eager mode, pl 0, little-endian, loadrs=0 */ \ |
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52 | |
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53 | |
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54 | |
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55 | #define VMX_MINSTATE_END_SAVE_MIN \ |
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56 | bsw.1; /* switch back to bank 1 (must be last in insn group) */ \ |
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57 | ;; |
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58 | |
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59 | |
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60 | #define PAL_VSA_SYNC_READ \ |
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61 | /* begin to call pal vps sync_read */ \ |
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62 | add r25=IA64_VPD_BASE_OFFSET, r21; \ |
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63 | movl r20=__vsa_base; \ |
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64 | ;; \ |
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65 | ld8 r25=[r25]; /* read vpd base */ \ |
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66 | ld8 r20=[r20]; /* read entry point */ \ |
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67 | ;; \ |
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68 | add r20=PAL_VPS_SYNC_READ,r20; \ |
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69 | ;; \ |
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70 | { .mii; \ |
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71 | nop 0x0; \ |
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72 | mov r24=ip; \ |
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73 | mov b0=r20; \ |
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74 | ;; \ |
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75 | }; \ |
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76 | { .mmb; \ |
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77 | add r24 = 0x20, r24; \ |
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78 | nop 0x0; \ |
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79 | br.cond.sptk b0; /* call the service */ \ |
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80 | ;; \ |
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81 | }; \ |
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82 | |
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83 | |
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84 | |
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85 | #define IA64_CURRENT_REG IA64_KR(CURRENT) /* r21 is reserved for current pointer */ |
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86 | //#define VMX_MINSTATE_GET_CURRENT(reg) mov reg=IA64_CURRENT_REG |
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87 | #define VMX_MINSTATE_GET_CURRENT(reg) mov reg=r21 |
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88 | |
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89 | /* |
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90 | * VMX_DO_SAVE_MIN switches to the kernel stacks (if necessary) and saves |
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91 | * the minimum state necessary that allows us to turn psr.ic back |
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92 | * on. |
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93 | * |
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94 | * Assumed state upon entry: |
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95 | * psr.ic: off |
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96 | * r31: contains saved predicates (pr) |
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97 | * |
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98 | * Upon exit, the state is as follows: |
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99 | * psr.ic: off |
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100 | * r2 = points to &pt_regs.r16 |
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101 | * r8 = contents of ar.ccv |
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102 | * r9 = contents of ar.csd |
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103 | * r10 = contents of ar.ssd |
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104 | * r11 = FPSR_DEFAULT |
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105 | * r12 = kernel sp (kernel virtual address) |
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106 | * r13 = points to current task_struct (kernel virtual address) |
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107 | * p15 = TRUE if psr.i is set in cr.ipsr |
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108 | * predicate registers (other than p2, p3, and p15), b6, r3, r14, r15: |
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109 | * preserved |
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110 | * |
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111 | * Note that psr.ic is NOT turned on by this macro. This is so that |
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112 | * we can pass interruption state as arguments to a handler. |
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113 | */ |
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114 | |
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115 | #define VMX_DO_SAVE_MIN(COVER,SAVE_IFS,EXTRA) \ |
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116 | VMX_MINSTATE_GET_CURRENT(r16); /* M (or M;;I) */ \ |
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117 | mov r27=ar.rsc; /* M */ \ |
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118 | mov r20=r1; /* A */ \ |
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119 | mov r25=ar.unat; /* M */ \ |
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120 | mov r29=cr.ipsr; /* M */ \ |
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121 | mov r26=ar.pfs; /* I */ \ |
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122 | mov r18=cr.isr; \ |
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123 | COVER; /* B;; (or nothing) */ \ |
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124 | ;; \ |
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125 | tbit.z p6,p0=r29,IA64_PSR_VM_BIT; \ |
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126 | ;; \ |
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127 | tbit.nz.or p6,p0 = r18,39; \ |
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128 | ;; \ |
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129 | (p6) br.sptk.few vmx_panic; \ |
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130 | tbit.z p0,p15=r29,IA64_PSR_I_BIT; \ |
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131 | mov r1=r16; \ |
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132 | /* mov r21=r16; */ \ |
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133 | /* switch from user to kernel RBS: */ \ |
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134 | ;; \ |
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135 | invala; /* M */ \ |
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136 | SAVE_IFS; \ |
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137 | ;; \ |
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138 | VMX_MINSTATE_START_SAVE_MIN \ |
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139 | adds r17=2*L1_CACHE_BYTES,r1; /* really: biggest cache-line size */ \ |
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140 | adds r16=PT(CR_IPSR),r1; \ |
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141 | ;; \ |
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142 | lfetch.fault.excl.nt1 [r17],L1_CACHE_BYTES; \ |
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143 | st8 [r16]=r29; /* save cr.ipsr */ \ |
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144 | ;; \ |
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145 | lfetch.fault.excl.nt1 [r17]; \ |
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146 | tbit.nz p15,p0=r29,IA64_PSR_I_BIT; \ |
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147 | mov r29=b0 \ |
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148 | ;; \ |
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149 | adds r16=PT(R8),r1; /* initialize first base pointer */ \ |
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150 | adds r17=PT(R9),r1; /* initialize second base pointer */ \ |
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151 | ;; \ |
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152 | .mem.offset 0,0; st8.spill [r16]=r8,16; \ |
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153 | .mem.offset 8,0; st8.spill [r17]=r9,16; \ |
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154 | ;; \ |
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155 | .mem.offset 0,0; st8.spill [r16]=r10,24; \ |
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156 | .mem.offset 8,0; st8.spill [r17]=r11,24; \ |
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157 | ;; \ |
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158 | mov r9=cr.iip; /* M */ \ |
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159 | mov r10=ar.fpsr; /* M */ \ |
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160 | ;; \ |
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161 | st8 [r16]=r9,16; /* save cr.iip */ \ |
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162 | st8 [r17]=r30,16; /* save cr.ifs */ \ |
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163 | sub r18=r18,r22; /* r18=RSE.ndirty*8 */ \ |
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164 | ;; \ |
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165 | st8 [r16]=r25,16; /* save ar.unat */ \ |
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166 | st8 [r17]=r26,16; /* save ar.pfs */ \ |
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167 | shl r18=r18,16; /* compute ar.rsc to be used for "loadrs" */ \ |
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168 | ;; \ |
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169 | st8 [r16]=r27,16; /* save ar.rsc */ \ |
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170 | st8 [r17]=r28,16; /* save ar.rnat */ \ |
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171 | ;; /* avoid RAW on r16 & r17 */ \ |
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172 | st8 [r16]=r23,16; /* save ar.bspstore */ \ |
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173 | st8 [r17]=r31,16; /* save predicates */ \ |
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174 | ;; \ |
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175 | st8 [r16]=r29,16; /* save b0 */ \ |
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176 | st8 [r17]=r18,16; /* save ar.rsc value for "loadrs" */ \ |
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177 | cmp.eq pNonSys,pSys=r0,r0 /* initialize pSys=0, pNonSys=1 */ \ |
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178 | ;; \ |
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179 | .mem.offset 0,0; st8.spill [r16]=r20,16; /* save original r1 */ \ |
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180 | .mem.offset 8,0; st8.spill [r17]=r12,16; \ |
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181 | adds r12=-16,r1; /* switch to kernel memory stack (with 16 bytes of scratch) */ \ |
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182 | ;; \ |
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183 | .mem.offset 0,0; st8.spill [r16]=r13,16; \ |
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184 | .mem.offset 8,0; st8.spill [r17]=r10,16; /* save ar.fpsr */ \ |
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185 | mov r13=r21; /* establish `current' */ \ |
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186 | ;; \ |
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187 | .mem.offset 0,0; st8.spill [r16]=r15,16; \ |
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188 | .mem.offset 8,0; st8.spill [r17]=r14,16; \ |
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189 | ;; \ |
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190 | .mem.offset 0,0; st8.spill [r16]=r2,16; \ |
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191 | .mem.offset 8,0; st8.spill [r17]=r3,16; \ |
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192 | adds r2=IA64_PT_REGS_R16_OFFSET,r1; \ |
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193 | ;; \ |
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194 | adds r16=IA64_VCPU_IIPA_OFFSET,r13; \ |
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195 | adds r17=IA64_VCPU_ISR_OFFSET,r13; \ |
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196 | mov r26=cr.iipa; \ |
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197 | mov r27=cr.isr; \ |
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198 | ;; \ |
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199 | st8 [r16]=r26; \ |
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200 | st8 [r17]=r27; \ |
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201 | ;; \ |
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202 | EXTRA; \ |
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203 | mov r8=ar.ccv; \ |
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204 | mov r9=ar.csd; \ |
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205 | mov r10=ar.ssd; \ |
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206 | movl r11=FPSR_DEFAULT; /* L-unit */ \ |
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207 | movl r1=__gp; /* establish kernel global pointer */ \ |
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208 | ;; \ |
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209 | PAL_VSA_SYNC_READ \ |
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210 | VMX_MINSTATE_END_SAVE_MIN |
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211 | |
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212 | /* |
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213 | * SAVE_REST saves the remainder of pt_regs (with psr.ic on). |
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214 | * |
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215 | * Assumed state upon entry: |
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216 | * psr.ic: on |
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217 | * r2: points to &pt_regs.f6 |
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218 | * r3: points to &pt_regs.f7 |
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219 | * r8: contents of ar.ccv |
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220 | * r9: contents of ar.csd |
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221 | * r10: contents of ar.ssd |
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222 | * r11: FPSR_DEFAULT |
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223 | * |
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224 | * Registers r14 and r15 are guaranteed not to be touched by SAVE_REST. |
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225 | */ |
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226 | #define VMX_SAVE_REST \ |
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227 | .mem.offset 0,0; st8.spill [r2]=r16,16; \ |
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228 | .mem.offset 8,0; st8.spill [r3]=r17,16; \ |
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229 | ;; \ |
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230 | .mem.offset 0,0; st8.spill [r2]=r18,16; \ |
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231 | .mem.offset 8,0; st8.spill [r3]=r19,16; \ |
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232 | ;; \ |
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233 | .mem.offset 0,0; st8.spill [r2]=r20,16; \ |
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234 | .mem.offset 8,0; st8.spill [r3]=r21,16; \ |
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235 | mov r18=b6; \ |
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236 | ;; \ |
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237 | .mem.offset 0,0; st8.spill [r2]=r22,16; \ |
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238 | .mem.offset 8,0; st8.spill [r3]=r23,16; \ |
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239 | mov r19=b7; \ |
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240 | ;; \ |
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241 | .mem.offset 0,0; st8.spill [r2]=r24,16; \ |
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242 | .mem.offset 8,0; st8.spill [r3]=r25,16; \ |
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243 | ;; \ |
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244 | .mem.offset 0,0; st8.spill [r2]=r26,16; \ |
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245 | .mem.offset 8,0; st8.spill [r3]=r27,16; \ |
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246 | ;; \ |
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247 | .mem.offset 0,0; st8.spill [r2]=r28,16; \ |
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248 | .mem.offset 8,0; st8.spill [r3]=r29,16; \ |
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249 | ;; \ |
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250 | .mem.offset 0,0; st8.spill [r2]=r30,16; \ |
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251 | .mem.offset 8,0; st8.spill [r3]=r31,32; \ |
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252 | ;; \ |
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253 | mov ar.fpsr=r11; \ |
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254 | st8 [r2]=r8,8; \ |
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255 | adds r24=PT(B6)-PT(F7),r3; \ |
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256 | ;; \ |
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257 | stf.spill [r2]=f6,32; \ |
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258 | stf.spill [r3]=f7,32; \ |
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259 | ;; \ |
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260 | stf.spill [r2]=f8,32; \ |
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261 | stf.spill [r3]=f9,32; \ |
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262 | ;; \ |
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263 | stf.spill [r2]=f10,32; \ |
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264 | stf.spill [r3]=f11; \ |
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265 | adds r25=PT(B7)-PT(F11),r3; \ |
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266 | ;; \ |
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267 | st8 [r24]=r18,16; /* b6 */ \ |
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268 | st8 [r25]=r19,16; /* b7 */ \ |
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269 | adds r3=PT(R5)-PT(F11),r3; \ |
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270 | ;; \ |
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271 | st8 [r24]=r9; /* ar.csd */ \ |
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272 | st8 [r25]=r10; /* ar.ssd */ \ |
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273 | ;; \ |
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274 | mov r18=ar.unat; \ |
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275 | adds r19=PT(EML_UNAT)-PT(R4),r2; \ |
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276 | ;; \ |
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277 | st8 [r19]=r18; /* eml_unat */ \ |
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278 | |
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279 | |
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280 | #define VMX_SAVE_EXTRA \ |
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281 | .mem.offset 0,0; st8.spill [r2]=r4,16; \ |
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282 | .mem.offset 8,0; st8.spill [r3]=r5,16; \ |
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283 | ;; \ |
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284 | .mem.offset 0,0; st8.spill [r2]=r6,16; \ |
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285 | .mem.offset 8,0; st8.spill [r3]=r7; \ |
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286 | ;; \ |
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287 | mov r26=ar.unat; \ |
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288 | ;; \ |
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289 | st8 [r2]=r26; /* eml_unat */ \ |
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290 | |
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291 | #define VMX_SAVE_MIN_WITH_COVER VMX_DO_SAVE_MIN(cover, mov r30=cr.ifs,) |
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292 | #define VMX_SAVE_MIN_WITH_COVER_R19 VMX_DO_SAVE_MIN(cover, mov r30=cr.ifs, mov r15=r19) |
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293 | #define VMX_SAVE_MIN VMX_DO_SAVE_MIN( , mov r30=r0, ) |
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