1 | /* -*- Mode:C; c-basic-offset:4; tab-width:4; indent-tabs-mode:nil -*- */ |
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2 | /* |
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3 | * vmx_interrupt.c: handle inject interruption. |
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4 | * Copyright (c) 2005, Intel Corporation. |
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5 | * |
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6 | * This program is free software; you can redistribute it and/or modify it |
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7 | * under the terms and conditions of the GNU General Public License, |
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8 | * version 2, as published by the Free Software Foundation. |
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9 | * |
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10 | * This program is distributed in the hope it will be useful, but WITHOUT |
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11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
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13 | * more details. |
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14 | * |
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15 | * You should have received a copy of the GNU General Public License along with |
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16 | * this program; if not, write to the Free Software Foundation, Inc., 59 Temple |
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17 | * Place - Suite 330, Boston, MA 02111-1307 USA. |
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18 | * |
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19 | * Shaofan Li (Susue Li) <susie.li@intel.com> |
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20 | * Xiaoyan Feng (Fleming Feng) <fleming.feng@intel.com> |
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21 | * Xuefei Xu (Anthony Xu) (Anthony.xu@intel.com) |
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22 | */ |
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23 | #include <xen/types.h> |
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24 | #include <asm/vmx_vcpu.h> |
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25 | #include <asm/vmx_mm_def.h> |
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26 | #include <asm/vmx_pal_vsa.h> |
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27 | |
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28 | /* SDM vol2 5.5 - IVA based interruption handling */ |
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29 | #define INITIAL_PSR_VALUE_AT_INTERRUPTION 0x0000001808028034 |
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30 | |
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31 | static void |
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32 | collect_interruption(VCPU *vcpu) |
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33 | { |
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34 | u64 ipsr; |
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35 | u64 vdcr; |
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36 | u64 vifs; |
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37 | IA64_PSR vpsr; |
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38 | REGS * regs = vcpu_regs(vcpu); |
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39 | vpsr.val = vmx_vcpu_get_psr(vcpu); |
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40 | vcpu_bsw0(vcpu); |
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41 | if(vpsr.ic){ |
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42 | |
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43 | /* Sync mpsr id/da/dd/ss/ed bits to vipsr |
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44 | * since after guest do rfi, we still want these bits on in |
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45 | * mpsr |
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46 | */ |
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47 | |
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48 | ipsr = regs->cr_ipsr; |
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49 | vpsr.val = vpsr.val | (ipsr & (IA64_PSR_ID | IA64_PSR_DA |
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50 | | IA64_PSR_DD |IA64_PSR_SS |IA64_PSR_ED)); |
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51 | vcpu_set_ipsr(vcpu, vpsr.val); |
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52 | |
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53 | /* Currently, for trap, we do not advance IIP to next |
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54 | * instruction. That's because we assume caller already |
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55 | * set up IIP correctly |
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56 | */ |
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57 | |
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58 | vcpu_set_iip(vcpu , regs->cr_iip); |
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59 | |
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60 | /* set vifs.v to zero */ |
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61 | vifs = VCPU(vcpu,ifs); |
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62 | vifs &= ~IA64_IFS_V; |
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63 | vcpu_set_ifs(vcpu, vifs); |
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64 | |
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65 | vcpu_set_iipa(vcpu, VMX(vcpu,cr_iipa)); |
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66 | } |
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67 | |
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68 | vdcr = VCPU(vcpu,dcr); |
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69 | |
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70 | /* Set guest psr |
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71 | * up/mfl/mfh/pk/dt/rt/mc/it keeps unchanged |
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72 | * be: set to the value of dcr.be |
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73 | * pp: set to the value of dcr.pp |
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74 | */ |
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75 | vpsr.val &= INITIAL_PSR_VALUE_AT_INTERRUPTION; |
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76 | vpsr.val |= ( vdcr & IA64_DCR_BE); |
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77 | |
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78 | /* VDCR pp bit position is different from VPSR pp bit */ |
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79 | if ( vdcr & IA64_DCR_PP ) { |
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80 | vpsr.val |= IA64_PSR_PP; |
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81 | } else { |
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82 | vpsr.val &= ~IA64_PSR_PP;; |
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83 | } |
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84 | |
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85 | vmx_vcpu_set_psr(vcpu, vpsr.val); |
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86 | |
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87 | } |
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88 | |
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89 | void |
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90 | inject_guest_interruption(VCPU *vcpu, u64 vec) |
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91 | { |
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92 | u64 viva; |
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93 | REGS *regs; |
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94 | ISR pt_isr; |
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95 | |
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96 | perfc_incra(vmx_inject_guest_interruption, vec >> 8); |
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97 | |
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98 | regs = vcpu_regs(vcpu); |
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99 | |
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100 | // clear cr.isr.ir (incomplete register frame) |
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101 | pt_isr.val = VMX(vcpu,cr_isr); |
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102 | pt_isr.ir = 0; |
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103 | VMX(vcpu,cr_isr) = pt_isr.val; |
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104 | |
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105 | collect_interruption(vcpu); |
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106 | vmx_ia64_set_dcr(vcpu); |
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107 | |
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108 | vmx_vcpu_get_iva(vcpu,&viva); |
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109 | regs->cr_iip = viva + vec; |
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110 | } |
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111 | |
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112 | |
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113 | /* |
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114 | * Set vIFA & vITIR & vIHA, when vPSR.ic =1 |
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115 | * Parameter: |
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116 | * set_ifa: if true, set vIFA |
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117 | * set_itir: if true, set vITIR |
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118 | * set_iha: if true, set vIHA |
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119 | */ |
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120 | void |
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121 | set_ifa_itir_iha (VCPU *vcpu, u64 vadr, |
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122 | int set_ifa, int set_itir, int set_iha) |
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123 | { |
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124 | IA64_PSR vpsr; |
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125 | u64 value; |
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126 | vpsr.val = VCPU(vcpu, vpsr); |
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127 | /* Vol2, Table 8-1 */ |
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128 | if ( vpsr.ic ) { |
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129 | if ( set_ifa){ |
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130 | vcpu_set_ifa(vcpu, vadr); |
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131 | } |
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132 | if ( set_itir) { |
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133 | value = vmx_vcpu_get_itir_on_fault(vcpu, vadr); |
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134 | vcpu_set_itir(vcpu, value); |
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135 | } |
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136 | |
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137 | if ( set_iha) { |
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138 | vmx_vcpu_thash(vcpu, vadr, &value); |
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139 | vcpu_set_iha(vcpu, value); |
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140 | } |
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141 | } |
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142 | |
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143 | |
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144 | } |
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145 | |
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146 | /* |
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147 | * Data TLB Fault |
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148 | * @ Data TLB vector |
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149 | * Refer to SDM Vol2 Table 5-6 & 8-1 |
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150 | */ |
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151 | void |
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152 | dtlb_fault (VCPU *vcpu, u64 vadr) |
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153 | { |
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154 | /* If vPSR.ic, IFA, ITIR, IHA */ |
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155 | set_ifa_itir_iha (vcpu, vadr, 1, 1, 1); |
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156 | inject_guest_interruption(vcpu,IA64_DATA_TLB_VECTOR); |
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157 | } |
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158 | |
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159 | /* |
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160 | * Instruction TLB Fault |
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161 | * @ Instruction TLB vector |
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162 | * Refer to SDM Vol2 Table 5-6 & 8-1 |
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163 | */ |
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164 | void |
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165 | itlb_fault (VCPU *vcpu, u64 vadr) |
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166 | { |
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167 | /* If vPSR.ic, IFA, ITIR, IHA */ |
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168 | set_ifa_itir_iha (vcpu, vadr, 1, 1, 1); |
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169 | inject_guest_interruption(vcpu,IA64_INST_TLB_VECTOR); |
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170 | } |
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171 | |
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172 | |
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173 | |
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174 | /* |
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175 | * Data Nested TLB Fault |
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176 | * @ Data Nested TLB Vector |
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177 | * Refer to SDM Vol2 Table 5-6 & 8-1 |
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178 | */ |
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179 | void |
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180 | nested_dtlb (VCPU *vcpu) |
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181 | { |
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182 | inject_guest_interruption(vcpu,IA64_DATA_NESTED_TLB_VECTOR); |
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183 | } |
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184 | |
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185 | /* |
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186 | * Alternate Data TLB Fault |
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187 | * @ Alternate Data TLB vector |
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188 | * Refer to SDM Vol2 Table 5-6 & 8-1 |
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189 | */ |
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190 | void |
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191 | alt_dtlb (VCPU *vcpu, u64 vadr) |
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192 | { |
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193 | set_ifa_itir_iha (vcpu, vadr, 1, 1, 0); |
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194 | inject_guest_interruption(vcpu,IA64_ALT_DATA_TLB_VECTOR); |
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195 | } |
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196 | |
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197 | |
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198 | /* |
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199 | * Data TLB Fault |
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200 | * @ Data TLB vector |
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201 | * Refer to SDM Vol2 Table 5-6 & 8-1 |
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202 | */ |
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203 | void |
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204 | alt_itlb (VCPU *vcpu, u64 vadr) |
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205 | { |
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206 | set_ifa_itir_iha (vcpu, vadr, 1, 1, 0); |
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207 | inject_guest_interruption(vcpu,IA64_ALT_INST_TLB_VECTOR); |
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208 | } |
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209 | |
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210 | /* Deal with: |
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211 | * VHPT Translation Vector |
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212 | */ |
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213 | static void |
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214 | _vhpt_fault(VCPU *vcpu, u64 vadr) |
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215 | { |
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216 | /* If vPSR.ic, IFA, ITIR, IHA*/ |
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217 | set_ifa_itir_iha (vcpu, vadr, 1, 1, 1); |
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218 | inject_guest_interruption(vcpu,IA64_VHPT_TRANS_VECTOR); |
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219 | |
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220 | |
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221 | } |
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222 | |
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223 | /* |
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224 | * VHPT Instruction Fault |
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225 | * @ VHPT Translation vector |
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226 | * Refer to SDM Vol2 Table 5-6 & 8-1 |
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227 | */ |
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228 | void |
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229 | ivhpt_fault (VCPU *vcpu, u64 vadr) |
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230 | { |
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231 | _vhpt_fault(vcpu, vadr); |
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232 | } |
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233 | |
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234 | |
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235 | /* |
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236 | * VHPT Data Fault |
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237 | * @ VHPT Translation vector |
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238 | * Refer to SDM Vol2 Table 5-6 & 8-1 |
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239 | */ |
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240 | void |
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241 | dvhpt_fault (VCPU *vcpu, u64 vadr) |
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242 | { |
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243 | _vhpt_fault(vcpu, vadr); |
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244 | } |
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245 | |
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246 | |
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247 | |
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248 | /* |
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249 | * Deal with: |
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250 | * General Exception vector |
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251 | */ |
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252 | void |
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253 | _general_exception (VCPU *vcpu) |
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254 | { |
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255 | inject_guest_interruption(vcpu,IA64_GENEX_VECTOR); |
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256 | } |
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257 | |
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258 | |
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259 | /* |
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260 | * Illegal Operation Fault |
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261 | * @ General Exception Vector |
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262 | * Refer to SDM Vol2 Table 5-6 & 8-1 |
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263 | */ |
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264 | void |
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265 | illegal_op (VCPU *vcpu) |
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266 | { |
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267 | _general_exception(vcpu); |
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268 | } |
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269 | |
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270 | /* |
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271 | * Illegal Dependency Fault |
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272 | * @ General Exception Vector |
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273 | * Refer to SDM Vol2 Table 5-6 & 8-1 |
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274 | */ |
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275 | void |
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276 | illegal_dep (VCPU *vcpu) |
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277 | { |
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278 | _general_exception(vcpu); |
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279 | } |
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280 | |
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281 | /* |
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282 | * Reserved Register/Field Fault |
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283 | * @ General Exception Vector |
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284 | * Refer to SDM Vol2 Table 5-6 & 8-1 |
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285 | */ |
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286 | void |
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287 | rsv_reg_field (VCPU *vcpu) |
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288 | { |
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289 | _general_exception(vcpu); |
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290 | } |
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291 | /* |
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292 | * Privileged Operation Fault |
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293 | * @ General Exception Vector |
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294 | * Refer to SDM Vol2 Table 5-6 & 8-1 |
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295 | */ |
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296 | |
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297 | void |
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298 | privilege_op (VCPU *vcpu) |
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299 | { |
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300 | _general_exception(vcpu); |
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301 | } |
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302 | |
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303 | /* |
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304 | * Unimplement Data Address Fault |
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305 | * @ General Exception Vector |
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306 | * Refer to SDM Vol2 Table 5-6 & 8-1 |
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307 | */ |
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308 | void |
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309 | unimpl_daddr (VCPU *vcpu) |
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310 | { |
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311 | _general_exception(vcpu); |
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312 | } |
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313 | |
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314 | /* |
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315 | * Privileged Register Fault |
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316 | * @ General Exception Vector |
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317 | * Refer to SDM Vol2 Table 5-6 & 8-1 |
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318 | */ |
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319 | void |
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320 | privilege_reg (VCPU *vcpu) |
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321 | { |
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322 | _general_exception(vcpu); |
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323 | } |
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324 | |
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325 | /* Deal with |
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326 | * Nat consumption vector |
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327 | * Parameter: |
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328 | * vaddr: Optional, if t == REGISTER |
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329 | */ |
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330 | static void |
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331 | _nat_consumption_fault(VCPU *vcpu, u64 vadr, miss_type t) |
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332 | { |
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333 | /* If vPSR.ic && t == DATA/INST, IFA */ |
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334 | if ( t == DATA || t == INSTRUCTION ) { |
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335 | /* IFA */ |
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336 | set_ifa_itir_iha (vcpu, vadr, 1, 0, 0); |
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337 | } |
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338 | |
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339 | inject_guest_interruption(vcpu,IA64_NAT_CONSUMPTION_VECTOR); |
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340 | } |
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341 | |
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342 | /* |
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343 | * IR Data Nat Page Consumption Fault |
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344 | * @ Nat Consumption Vector |
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345 | * Refer to SDM Vol2 Table 5-6 & 8-1 |
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346 | */ |
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347 | #if 0 |
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348 | static void |
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349 | ir_nat_page_consumption (VCPU *vcpu, u64 vadr) |
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350 | { |
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351 | _nat_consumption_fault(vcpu, vadr, DATA); |
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352 | } |
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353 | #endif //shadow it due to no use currently |
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354 | |
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355 | /* |
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356 | * Instruction Nat Page Consumption Fault |
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357 | * @ Nat Consumption Vector |
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358 | * Refer to SDM Vol2 Table 5-6 & 8-1 |
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359 | */ |
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360 | void |
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361 | inat_page_consumption (VCPU *vcpu, u64 vadr) |
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362 | { |
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363 | _nat_consumption_fault(vcpu, vadr, INSTRUCTION); |
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364 | } |
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365 | |
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366 | /* |
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367 | * Register Nat Consumption Fault |
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368 | * @ Nat Consumption Vector |
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369 | * Refer to SDM Vol2 Table 5-6 & 8-1 |
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370 | */ |
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371 | void |
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372 | rnat_consumption (VCPU *vcpu) |
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373 | { |
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374 | _nat_consumption_fault(vcpu, 0, REGISTER); |
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375 | } |
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376 | |
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377 | /* |
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378 | * Data Nat Page Consumption Fault |
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379 | * @ Nat Consumption Vector |
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380 | * Refer to SDM Vol2 Table 5-6 & 8-1 |
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381 | */ |
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382 | void |
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383 | dnat_page_consumption (VCPU *vcpu, uint64_t vadr) |
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384 | { |
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385 | _nat_consumption_fault(vcpu, vadr, DATA); |
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386 | } |
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387 | |
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388 | /* Deal with |
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389 | * Page not present vector |
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390 | */ |
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391 | static void |
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392 | __page_not_present(VCPU *vcpu, u64 vadr) |
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393 | { |
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394 | /* If vPSR.ic, IFA, ITIR */ |
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395 | set_ifa_itir_iha (vcpu, vadr, 1, 1, 0); |
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396 | inject_guest_interruption(vcpu, IA64_PAGE_NOT_PRESENT_VECTOR); |
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397 | } |
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398 | |
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399 | |
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400 | void |
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401 | data_page_not_present(VCPU *vcpu, u64 vadr) |
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402 | { |
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403 | __page_not_present(vcpu, vadr); |
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404 | } |
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405 | |
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406 | |
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407 | void |
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408 | inst_page_not_present(VCPU *vcpu, u64 vadr) |
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409 | { |
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410 | __page_not_present(vcpu, vadr); |
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411 | } |
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412 | |
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413 | |
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414 | /* Deal with |
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415 | * Data access rights vector |
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416 | */ |
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417 | void |
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418 | data_access_rights(VCPU *vcpu, u64 vadr) |
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419 | { |
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420 | /* If vPSR.ic, IFA, ITIR */ |
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421 | set_ifa_itir_iha (vcpu, vadr, 1, 1, 0); |
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422 | inject_guest_interruption(vcpu, IA64_DATA_ACCESS_RIGHTS_VECTOR); |
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423 | } |
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424 | |
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