| 1 | /* |
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| 2 | * This file is subject to the terms and conditions of the GNU General Public |
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| 3 | * License. See the file "COPYING" in the main directory of this archive |
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| 4 | * for more details. |
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| 5 | * |
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| 6 | * Copyright (C) 2000-2005 Silicon Graphics, Inc. All rights reserved. |
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| 7 | */ |
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| 8 | |
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| 9 | #include <asm/types.h> |
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| 10 | #include <asm/sn/shub_mmr.h> |
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| 11 | |
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| 12 | #define DEADLOCKBIT SH_PIO_WRITE_STATUS_WRITE_DEADLOCK_SHFT |
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| 13 | #define WRITECOUNTMASK SH_PIO_WRITE_STATUS_PENDING_WRITE_COUNT_MASK |
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| 14 | #define ALIAS_OFFSET 8 |
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| 15 | |
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| 16 | |
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| 17 | .global sn2_ptc_deadlock_recovery_core |
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| 18 | .proc sn2_ptc_deadlock_recovery_core |
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| 19 | |
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| 20 | sn2_ptc_deadlock_recovery_core: |
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| 21 | .regstk 6,0,0,0 |
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| 22 | |
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| 23 | ptc0 = in0 |
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| 24 | data0 = in1 |
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| 25 | ptc1 = in2 |
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| 26 | data1 = in3 |
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| 27 | piowc = in4 |
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| 28 | zeroval = in5 |
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| 29 | piowcphy = r30 |
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| 30 | psrsave = r2 |
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| 31 | scr1 = r16 |
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| 32 | scr2 = r17 |
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| 33 | mask = r18 |
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| 34 | |
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| 35 | |
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| 36 | extr.u piowcphy=piowc,0,61;; // Convert piowc to uncached physical address |
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| 37 | dep piowcphy=-1,piowcphy,63,1 |
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| 38 | movl mask=WRITECOUNTMASK |
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| 39 | mov r8=r0 |
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| 40 | |
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| 41 | 1: |
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| 42 | cmp.ne p8,p9=r0,ptc1 // Test for shub type (ptc1 non-null on shub1) |
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| 43 | // p8 = 1 if shub1, p9 = 1 if shub2 |
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| 44 | |
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| 45 | add scr2=ALIAS_OFFSET,piowc // Address of WRITE_STATUS alias register |
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| 46 | mov scr1=7;; // Clear DEADLOCK, WRITE_ERROR, MULTI_WRITE_ERROR |
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| 47 | (p8) st8.rel [scr2]=scr1;; |
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| 48 | (p9) ld8.acq scr1=[scr2];; |
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| 49 | |
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| 50 | 5: ld8.acq scr1=[piowc];; // Wait for PIOs to complete. |
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| 51 | hint @pause |
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| 52 | and scr2=scr1,mask;; // mask of writecount bits |
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| 53 | cmp.ne p6,p0=zeroval,scr2 |
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| 54 | (p6) br.cond.sptk 5b |
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| 55 | |
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| 56 | |
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| 57 | |
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| 58 | ////////////// BEGIN PHYSICAL MODE //////////////////// |
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| 59 | mov psrsave=psr // Disable IC (no PMIs) |
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| 60 | rsm psr.i | psr.dt | psr.ic;; |
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| 61 | srlz.i;; |
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| 62 | |
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| 63 | st8.rel [ptc0]=data0 // Write PTC0 & wait for completion. |
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| 64 | |
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| 65 | 5: ld8.acq scr1=[piowcphy];; // Wait for PIOs to complete. |
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| 66 | hint @pause |
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| 67 | and scr2=scr1,mask;; // mask of writecount bits |
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| 68 | cmp.ne p6,p0=zeroval,scr2 |
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| 69 | (p6) br.cond.sptk 5b;; |
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| 70 | |
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| 71 | tbit.nz p8,p7=scr1,DEADLOCKBIT;;// Test for DEADLOCK |
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| 72 | (p7) cmp.ne p7,p0=r0,ptc1;; // Test for non-null ptc1 |
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| 73 | |
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| 74 | (p7) st8.rel [ptc1]=data1;; // Now write PTC1. |
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| 75 | |
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| 76 | 5: ld8.acq scr1=[piowcphy];; // Wait for PIOs to complete. |
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| 77 | hint @pause |
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| 78 | and scr2=scr1,mask;; // mask of writecount bits |
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| 79 | cmp.ne p6,p0=zeroval,scr2 |
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| 80 | (p6) br.cond.sptk 5b |
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| 81 | |
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| 82 | tbit.nz p8,p0=scr1,DEADLOCKBIT;;// Test for DEADLOCK |
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| 83 | |
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| 84 | mov psr.l=psrsave;; // Reenable IC |
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| 85 | srlz.i;; |
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| 86 | ////////////// END PHYSICAL MODE //////////////////// |
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| 87 | |
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| 88 | (p8) add r8=1,r8 |
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| 89 | (p8) br.cond.spnt 1b;; // Repeat if DEADLOCK occurred. |
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| 90 | |
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| 91 | br.ret.sptk rp |
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| 92 | .endp sn2_ptc_deadlock_recovery_core |
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