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1 | /* |
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2 | * This file is subject to the terms and conditions of the GNU General Public |
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3 | * License. See the file "COPYING" in the main directory of this archive |
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4 | * for more details. |
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5 | * |
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6 | * Copyright (C) 2000-2005 Silicon Graphics, Inc. All rights reserved. |
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7 | * |
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8 | * This file contains macros used to access MMR registers via |
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9 | * uncached physical addresses. |
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10 | * pio_phys_read_mmr - read an MMR |
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11 | * pio_phys_write_mmr - write an MMR |
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12 | * pio_atomic_phys_write_mmrs - atomically write 1 or 2 MMRs with psr.ic=0 |
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13 | * Second MMR will be skipped if address is NULL |
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14 | * |
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15 | * Addresses passed to these routines should be uncached physical addresses |
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16 | * ie., 0x80000.... |
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17 | */ |
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18 | |
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19 | |
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20 | |
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21 | #include <asm/asmmacro.h> |
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22 | #include <asm/page.h> |
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23 | |
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24 | GLOBAL_ENTRY(pio_phys_read_mmr) |
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25 | .prologue |
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26 | .regstk 1,0,0,0 |
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27 | .body |
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28 | mov r2=psr |
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29 | rsm psr.i | psr.dt |
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30 | ;; |
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31 | srlz.d |
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32 | ld8.acq r8=[r32] |
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33 | ;; |
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34 | mov psr.l=r2;; |
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35 | srlz.d |
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36 | br.ret.sptk.many rp |
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37 | END(pio_phys_read_mmr) |
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38 | |
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39 | GLOBAL_ENTRY(pio_phys_write_mmr) |
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40 | .prologue |
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41 | .regstk 2,0,0,0 |
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42 | .body |
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43 | mov r2=psr |
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44 | rsm psr.i | psr.dt |
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45 | ;; |
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46 | srlz.d |
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47 | st8.rel [r32]=r33 |
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48 | ;; |
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49 | mov psr.l=r2;; |
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50 | srlz.d |
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51 | br.ret.sptk.many rp |
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52 | END(pio_phys_write_mmr) |
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53 | |
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54 | GLOBAL_ENTRY(pio_atomic_phys_write_mmrs) |
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55 | .prologue |
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56 | .regstk 4,0,0,0 |
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57 | .body |
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58 | mov r2=psr |
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59 | cmp.ne p9,p0=r34,r0; |
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60 | rsm psr.i | psr.dt | psr.ic |
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61 | ;; |
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62 | srlz.d |
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63 | st8.rel [r32]=r33 |
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64 | (p9) st8.rel [r34]=r35 |
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65 | ;; |
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66 | mov psr.l=r2;; |
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67 | srlz.d |
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68 | br.ret.sptk.many rp |
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69 | END(pio_atomic_phys_write_mmrs) |
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70 | |
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71 | |
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