[34] | 1 | /* |
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| 2 | * TLB support routines. |
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| 3 | * |
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| 4 | * Copyright (C) 1998-2001, 2003 Hewlett-Packard Co |
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| 5 | * David Mosberger-Tang <davidm@hpl.hp.com> |
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| 6 | * |
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| 7 | * 08/02/00 A. Mallick <asit.k.mallick@intel.com> |
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| 8 | * Modified RID allocation for SMP |
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| 9 | * Goutham Rao <goutham.rao@intel.com> |
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| 10 | * IPI based ptc implementation and A-step IPI implementation. |
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| 11 | */ |
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| 12 | #include <linux/config.h> |
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| 13 | #include <linux/module.h> |
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| 14 | #include <linux/init.h> |
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| 15 | #include <linux/kernel.h> |
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| 16 | #include <linux/sched.h> |
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| 17 | #include <linux/smp.h> |
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| 18 | #include <linux/mm.h> |
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| 19 | |
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| 20 | #include <asm/delay.h> |
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| 21 | #include <asm/mmu_context.h> |
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| 22 | #include <asm/pgalloc.h> |
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| 23 | #include <asm/pal.h> |
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| 24 | #include <asm/tlbflush.h> |
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| 25 | |
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| 26 | static struct { |
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| 27 | unsigned long mask; /* mask of supported purge page-sizes */ |
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| 28 | unsigned long max_bits; /* log2() of largest supported purge page-size */ |
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| 29 | } purge; |
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| 30 | |
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| 31 | #ifndef XEN |
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| 32 | struct ia64_ctx ia64_ctx = { |
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| 33 | .lock = SPIN_LOCK_UNLOCKED, |
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| 34 | .next = 1, |
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| 35 | .limit = (1 << 15) - 1, /* start out with the safe (architected) limit */ |
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| 36 | .max_ctx = ~0U |
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| 37 | }; |
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| 38 | |
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| 39 | DEFINE_PER_CPU(u8, ia64_need_tlb_flush); |
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| 40 | |
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| 41 | /* |
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| 42 | * Acquire the ia64_ctx.lock before calling this function! |
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| 43 | */ |
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| 44 | void |
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| 45 | wrap_mmu_context (struct mm_struct *mm) |
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| 46 | { |
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| 47 | unsigned long tsk_context, max_ctx = ia64_ctx.max_ctx; |
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| 48 | struct task_struct *tsk; |
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| 49 | int i; |
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| 50 | |
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| 51 | if (ia64_ctx.next > max_ctx) |
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| 52 | ia64_ctx.next = 300; /* skip daemons */ |
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| 53 | ia64_ctx.limit = max_ctx + 1; |
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| 54 | |
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| 55 | /* |
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| 56 | * Scan all the task's mm->context and set proper safe range |
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| 57 | */ |
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| 58 | |
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| 59 | read_lock(&tasklist_lock); |
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| 60 | repeat: |
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| 61 | for_each_process(tsk) { |
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| 62 | if (!tsk->mm) |
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| 63 | continue; |
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| 64 | tsk_context = tsk->mm->context; |
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| 65 | if (tsk_context == ia64_ctx.next) { |
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| 66 | if (++ia64_ctx.next >= ia64_ctx.limit) { |
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| 67 | /* empty range: reset the range limit and start over */ |
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| 68 | if (ia64_ctx.next > max_ctx) |
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| 69 | ia64_ctx.next = 300; |
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| 70 | ia64_ctx.limit = max_ctx + 1; |
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| 71 | goto repeat; |
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| 72 | } |
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| 73 | } |
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| 74 | if ((tsk_context > ia64_ctx.next) && (tsk_context < ia64_ctx.limit)) |
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| 75 | ia64_ctx.limit = tsk_context; |
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| 76 | } |
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| 77 | read_unlock(&tasklist_lock); |
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| 78 | /* can't call flush_tlb_all() here because of race condition with O(1) scheduler [EF] */ |
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| 79 | { |
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| 80 | int cpu = get_cpu(); /* prevent preemption/migration */ |
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| 81 | for (i = 0; i < NR_CPUS; ++i) |
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| 82 | if (cpu_online(i) && (i != cpu)) |
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| 83 | per_cpu(ia64_need_tlb_flush, i) = 1; |
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| 84 | put_cpu(); |
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| 85 | } |
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| 86 | local_flush_tlb_all(); |
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| 87 | } |
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| 88 | #endif /* XEN */ |
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| 89 | |
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| 90 | void |
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| 91 | ia64_global_tlb_purge (unsigned long start, unsigned long end, unsigned long nbits) |
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| 92 | { |
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| 93 | static DEFINE_SPINLOCK(ptcg_lock); |
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| 94 | |
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| 95 | /* HW requires global serialization of ptc.ga. */ |
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| 96 | spin_lock(&ptcg_lock); |
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| 97 | { |
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| 98 | do { |
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| 99 | /* |
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| 100 | * Flush ALAT entries also. |
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| 101 | */ |
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| 102 | ia64_ptcga(start, (nbits<<2)); |
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| 103 | ia64_srlz_i(); |
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| 104 | start += (1UL << nbits); |
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| 105 | } while (start < end); |
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| 106 | } |
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| 107 | spin_unlock(&ptcg_lock); |
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| 108 | } |
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| 109 | |
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| 110 | void |
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| 111 | local_flush_tlb_all (void) |
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| 112 | { |
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| 113 | unsigned long i, j, flags, count0, count1, stride0, stride1, addr; |
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| 114 | #ifdef XEN |
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| 115 | /* increment flush clock before mTLB flush */ |
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| 116 | u32 flush_time = tlbflush_clock_inc_and_return(); |
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| 117 | #endif |
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| 118 | addr = local_cpu_data->ptce_base; |
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| 119 | count0 = local_cpu_data->ptce_count[0]; |
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| 120 | count1 = local_cpu_data->ptce_count[1]; |
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| 121 | stride0 = local_cpu_data->ptce_stride[0]; |
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| 122 | stride1 = local_cpu_data->ptce_stride[1]; |
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| 123 | |
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| 124 | local_irq_save(flags); |
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| 125 | for (i = 0; i < count0; ++i) { |
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| 126 | for (j = 0; j < count1; ++j) { |
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| 127 | ia64_ptce(addr); |
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| 128 | addr += stride1; |
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| 129 | } |
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| 130 | addr += stride0; |
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| 131 | } |
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| 132 | local_irq_restore(flags); |
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| 133 | ia64_srlz_i(); /* srlz.i implies srlz.d */ |
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| 134 | #ifdef XEN |
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| 135 | /* update after mTLB flush. */ |
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| 136 | tlbflush_update_time(&__get_cpu_var(tlbflush_time), flush_time); |
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| 137 | #endif |
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| 138 | } |
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| 139 | EXPORT_SYMBOL(local_flush_tlb_all); |
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| 140 | |
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| 141 | #ifndef XEN |
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| 142 | void |
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| 143 | flush_tlb_range (struct vm_area_struct *vma, unsigned long start, unsigned long end) |
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| 144 | { |
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| 145 | struct mm_struct *mm = vma->vm_mm; |
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| 146 | unsigned long size = end - start; |
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| 147 | unsigned long nbits; |
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| 148 | |
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| 149 | if (mm != current->active_mm) { |
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| 150 | /* this does happen, but perhaps it's not worth optimizing for? */ |
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| 151 | #ifdef CONFIG_SMP |
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| 152 | flush_tlb_all(); |
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| 153 | #else |
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| 154 | mm->context = 0; |
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| 155 | #endif |
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| 156 | return; |
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| 157 | } |
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| 158 | |
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| 159 | nbits = ia64_fls(size + 0xfff); |
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| 160 | while (unlikely (((1UL << nbits) & purge.mask) == 0) && (nbits < purge.max_bits)) |
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| 161 | ++nbits; |
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| 162 | if (nbits > purge.max_bits) |
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| 163 | nbits = purge.max_bits; |
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| 164 | start &= ~((1UL << nbits) - 1); |
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| 165 | |
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| 166 | # ifdef CONFIG_SMP |
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| 167 | platform_global_tlb_purge(start, end, nbits); |
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| 168 | # else |
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| 169 | do { |
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| 170 | ia64_ptcl(start, (nbits<<2)); |
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| 171 | start += (1UL << nbits); |
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| 172 | } while (start < end); |
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| 173 | # endif |
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| 174 | |
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| 175 | ia64_srlz_i(); /* srlz.i implies srlz.d */ |
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| 176 | } |
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| 177 | EXPORT_SYMBOL(flush_tlb_range); |
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| 178 | #endif |
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| 179 | |
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| 180 | void __devinit |
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| 181 | ia64_tlb_init (void) |
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| 182 | { |
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| 183 | #ifndef XEN |
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| 184 | ia64_ptce_info_t ptce_info; |
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| 185 | #else |
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| 186 | ia64_ptce_info_t ptce_info = { 0 }; |
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| 187 | #endif |
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| 188 | unsigned long tr_pgbits; |
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| 189 | long status; |
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| 190 | |
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| 191 | if ((status = ia64_pal_vm_page_size(&tr_pgbits, &purge.mask)) != 0) { |
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| 192 | printk(KERN_ERR "PAL_VM_PAGE_SIZE failed with status=%ld;" |
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| 193 | "defaulting to architected purge page-sizes.\n", status); |
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| 194 | purge.mask = 0x115557000UL; |
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| 195 | } |
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| 196 | purge.max_bits = ia64_fls(purge.mask); |
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| 197 | |
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| 198 | ia64_get_ptce(&ptce_info); |
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| 199 | local_cpu_data->ptce_base = ptce_info.base; |
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| 200 | local_cpu_data->ptce_count[0] = ptce_info.count[0]; |
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| 201 | local_cpu_data->ptce_count[1] = ptce_info.count[1]; |
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| 202 | local_cpu_data->ptce_stride[0] = ptce_info.stride[0]; |
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| 203 | local_cpu_data->ptce_stride[1] = ptce_info.stride[1]; |
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| 204 | |
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| 205 | local_flush_tlb_all(); /* nuke left overs from bootstrapping... */ |
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| 206 | } |
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