1 | /* |
---|
2 | * This file contains the Montecito PMU register description tables |
---|
3 | * and pmc checker used by perfmon.c. |
---|
4 | * |
---|
5 | * Copyright (c) 2005-2006 Hewlett-Packard Development Company, L.P. |
---|
6 | * Contributed by Stephane Eranian <eranian@hpl.hp.com> |
---|
7 | */ |
---|
8 | static int pfm_mont_pmc_check(struct task_struct *task, pfm_context_t *ctx, unsigned int cnum, unsigned long *val, struct pt_regs *regs); |
---|
9 | |
---|
10 | #define RDEP_MONT_ETB (RDEP(38)|RDEP(39)|RDEP(48)|RDEP(49)|RDEP(50)|RDEP(51)|RDEP(52)|RDEP(53)|RDEP(54)|\ |
---|
11 | RDEP(55)|RDEP(56)|RDEP(57)|RDEP(58)|RDEP(59)|RDEP(60)|RDEP(61)|RDEP(62)|RDEP(63)) |
---|
12 | #define RDEP_MONT_DEAR (RDEP(32)|RDEP(33)|RDEP(36)) |
---|
13 | #define RDEP_MONT_IEAR (RDEP(34)|RDEP(35)) |
---|
14 | |
---|
15 | static pfm_reg_desc_t pfm_mont_pmc_desc[PMU_MAX_PMCS]={ |
---|
16 | /* pmc0 */ { PFM_REG_CONTROL , 0, 0x0, -1, NULL, NULL, {0,0, 0, 0}, {0,0, 0, 0}}, |
---|
17 | /* pmc1 */ { PFM_REG_CONTROL , 0, 0x0, -1, NULL, NULL, {0,0, 0, 0}, {0,0, 0, 0}}, |
---|
18 | /* pmc2 */ { PFM_REG_CONTROL , 0, 0x0, -1, NULL, NULL, {0,0, 0, 0}, {0,0, 0, 0}}, |
---|
19 | /* pmc3 */ { PFM_REG_CONTROL , 0, 0x0, -1, NULL, NULL, {0,0, 0, 0}, {0,0, 0, 0}}, |
---|
20 | /* pmc4 */ { PFM_REG_COUNTING, 6, 0x2000000, 0x7c7fff7f, NULL, pfm_mont_pmc_check, {RDEP(4),0, 0, 0}, {0,0, 0, 0}}, |
---|
21 | /* pmc5 */ { PFM_REG_COUNTING, 6, 0x2000000, 0x7c7fff7f, NULL, pfm_mont_pmc_check, {RDEP(5),0, 0, 0}, {0,0, 0, 0}}, |
---|
22 | /* pmc6 */ { PFM_REG_COUNTING, 6, 0x2000000, 0x7c7fff7f, NULL, pfm_mont_pmc_check, {RDEP(6),0, 0, 0}, {0,0, 0, 0}}, |
---|
23 | /* pmc7 */ { PFM_REG_COUNTING, 6, 0x2000000, 0x7c7fff7f, NULL, pfm_mont_pmc_check, {RDEP(7),0, 0, 0}, {0,0, 0, 0}}, |
---|
24 | /* pmc8 */ { PFM_REG_COUNTING, 6, 0x2000000, 0x7c7fff7f, NULL, pfm_mont_pmc_check, {RDEP(8),0, 0, 0}, {0,0, 0, 0}}, |
---|
25 | /* pmc9 */ { PFM_REG_COUNTING, 6, 0x2000000, 0x7c7fff7f, NULL, pfm_mont_pmc_check, {RDEP(9),0, 0, 0}, {0,0, 0, 0}}, |
---|
26 | /* pmc10 */ { PFM_REG_COUNTING, 6, 0x2000000, 0x7c7fff7f, NULL, pfm_mont_pmc_check, {RDEP(10),0, 0, 0}, {0,0, 0, 0}}, |
---|
27 | /* pmc11 */ { PFM_REG_COUNTING, 6, 0x2000000, 0x7c7fff7f, NULL, pfm_mont_pmc_check, {RDEP(11),0, 0, 0}, {0,0, 0, 0}}, |
---|
28 | /* pmc12 */ { PFM_REG_COUNTING, 6, 0x2000000, 0x7c7fff7f, NULL, pfm_mont_pmc_check, {RDEP(12),0, 0, 0}, {0,0, 0, 0}}, |
---|
29 | /* pmc13 */ { PFM_REG_COUNTING, 6, 0x2000000, 0x7c7fff7f, NULL, pfm_mont_pmc_check, {RDEP(13),0, 0, 0}, {0,0, 0, 0}}, |
---|
30 | /* pmc14 */ { PFM_REG_COUNTING, 6, 0x2000000, 0x7c7fff7f, NULL, pfm_mont_pmc_check, {RDEP(14),0, 0, 0}, {0,0, 0, 0}}, |
---|
31 | /* pmc15 */ { PFM_REG_COUNTING, 6, 0x2000000, 0x7c7fff7f, NULL, pfm_mont_pmc_check, {RDEP(15),0, 0, 0}, {0,0, 0, 0}}, |
---|
32 | /* pmc16 */ { PFM_REG_NOTIMPL, }, |
---|
33 | /* pmc17 */ { PFM_REG_NOTIMPL, }, |
---|
34 | /* pmc18 */ { PFM_REG_NOTIMPL, }, |
---|
35 | /* pmc19 */ { PFM_REG_NOTIMPL, }, |
---|
36 | /* pmc20 */ { PFM_REG_NOTIMPL, }, |
---|
37 | /* pmc21 */ { PFM_REG_NOTIMPL, }, |
---|
38 | /* pmc22 */ { PFM_REG_NOTIMPL, }, |
---|
39 | /* pmc23 */ { PFM_REG_NOTIMPL, }, |
---|
40 | /* pmc24 */ { PFM_REG_NOTIMPL, }, |
---|
41 | /* pmc25 */ { PFM_REG_NOTIMPL, }, |
---|
42 | /* pmc26 */ { PFM_REG_NOTIMPL, }, |
---|
43 | /* pmc27 */ { PFM_REG_NOTIMPL, }, |
---|
44 | /* pmc28 */ { PFM_REG_NOTIMPL, }, |
---|
45 | /* pmc29 */ { PFM_REG_NOTIMPL, }, |
---|
46 | /* pmc30 */ { PFM_REG_NOTIMPL, }, |
---|
47 | /* pmc31 */ { PFM_REG_NOTIMPL, }, |
---|
48 | /* pmc32 */ { PFM_REG_CONFIG, 0, 0x30f01ffffffffff, 0x30f01ffffffffff, NULL, pfm_mont_pmc_check, {0,0, 0, 0}, {0,0, 0, 0}}, |
---|
49 | /* pmc33 */ { PFM_REG_CONFIG, 0, 0x0, 0x1ffffffffff, NULL, pfm_mont_pmc_check, {0,0, 0, 0}, {0,0, 0, 0}}, |
---|
50 | /* pmc34 */ { PFM_REG_CONFIG, 0, 0xf01ffffffffff, 0xf01ffffffffff, NULL, pfm_mont_pmc_check, {0,0, 0, 0}, {0,0, 0, 0}}, |
---|
51 | /* pmc35 */ { PFM_REG_CONFIG, 0, 0x0, 0x1ffffffffff, NULL, pfm_mont_pmc_check, {0,0, 0, 0}, {0,0, 0, 0}}, |
---|
52 | /* pmc36 */ { PFM_REG_CONFIG, 0, 0xfffffff0, 0xf, NULL, pfm_mont_pmc_check, {0,0, 0, 0}, {0,0, 0, 0}}, |
---|
53 | /* pmc37 */ { PFM_REG_MONITOR, 4, 0x0, 0x3fff, NULL, pfm_mont_pmc_check, {RDEP_MONT_IEAR, 0, 0, 0}, {0, 0, 0, 0}}, |
---|
54 | /* pmc38 */ { PFM_REG_CONFIG, 0, 0xdb6, 0x2492, NULL, pfm_mont_pmc_check, {0,0, 0, 0}, {0,0, 0, 0}}, |
---|
55 | /* pmc39 */ { PFM_REG_MONITOR, 6, 0x0, 0xffcf, NULL, pfm_mont_pmc_check, {RDEP_MONT_ETB,0, 0, 0}, {0,0, 0, 0}}, |
---|
56 | /* pmc40 */ { PFM_REG_MONITOR, 6, 0x2000000, 0xf01cf, NULL, pfm_mont_pmc_check, {RDEP_MONT_DEAR,0, 0, 0}, {0,0, 0, 0}}, |
---|
57 | /* pmc41 */ { PFM_REG_CONFIG, 0, 0x00002078fefefefe, 0x1e00018181818, NULL, pfm_mont_pmc_check, {0,0, 0, 0}, {0,0, 0, 0}}, |
---|
58 | /* pmc42 */ { PFM_REG_MONITOR, 6, 0x0, 0x7ff4f, NULL, pfm_mont_pmc_check, {RDEP_MONT_ETB,0, 0, 0}, {0,0, 0, 0}}, |
---|
59 | { PFM_REG_END , 0, 0x0, -1, NULL, NULL, {0,}, {0,}}, /* end marker */ |
---|
60 | }; |
---|
61 | |
---|
62 | static pfm_reg_desc_t pfm_mont_pmd_desc[PMU_MAX_PMDS]={ |
---|
63 | /* pmd0 */ { PFM_REG_NOTIMPL, }, |
---|
64 | /* pmd1 */ { PFM_REG_NOTIMPL, }, |
---|
65 | /* pmd2 */ { PFM_REG_NOTIMPL, }, |
---|
66 | /* pmd3 */ { PFM_REG_NOTIMPL, }, |
---|
67 | /* pmd4 */ { PFM_REG_COUNTING, 0, 0x0, -1, NULL, NULL, {0,0, 0, 0}, {RDEP(4),0, 0, 0}}, |
---|
68 | /* pmd5 */ { PFM_REG_COUNTING, 0, 0x0, -1, NULL, NULL, {0,0, 0, 0}, {RDEP(5),0, 0, 0}}, |
---|
69 | /* pmd6 */ { PFM_REG_COUNTING, 0, 0x0, -1, NULL, NULL, {0,0, 0, 0}, {RDEP(6),0, 0, 0}}, |
---|
70 | /* pmd7 */ { PFM_REG_COUNTING, 0, 0x0, -1, NULL, NULL, {0,0, 0, 0}, {RDEP(7),0, 0, 0}}, |
---|
71 | /* pmd8 */ { PFM_REG_COUNTING, 0, 0x0, -1, NULL, NULL, {0,0, 0, 0}, {RDEP(8),0, 0, 0}}, |
---|
72 | /* pmd9 */ { PFM_REG_COUNTING, 0, 0x0, -1, NULL, NULL, {0,0, 0, 0}, {RDEP(9),0, 0, 0}}, |
---|
73 | /* pmd10 */ { PFM_REG_COUNTING, 0, 0x0, -1, NULL, NULL, {0,0, 0, 0}, {RDEP(10),0, 0, 0}}, |
---|
74 | /* pmd11 */ { PFM_REG_COUNTING, 0, 0x0, -1, NULL, NULL, {0,0, 0, 0}, {RDEP(11),0, 0, 0}}, |
---|
75 | /* pmd12 */ { PFM_REG_COUNTING, 0, 0x0, -1, NULL, NULL, {0,0, 0, 0}, {RDEP(12),0, 0, 0}}, |
---|
76 | /* pmd13 */ { PFM_REG_COUNTING, 0, 0x0, -1, NULL, NULL, {0,0, 0, 0}, {RDEP(13),0, 0, 0}}, |
---|
77 | /* pmd14 */ { PFM_REG_COUNTING, 0, 0x0, -1, NULL, NULL, {0,0, 0, 0}, {RDEP(14),0, 0, 0}}, |
---|
78 | /* pmd15 */ { PFM_REG_COUNTING, 0, 0x0, -1, NULL, NULL, {0,0, 0, 0}, {RDEP(15),0, 0, 0}}, |
---|
79 | /* pmd16 */ { PFM_REG_NOTIMPL, }, |
---|
80 | /* pmd17 */ { PFM_REG_NOTIMPL, }, |
---|
81 | /* pmd18 */ { PFM_REG_NOTIMPL, }, |
---|
82 | /* pmd19 */ { PFM_REG_NOTIMPL, }, |
---|
83 | /* pmd20 */ { PFM_REG_NOTIMPL, }, |
---|
84 | /* pmd21 */ { PFM_REG_NOTIMPL, }, |
---|
85 | /* pmd22 */ { PFM_REG_NOTIMPL, }, |
---|
86 | /* pmd23 */ { PFM_REG_NOTIMPL, }, |
---|
87 | /* pmd24 */ { PFM_REG_NOTIMPL, }, |
---|
88 | /* pmd25 */ { PFM_REG_NOTIMPL, }, |
---|
89 | /* pmd26 */ { PFM_REG_NOTIMPL, }, |
---|
90 | /* pmd27 */ { PFM_REG_NOTIMPL, }, |
---|
91 | /* pmd28 */ { PFM_REG_NOTIMPL, }, |
---|
92 | /* pmd29 */ { PFM_REG_NOTIMPL, }, |
---|
93 | /* pmd30 */ { PFM_REG_NOTIMPL, }, |
---|
94 | /* pmd31 */ { PFM_REG_NOTIMPL, }, |
---|
95 | /* pmd32 */ { PFM_REG_BUFFER, 0, 0x0, -1, NULL, NULL, {RDEP(33)|RDEP(36),0, 0, 0}, {RDEP(40),0, 0, 0}}, |
---|
96 | /* pmd33 */ { PFM_REG_BUFFER, 0, 0x0, -1, NULL, NULL, {RDEP(32)|RDEP(36),0, 0, 0}, {RDEP(40),0, 0, 0}}, |
---|
97 | /* pmd34 */ { PFM_REG_BUFFER, 0, 0x0, -1, NULL, NULL, {RDEP(35),0, 0, 0}, {RDEP(37),0, 0, 0}}, |
---|
98 | /* pmd35 */ { PFM_REG_BUFFER, 0, 0x0, -1, NULL, NULL, {RDEP(34),0, 0, 0}, {RDEP(37),0, 0, 0}}, |
---|
99 | /* pmd36 */ { PFM_REG_BUFFER, 0, 0x0, -1, NULL, NULL, {RDEP(32)|RDEP(33),0, 0, 0}, {RDEP(40),0, 0, 0}}, |
---|
100 | /* pmd37 */ { PFM_REG_NOTIMPL, }, |
---|
101 | /* pmd38 */ { PFM_REG_BUFFER, 0, 0x0, -1, NULL, NULL, {RDEP_MONT_ETB,0, 0, 0}, {RDEP(39),0, 0, 0}}, |
---|
102 | /* pmd39 */ { PFM_REG_BUFFER, 0, 0x0, -1, NULL, NULL, {RDEP_MONT_ETB,0, 0, 0}, {RDEP(39),0, 0, 0}}, |
---|
103 | /* pmd40 */ { PFM_REG_NOTIMPL, }, |
---|
104 | /* pmd41 */ { PFM_REG_NOTIMPL, }, |
---|
105 | /* pmd42 */ { PFM_REG_NOTIMPL, }, |
---|
106 | /* pmd43 */ { PFM_REG_NOTIMPL, }, |
---|
107 | /* pmd44 */ { PFM_REG_NOTIMPL, }, |
---|
108 | /* pmd45 */ { PFM_REG_NOTIMPL, }, |
---|
109 | /* pmd46 */ { PFM_REG_NOTIMPL, }, |
---|
110 | /* pmd47 */ { PFM_REG_NOTIMPL, }, |
---|
111 | /* pmd48 */ { PFM_REG_BUFFER, 0, 0x0, -1, NULL, NULL, {RDEP_MONT_ETB,0, 0, 0}, {RDEP(39),0, 0, 0}}, |
---|
112 | /* pmd49 */ { PFM_REG_BUFFER, 0, 0x0, -1, NULL, NULL, {RDEP_MONT_ETB,0, 0, 0}, {RDEP(39),0, 0, 0}}, |
---|
113 | /* pmd50 */ { PFM_REG_BUFFER, 0, 0x0, -1, NULL, NULL, {RDEP_MONT_ETB,0, 0, 0}, {RDEP(39),0, 0, 0}}, |
---|
114 | /* pmd51 */ { PFM_REG_BUFFER, 0, 0x0, -1, NULL, NULL, {RDEP_MONT_ETB,0, 0, 0}, {RDEP(39),0, 0, 0}}, |
---|
115 | /* pmd52 */ { PFM_REG_BUFFER, 0, 0x0, -1, NULL, NULL, {RDEP_MONT_ETB,0, 0, 0}, {RDEP(39),0, 0, 0}}, |
---|
116 | /* pmd53 */ { PFM_REG_BUFFER, 0, 0x0, -1, NULL, NULL, {RDEP_MONT_ETB,0, 0, 0}, {RDEP(39),0, 0, 0}}, |
---|
117 | /* pmd54 */ { PFM_REG_BUFFER, 0, 0x0, -1, NULL, NULL, {RDEP_MONT_ETB,0, 0, 0}, {RDEP(39),0, 0, 0}}, |
---|
118 | /* pmd55 */ { PFM_REG_BUFFER, 0, 0x0, -1, NULL, NULL, {RDEP_MONT_ETB,0, 0, 0}, {RDEP(39),0, 0, 0}}, |
---|
119 | /* pmd56 */ { PFM_REG_BUFFER, 0, 0x0, -1, NULL, NULL, {RDEP_MONT_ETB,0, 0, 0}, {RDEP(39),0, 0, 0}}, |
---|
120 | /* pmd57 */ { PFM_REG_BUFFER, 0, 0x0, -1, NULL, NULL, {RDEP_MONT_ETB,0, 0, 0}, {RDEP(39),0, 0, 0}}, |
---|
121 | /* pmd58 */ { PFM_REG_BUFFER, 0, 0x0, -1, NULL, NULL, {RDEP_MONT_ETB,0, 0, 0}, {RDEP(39),0, 0, 0}}, |
---|
122 | /* pmd59 */ { PFM_REG_BUFFER, 0, 0x0, -1, NULL, NULL, {RDEP_MONT_ETB,0, 0, 0}, {RDEP(39),0, 0, 0}}, |
---|
123 | /* pmd60 */ { PFM_REG_BUFFER, 0, 0x0, -1, NULL, NULL, {RDEP_MONT_ETB,0, 0, 0}, {RDEP(39),0, 0, 0}}, |
---|
124 | /* pmd61 */ { PFM_REG_BUFFER, 0, 0x0, -1, NULL, NULL, {RDEP_MONT_ETB,0, 0, 0}, {RDEP(39),0, 0, 0}}, |
---|
125 | /* pmd62 */ { PFM_REG_BUFFER, 0, 0x0, -1, NULL, NULL, {RDEP_MONT_ETB,0, 0, 0}, {RDEP(39),0, 0, 0}}, |
---|
126 | /* pmd63 */ { PFM_REG_BUFFER, 0, 0x0, -1, NULL, NULL, {RDEP_MONT_ETB,0, 0, 0}, {RDEP(39),0, 0, 0}}, |
---|
127 | { PFM_REG_END , 0, 0x0, -1, NULL, NULL, {0,}, {0,}}, /* end marker */ |
---|
128 | }; |
---|
129 | |
---|
130 | /* |
---|
131 | * PMC reserved fields must have their power-up values preserved |
---|
132 | */ |
---|
133 | static int |
---|
134 | pfm_mont_reserved(unsigned int cnum, unsigned long *val, struct pt_regs *regs) |
---|
135 | { |
---|
136 | unsigned long tmp1, tmp2, ival = *val; |
---|
137 | |
---|
138 | /* remove reserved areas from user value */ |
---|
139 | tmp1 = ival & PMC_RSVD_MASK(cnum); |
---|
140 | |
---|
141 | /* get reserved fields values */ |
---|
142 | tmp2 = PMC_DFL_VAL(cnum) & ~PMC_RSVD_MASK(cnum); |
---|
143 | |
---|
144 | *val = tmp1 | tmp2; |
---|
145 | |
---|
146 | DPRINT(("pmc[%d]=0x%lx, mask=0x%lx, reset=0x%lx, val=0x%lx\n", |
---|
147 | cnum, ival, PMC_RSVD_MASK(cnum), PMC_DFL_VAL(cnum), *val)); |
---|
148 | return 0; |
---|
149 | } |
---|
150 | |
---|
151 | /* |
---|
152 | * task can be NULL if the context is unloaded |
---|
153 | */ |
---|
154 | static int |
---|
155 | pfm_mont_pmc_check(struct task_struct *task, pfm_context_t *ctx, unsigned int cnum, unsigned long *val, struct pt_regs *regs) |
---|
156 | { |
---|
157 | int ret = 0; |
---|
158 | unsigned long val32 = 0, val38 = 0, val41 = 0; |
---|
159 | unsigned long tmpval; |
---|
160 | int check_case1 = 0; |
---|
161 | int is_loaded; |
---|
162 | |
---|
163 | /* first preserve the reserved fields */ |
---|
164 | pfm_mont_reserved(cnum, val, regs); |
---|
165 | |
---|
166 | tmpval = *val; |
---|
167 | |
---|
168 | /* sanity check */ |
---|
169 | if (ctx == NULL) return -EINVAL; |
---|
170 | |
---|
171 | is_loaded = ctx->ctx_state == PFM_CTX_LOADED || ctx->ctx_state == PFM_CTX_MASKED; |
---|
172 | |
---|
173 | /* |
---|
174 | * we must clear the debug registers if pmc41 has a value which enable |
---|
175 | * memory pipeline event constraints. In this case we need to clear the |
---|
176 | * the debug registers if they have not yet been accessed. This is required |
---|
177 | * to avoid picking stale state. |
---|
178 | * PMC41 is "active" if: |
---|
179 | * one of the pmc41.cfg_dtagXX field is different from 0x3 |
---|
180 | * AND |
---|
181 | * at the corresponding pmc41.en_dbrpXX is set. |
---|
182 | * AND |
---|
183 | * ctx_fl_using_dbreg == 0 (i.e., dbr not yet used) |
---|
184 | */ |
---|
185 | DPRINT(("cnum=%u val=0x%lx, using_dbreg=%d loaded=%d\n", cnum, tmpval, ctx->ctx_fl_using_dbreg, is_loaded)); |
---|
186 | |
---|
187 | if (cnum == 41 && is_loaded |
---|
188 | && (tmpval & 0x1e00000000000) && (tmpval & 0x18181818UL) != 0x18181818UL && ctx->ctx_fl_using_dbreg == 0) { |
---|
189 | |
---|
190 | DPRINT(("pmc[%d]=0x%lx has active pmc41 settings, clearing dbr\n", cnum, tmpval)); |
---|
191 | |
---|
192 | /* don't mix debug with perfmon */ |
---|
193 | if (task && (task->thread.flags & IA64_THREAD_DBG_VALID) != 0) return -EINVAL; |
---|
194 | |
---|
195 | /* |
---|
196 | * a count of 0 will mark the debug registers if: |
---|
197 | * AND |
---|
198 | */ |
---|
199 | ret = pfm_write_ibr_dbr(PFM_DATA_RR, ctx, NULL, 0, regs); |
---|
200 | if (ret) return ret; |
---|
201 | } |
---|
202 | /* |
---|
203 | * we must clear the (instruction) debug registers if: |
---|
204 | * pmc38.ig_ibrpX is 0 (enabled) |
---|
205 | * AND |
---|
206 | * ctx_fl_using_dbreg == 0 (i.e., dbr not yet used) |
---|
207 | */ |
---|
208 | if (cnum == 38 && is_loaded && ((tmpval & 0x492UL) != 0x492UL) && ctx->ctx_fl_using_dbreg == 0) { |
---|
209 | |
---|
210 | DPRINT(("pmc38=0x%lx has active pmc38 settings, clearing ibr\n", tmpval)); |
---|
211 | |
---|
212 | /* don't mix debug with perfmon */ |
---|
213 | if (task && (task->thread.flags & IA64_THREAD_DBG_VALID) != 0) return -EINVAL; |
---|
214 | |
---|
215 | /* |
---|
216 | * a count of 0 will mark the debug registers as in use and also |
---|
217 | * ensure that they are properly cleared. |
---|
218 | */ |
---|
219 | ret = pfm_write_ibr_dbr(PFM_CODE_RR, ctx, NULL, 0, regs); |
---|
220 | if (ret) return ret; |
---|
221 | |
---|
222 | } |
---|
223 | switch(cnum) { |
---|
224 | case 32: val32 = *val; |
---|
225 | val38 = ctx->ctx_pmcs[38]; |
---|
226 | val41 = ctx->ctx_pmcs[41]; |
---|
227 | check_case1 = 1; |
---|
228 | break; |
---|
229 | case 38: val38 = *val; |
---|
230 | val32 = ctx->ctx_pmcs[32]; |
---|
231 | val41 = ctx->ctx_pmcs[41]; |
---|
232 | check_case1 = 1; |
---|
233 | break; |
---|
234 | case 41: val41 = *val; |
---|
235 | val32 = ctx->ctx_pmcs[32]; |
---|
236 | val38 = ctx->ctx_pmcs[38]; |
---|
237 | check_case1 = 1; |
---|
238 | break; |
---|
239 | } |
---|
240 | /* check illegal configuration which can produce inconsistencies in tagging |
---|
241 | * i-side events in L1D and L2 caches |
---|
242 | */ |
---|
243 | if (check_case1) { |
---|
244 | ret = (((val41 >> 45) & 0xf) == 0 && ((val32>>57) & 0x1) == 0) |
---|
245 | && ((((val38>>1) & 0x3) == 0x2 || ((val38>>1) & 0x3) == 0) |
---|
246 | || (((val38>>4) & 0x3) == 0x2 || ((val38>>4) & 0x3) == 0)); |
---|
247 | if (ret) { |
---|
248 | DPRINT(("invalid config pmc38=0x%lx pmc41=0x%lx pmc32=0x%lx\n", val38, val41, val32)); |
---|
249 | return -EINVAL; |
---|
250 | } |
---|
251 | } |
---|
252 | *val = tmpval; |
---|
253 | return 0; |
---|
254 | } |
---|
255 | |
---|
256 | /* |
---|
257 | * impl_pmcs, impl_pmds are computed at runtime to minimize errors! |
---|
258 | */ |
---|
259 | static pmu_config_t pmu_conf_mont={ |
---|
260 | .pmu_name = "Montecito", |
---|
261 | .pmu_family = 0x20, |
---|
262 | .flags = PFM_PMU_IRQ_RESEND, |
---|
263 | .ovfl_val = (1UL << 47) - 1, |
---|
264 | .pmd_desc = pfm_mont_pmd_desc, |
---|
265 | .pmc_desc = pfm_mont_pmc_desc, |
---|
266 | .num_ibrs = 8, |
---|
267 | .num_dbrs = 8, |
---|
268 | .use_rr_dbregs = 1 /* debug register are use for range retrictions */ |
---|
269 | }; |
---|