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Last change on this file since 34 was 34, checked in by hartmans, 18 years ago
Add xen and xen-common
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1	/*
2	* Here is where the ball gets rolling as far as the kernel is concerned.
3	* When control is transferred to _start, the bootload has already
4	* loaded us to the correct address. All that's left to do here is
5	* to set up the kernel's global pointer and jump to the kernel
6	* entry point.
7	*
8	* Copyright (C) 1998-2001, 2003, 2005 Hewlett-Packard Co
9	* David Mosberger-Tang <davidm@hpl.hp.com>
10	* Stephane Eranian <eranian@hpl.hp.com>
11	* Copyright (C) 1999 VA Linux Systems
12	* Copyright (C) 1999 Walt Drummond <drummond@valinux.com>
13	* Copyright (C) 1999 Intel Corp.
14	* Copyright (C) 1999 Asit Mallick <Asit.K.Mallick@intel.com>
15	* Copyright (C) 1999 Don Dugger <Don.Dugger@intel.com>
16	* Copyright (C) 2002 Fenghua Yu <fenghua.yu@intel.com>
17	* -Optimize __ia64_save_fpu() and __ia64_load_fpu() for Itanium 2.
18	* Copyright (C) 2004 Ashok Raj <ashok.raj@intel.com>
19	* Support for CPU Hotplug
20	*/
21
22	#include <linux/config.h>
23
24	#include <asm/asmmacro.h>
25	#include <asm/fpu.h>
26	#include <asm/kregs.h>
27	#include <asm/mmu_context.h>
28	#include <asm/offsets.h>
29	#include <asm/pal.h>
30	#include <asm/pgtable.h>
31	#include <asm/processor.h>
32	#include <asm/ptrace.h>
33	#include <asm/system.h>
34	#include <asm/mca_asm.h>
35
36	#ifdef CONFIG_HOTPLUG_CPU
37	#define SAL_PSR_BITS_TO_SET \
38	(IA64_PSR_AC \| IA64_PSR_BN \| IA64_PSR_MFH \| IA64_PSR_MFL)
39
40	#define SAVE_FROM_REG(src, ptr, dest) \
41	mov dest=src;; \
42	st8 [ptr]=dest,0x08
43
44	#define RESTORE_REG(reg, ptr, _tmp) \
45	ld8 _tmp=[ptr],0x08;; \
46	mov reg=_tmp
47
48	#define SAVE_BREAK_REGS(ptr, _idx, _breg, _dest)\
49	mov ar.lc=IA64_NUM_DBG_REGS-1;; \
50	mov _idx=0;; \
51	1: \
52	SAVE_FROM_REG(_breg[_idx], ptr, _dest);; \
53	add _idx=1,_idx;; \
54	br.cloop.sptk.many 1b
55
56	#define RESTORE_BREAK_REGS(ptr, _idx, _breg, _tmp, _lbl)\
57	mov ar.lc=IA64_NUM_DBG_REGS-1;; \
58	mov _idx=0;; \
59	_lbl: RESTORE_REG(_breg[_idx], ptr, _tmp);; \
60	add _idx=1, _idx;; \
61	br.cloop.sptk.many _lbl
62
63	#define SAVE_ONE_RR(num, _reg, _tmp) \
64	movl _tmp=(num<<61);; \
65	mov _reg=rr[_tmp]
66
67	#define SAVE_REGION_REGS(_tmp, _r0, _r1, _r2, _r3, _r4, _r5, _r6, _r7) \
68	SAVE_ONE_RR(0,_r0, _tmp);; \
69	SAVE_ONE_RR(1,_r1, _tmp);; \
70	SAVE_ONE_RR(2,_r2, _tmp);; \
71	SAVE_ONE_RR(3,_r3, _tmp);; \
72	SAVE_ONE_RR(4,_r4, _tmp);; \
73	SAVE_ONE_RR(5,_r5, _tmp);; \
74	SAVE_ONE_RR(6,_r6, _tmp);; \
75	SAVE_ONE_RR(7,_r7, _tmp);;
76
77	#define STORE_REGION_REGS(ptr, _r0, _r1, _r2, _r3, _r4, _r5, _r6, _r7) \
78	st8 [ptr]=_r0, 8;; \
79	st8 [ptr]=_r1, 8;; \
80	st8 [ptr]=_r2, 8;; \
81	st8 [ptr]=_r3, 8;; \
82	st8 [ptr]=_r4, 8;; \
83	st8 [ptr]=_r5, 8;; \
84	st8 [ptr]=_r6, 8;; \
85	st8 [ptr]=_r7, 8;;
86
87	#define RESTORE_REGION_REGS(ptr, _idx1, _idx2, _tmp) \
88	mov ar.lc=0x08-1;; \
89	movl _idx1=0x00;; \
90	RestRR: \
91	dep.z _idx2=_idx1,61,3;; \
92	ld8 _tmp=[ptr],8;; \
93	mov rr[_idx2]=_tmp;; \
94	srlz.d;; \
95	add _idx1=1,_idx1;; \
96	br.cloop.sptk.few RestRR
97
98	#define SET_AREA_FOR_BOOTING_CPU(reg1, reg2) \
99	movl reg1=sal_state_for_booting_cpu;; \
100	ld8 reg2=[reg1];;
101
102	/*
103	* Adjust region registers saved before starting to save
104	* break regs and rest of the states that need to be preserved.
105	*/
106	#define SAL_TO_OS_BOOT_HANDOFF_STATE_SAVE(_reg1,_reg2,_pred) \
107	SAVE_FROM_REG(b0,_reg1,_reg2);; \
108	SAVE_FROM_REG(b1,_reg1,_reg2);; \
109	SAVE_FROM_REG(b2,_reg1,_reg2);; \
110	SAVE_FROM_REG(b3,_reg1,_reg2);; \
111	SAVE_FROM_REG(b4,_reg1,_reg2);; \
112	SAVE_FROM_REG(b5,_reg1,_reg2);; \
113	st8 [_reg1]=r1,0x08;; \
114	st8 [_reg1]=r12,0x08;; \
115	st8 [_reg1]=r13,0x08;; \
116	SAVE_FROM_REG(ar.fpsr,_reg1,_reg2);; \
117	SAVE_FROM_REG(ar.pfs,_reg1,_reg2);; \
118	SAVE_FROM_REG(ar.rnat,_reg1,_reg2);; \
119	SAVE_FROM_REG(ar.unat,_reg1,_reg2);; \
120	SAVE_FROM_REG(ar.bspstore,_reg1,_reg2);; \
121	SAVE_FROM_REG(cr.dcr,_reg1,_reg2);; \
122	SAVE_FROM_REG(cr.iva,_reg1,_reg2);; \
123	SAVE_FROM_REG(cr.pta,_reg1,_reg2);; \
124	SAVE_FROM_REG(cr.itv,_reg1,_reg2);; \
125	SAVE_FROM_REG(cr.pmv,_reg1,_reg2);; \
126	SAVE_FROM_REG(cr.cmcv,_reg1,_reg2);; \
127	SAVE_FROM_REG(cr.lrr0,_reg1,_reg2);; \
128	SAVE_FROM_REG(cr.lrr1,_reg1,_reg2);; \
129	st8 [_reg1]=r4,0x08;; \
130	st8 [_reg1]=r5,0x08;; \
131	st8 [_reg1]=r6,0x08;; \
132	st8 [_reg1]=r7,0x08;; \
133	st8 [_reg1]=_pred,0x08;; \
134	SAVE_FROM_REG(ar.lc, _reg1, _reg2);; \
135	stf.spill.nta [_reg1]=f2,16;; \
136	stf.spill.nta [_reg1]=f3,16;; \
137	stf.spill.nta [_reg1]=f4,16;; \
138	stf.spill.nta [_reg1]=f5,16;; \
139	stf.spill.nta [_reg1]=f16,16;; \
140	stf.spill.nta [_reg1]=f17,16;; \
141	stf.spill.nta [_reg1]=f18,16;; \
142	stf.spill.nta [_reg1]=f19,16;; \
143	stf.spill.nta [_reg1]=f20,16;; \
144	stf.spill.nta [_reg1]=f21,16;; \
145	stf.spill.nta [_reg1]=f22,16;; \
146	stf.spill.nta [_reg1]=f23,16;; \
147	stf.spill.nta [_reg1]=f24,16;; \
148	stf.spill.nta [_reg1]=f25,16;; \
149	stf.spill.nta [_reg1]=f26,16;; \
150	stf.spill.nta [_reg1]=f27,16;; \
151	stf.spill.nta [_reg1]=f28,16;; \
152	stf.spill.nta [_reg1]=f29,16;; \
153	stf.spill.nta [_reg1]=f30,16;; \
154	stf.spill.nta [_reg1]=f31,16;;
155
156	#else
157	#define SET_AREA_FOR_BOOTING_CPU(a1, a2)
158	#define SAL_TO_OS_BOOT_HANDOFF_STATE_SAVE(a1,a2, a3)
159	#define SAVE_REGION_REGS(_tmp, _r0, _r1, _r2, _r3, _r4, _r5, _r6, _r7)
160	#define STORE_REGION_REGS(ptr, _r0, _r1, _r2, _r3, _r4, _r5, _r6, _r7)
161	#endif
162
163	#ifdef XEN
164	#define SET_ONE_RR(num, pgsize, _tmp1, _tmp2, vhpt) \
165	movl _tmp1=(num << 61);; \
166	movl _tmp2=((ia64_rid(IA64_REGION_ID_KERNEL, (num<<61)) << 8) \| (pgsize << 2) \| vhpt);; \
167	mov rr[_tmp1]=_tmp2
168	#else
169	#define SET_ONE_RR(num, pgsize, _tmp1, _tmp2, vhpt) \
170	movl _tmp1=(num << 61);; \
171	mov _tmp2=((ia64_rid(IA64_REGION_ID_KERNEL, (num<<61)) << 8) \| (pgsize << 2) \| vhpt);; \
172	mov rr[_tmp1]=_tmp2
173	#endif
174
175	.section __special_page_section,"ax"
176
177	.global empty_zero_page
178	empty_zero_page:
179	.skip PAGE_SIZE
180
181	#ifndef XEN
182	.global swapper_pg_dir
183	swapper_pg_dir:
184	.skip PAGE_SIZE
185	#endif
186
187	#if defined(XEN) && defined(CONFIG_VIRTUAL_FRAME_TABLE)
188	.global frametable_pg_dir
189	frametable_pg_dir:
190	.skip PAGE_SIZE
191	#endif
192
193	.rodata
194	halt_msg:
195	stringz "Halting kernel\n"
196
197	.text
198
199	.global start_ap
200
201	/*
202	* Start the kernel. When the bootloader passes control to _start(), r28
203	* points to the address of the boot parameter area. Execution reaches
204	* here in physical mode.
205	*/
206	GLOBAL_ENTRY(_start)
207	start_ap:
208	.prologue
209	.save rp, r0 // terminate unwind chain with a NULL rp
210	.body
211
212	rsm psr.i \| psr.ic
213	;;
214	srlz.i
215	;;
216	/*
217	* Save the region registers, predicate before they get clobbered
218	*/
219	SAVE_REGION_REGS(r2, r8,r9,r10,r11,r12,r13,r14,r15);
220	mov r25=pr;;
221
222	/*
223	* Initialize kernel region registers:
224	* rr[0]: VHPT enabled, page size = PAGE_SHIFT
225	* rr[1]: VHPT enabled, page size = PAGE_SHIFT
226	* rr[2]: VHPT enabled, page size = PAGE_SHIFT
227	* rr[3]: VHPT enabled, page size = PAGE_SHIFT
228	* rr[4]: VHPT enabled, page size = PAGE_SHIFT
229	* rr[5]: VHPT enabled, page size = PAGE_SHIFT
230	* rr[6]: VHPT disabled, page size = IA64_GRANULE_SHIFT
231	* rr[7]: VHPT disabled, page size = IA64_GRANULE_SHIFT
232	* We initialize all of them to prevent inadvertently assuming
233	* something about the state of address translation early in boot.
234	*/
235	SET_ONE_RR(0, PAGE_SHIFT, r2, r16, 1);;
236	SET_ONE_RR(1, PAGE_SHIFT, r2, r16, 1);;
237	SET_ONE_RR(2, PAGE_SHIFT, r2, r16, 1);;
238	SET_ONE_RR(3, PAGE_SHIFT, r2, r16, 1);;
239	SET_ONE_RR(4, PAGE_SHIFT, r2, r16, 1);;
240	SET_ONE_RR(5, PAGE_SHIFT, r2, r16, 1);;
241	SET_ONE_RR(6, IA64_GRANULE_SHIFT, r2, r16, 0);;
242	SET_ONE_RR(7, IA64_GRANULE_SHIFT, r2, r16, 0);;
243	/*
244	* Now pin mappings into the TLB for kernel text and data
245	*/
246	mov r18=KERNEL_TR_PAGE_SHIFT<<2
247	movl r17=KERNEL_START
248	;;
249	mov cr.itir=r18
250	mov cr.ifa=r17
251	mov r16=IA64_TR_KERNEL
252	mov r3=ip
253	movl r18=PAGE_KERNEL
254	;;
255	dep r2=0,r3,0,KERNEL_TR_PAGE_SHIFT
256	;;
257	or r18=r2,r18
258	;;
259	srlz.i
260	;;
261	itr.i itr[r16]=r18
262	;;
263	itr.d dtr[r16]=r18
264	;;
265	srlz.i
266
267	/*
268	* Switch into virtual mode:
269	*/
270	movl r16=(IA64_PSR_IT\|IA64_PSR_IC\|IA64_PSR_DT\|IA64_PSR_RT\|IA64_PSR_DFH\|IA64_PSR_BN \
271	\|IA64_PSR_DI)
272	;;
273	mov cr.ipsr=r16
274	movl r17=1f
275	;;
276	mov cr.iip=r17
277	mov cr.ifs=r0
278	;;
279	rfi
280	;;
281	1: // now we are in virtual mode
282
283	SET_AREA_FOR_BOOTING_CPU(r2, r16);
284
285	STORE_REGION_REGS(r16, r8,r9,r10,r11,r12,r13,r14,r15);
286	SAL_TO_OS_BOOT_HANDOFF_STATE_SAVE(r16,r17,r25)
287	;;
288
289	// set IVT entry point---can't access I/O ports without it
290	movl r3=ia64_ivt
291	;;
292	mov cr.iva=r3
293	movl r2=FPSR_DEFAULT
294	;;
295	srlz.i
296	movl gp=__gp
297
298	mov ar.fpsr=r2
299	;;
300
301	#define isAP p2 // are we an Application Processor?
302	#define isBP p3 // are we the Bootstrap Processor?
303
304	#ifdef CONFIG_SMP
305	/*
306	* Find the init_task for the currently booting CPU. At poweron, and in
307	* UP mode, task_for_booting_cpu is NULL.
308	*/
309	movl r3=task_for_booting_cpu
310	;;
311	ld8 r3=[r3]
312	movl r2=init_task
313	;;
314	cmp.eq isBP,isAP=r3,r0
315	;;
316	(isAP) mov r2=r3
317	#else
318	movl r2=init_task
319	cmp.eq isBP,isAP=r0,r0
320	#endif
321	;;
322	tpa r3=r2 // r3 == phys addr of task struct
323	mov r16=-1
324	(isBP) br.cond.dpnt .load_current // BP stack is on region 5 --- no need to map it
325
326	#ifndef XEN
327	// XEN: stack is allocated in xenheap, which is currently always
328	// mapped.
329	// load mapping for stack (virtaddr in r2, physaddr in r3)
330	rsm psr.ic
331	movl r17=PAGE_KERNEL
332	;;
333	srlz.d
334	dep r18=0,r3,0,12
335	;;
336	or r18=r17,r18
337	#ifdef XEN
338	dep r2=-1,r3,60,4 // IMVA of task
339	#else
340	dep r2=-1,r3,61,3 // IMVA of task
341	#endif
342	;;
343	mov r17=rr[r2]
344	shr.u r16=r3,IA64_GRANULE_SHIFT
345	;;
346	dep r17=0,r17,8,24
347	;;
348	mov cr.itir=r17
349	mov cr.ifa=r2
350
351	mov r19=IA64_TR_CURRENT_STACK
352	;;
353	itr.d dtr[r19]=r18
354	;;
355	ssm psr.ic
356	srlz.d
357	#endif
358	;;
359
360	.load_current:
361	// load the "current" pointer (r13) and ar.k6 with the current task
362	mov IA64_KR(CURRENT)=r2 // virtual address
363	mov IA64_KR(CURRENT_STACK)=r16
364	mov r13=r2
365	/*
366	* Reserve space at the top of the stack for "struct pt_regs". Kernel
367	* threads don't store interesting values in that structure, but the space
368	* still needs to be there because time-critical stuff such as the context
369	* switching can be implemented more efficiently (for example, __switch_to()
370	* always sets the psr.dfh bit of the task it is switching to).
371	*/
372
373	addl r12=IA64_STK_OFFSET-IA64_PT_REGS_SIZE-16,r2
374	addl r2=IA64_RBS_OFFSET,r2 // initialize the RSE
375	mov ar.rsc=0 // place RSE in enforced lazy mode
376	;;
377	loadrs // clear the dirty partition
378	;;
379	mov ar.bspstore=r2 // establish the new RSE stack
380	;;
381	mov ar.rsc=0x3 // place RSE in eager mode
382
383	#ifdef XEN
384	(isBP) dep r28=-1,r28,60,4 // make address virtual
385	#else
386	(isBP) dep r28=-1,r28,61,3 // make address virtual
387	#endif
388	(isBP) movl r2=ia64_boot_param
389	;;
390	(isBP) st8 [r2]=r28 // save the address of the boot param area passed by the bootloader
391
392	#ifdef CONFIG_SMP
393	(isAP) br.call.sptk.many rp=start_secondary
394	.ret0:
395	(isAP) br.cond.sptk self
396	#endif
397
398	// This is executed by the bootstrap processor (bsp) only:
399
400	#ifdef CONFIG_IA64_FW_EMU
401	// initialize PAL & SAL emulator:
402	br.call.sptk.many rp=sys_fw_init
403	.ret1:
404	#endif
405	br.call.sptk.many rp=start_kernel
406	.ret2: addl r3=@ltoff(halt_msg),gp
407	;;
408	alloc r2=ar.pfs,8,0,2,0
409	;;
410	ld8 out0=[r3]
411	br.call.sptk.many b0=console_print
412
413	self: hint @pause
414	#ifdef XEN
415	;;
416	br.sptk.many self // endless loop
417	;;
418	#else
419	br.sptk.many self // endless loop
420	#endif
421	END(_start)
422
423	GLOBAL_ENTRY(ia64_save_debug_regs)
424	alloc r16=ar.pfs,1,0,0,0
425	mov r20=ar.lc // preserve ar.lc
426	mov ar.lc=IA64_NUM_DBG_REGS-1
427	mov r18=0
428	add r19=IA64_NUM_DBG_REGS*8,in0
429	;;
430	1: mov r16=dbr[r18]
431	#ifdef CONFIG_ITANIUM
432	;;
433	srlz.d
434	#endif
435	mov r17=ibr[r18]
436	add r18=1,r18
437	;;
438	st8.nta [in0]=r16,8
439	st8.nta [r19]=r17,8
440	br.cloop.sptk.many 1b
441	;;
442	mov ar.lc=r20 // restore ar.lc
443	br.ret.sptk.many rp
444	END(ia64_save_debug_regs)
445
446	GLOBAL_ENTRY(ia64_load_debug_regs)
447	alloc r16=ar.pfs,1,0,0,0
448	lfetch.nta [in0]
449	mov r20=ar.lc // preserve ar.lc
450	add r19=IA64_NUM_DBG_REGS*8,in0
451	mov ar.lc=IA64_NUM_DBG_REGS-1
452	mov r18=-1
453	;;
454	1: ld8.nta r16=[in0],8
455	ld8.nta r17=[r19],8
456	add r18=1,r18
457	;;
458	mov dbr[r18]=r16
459	#ifdef CONFIG_ITANIUM
460	;;
461	srlz.d // Errata 132 (NoFix status)
462	#endif
463	mov ibr[r18]=r17
464	br.cloop.sptk.many 1b
465	;;
466	mov ar.lc=r20 // restore ar.lc
467	br.ret.sptk.many rp
468	END(ia64_load_debug_regs)
469
470	GLOBAL_ENTRY(__ia64_save_fpu)
471	alloc r2=ar.pfs,1,4,0,0
472	adds loc0=96*16-16,in0
473	adds loc1=96*16-16-128,in0
474	;;
475	stf.spill.nta [loc0]=f127,-256
476	stf.spill.nta [loc1]=f119,-256
477	;;
478	stf.spill.nta [loc0]=f111,-256
479	stf.spill.nta [loc1]=f103,-256
480	;;
481	stf.spill.nta [loc0]=f95,-256
482	stf.spill.nta [loc1]=f87,-256
483	;;
484	stf.spill.nta [loc0]=f79,-256
485	stf.spill.nta [loc1]=f71,-256
486	;;
487	stf.spill.nta [loc0]=f63,-256
488	stf.spill.nta [loc1]=f55,-256
489	adds loc2=96*16-32,in0
490	;;
491	stf.spill.nta [loc0]=f47,-256
492	stf.spill.nta [loc1]=f39,-256
493	adds loc3=96*16-32-128,in0
494	;;
495	stf.spill.nta [loc2]=f126,-256
496	stf.spill.nta [loc3]=f118,-256
497	;;
498	stf.spill.nta [loc2]=f110,-256
499	stf.spill.nta [loc3]=f102,-256
500	;;
501	stf.spill.nta [loc2]=f94,-256
502	stf.spill.nta [loc3]=f86,-256
503	;;
504	stf.spill.nta [loc2]=f78,-256
505	stf.spill.nta [loc3]=f70,-256
506	;;
507	stf.spill.nta [loc2]=f62,-256
508	stf.spill.nta [loc3]=f54,-256
509	adds loc0=96*16-48,in0
510	;;
511	stf.spill.nta [loc2]=f46,-256
512	stf.spill.nta [loc3]=f38,-256
513	adds loc1=96*16-48-128,in0
514	;;
515	stf.spill.nta [loc0]=f125,-256
516	stf.spill.nta [loc1]=f117,-256
517	;;
518	stf.spill.nta [loc0]=f109,-256
519	stf.spill.nta [loc1]=f101,-256
520	;;
521	stf.spill.nta [loc0]=f93,-256
522	stf.spill.nta [loc1]=f85,-256
523	;;
524	stf.spill.nta [loc0]=f77,-256
525	stf.spill.nta [loc1]=f69,-256
526	;;
527	stf.spill.nta [loc0]=f61,-256
528	stf.spill.nta [loc1]=f53,-256
529	adds loc2=96*16-64,in0
530	;;
531	stf.spill.nta [loc0]=f45,-256
532	stf.spill.nta [loc1]=f37,-256
533	adds loc3=96*16-64-128,in0
534	;;
535	stf.spill.nta [loc2]=f124,-256
536	stf.spill.nta [loc3]=f116,-256
537	;;
538	stf.spill.nta [loc2]=f108,-256
539	stf.spill.nta [loc3]=f100,-256
540	;;
541	stf.spill.nta [loc2]=f92,-256
542	stf.spill.nta [loc3]=f84,-256
543	;;
544	stf.spill.nta [loc2]=f76,-256
545	stf.spill.nta [loc3]=f68,-256
546	;;
547	stf.spill.nta [loc2]=f60,-256
548	stf.spill.nta [loc3]=f52,-256
549	adds loc0=96*16-80,in0
550	;;
551	stf.spill.nta [loc2]=f44,-256
552	stf.spill.nta [loc3]=f36,-256
553	adds loc1=96*16-80-128,in0
554	;;
555	stf.spill.nta [loc0]=f123,-256
556	stf.spill.nta [loc1]=f115,-256
557	;;
558	stf.spill.nta [loc0]=f107,-256
559	stf.spill.nta [loc1]=f99,-256
560	;;
561	stf.spill.nta [loc0]=f91,-256
562	stf.spill.nta [loc1]=f83,-256
563	;;
564	stf.spill.nta [loc0]=f75,-256
565	stf.spill.nta [loc1]=f67,-256
566	;;
567	stf.spill.nta [loc0]=f59,-256
568	stf.spill.nta [loc1]=f51,-256
569	adds loc2=96*16-96,in0
570	;;
571	stf.spill.nta [loc0]=f43,-256
572	stf.spill.nta [loc1]=f35,-256
573	adds loc3=96*16-96-128,in0
574	;;
575	stf.spill.nta [loc2]=f122,-256
576	stf.spill.nta [loc3]=f114,-256
577	;;
578	stf.spill.nta [loc2]=f106,-256
579	stf.spill.nta [loc3]=f98,-256
580	;;
581	stf.spill.nta [loc2]=f90,-256
582	stf.spill.nta [loc3]=f82,-256
583	;;
584	stf.spill.nta [loc2]=f74,-256
585	stf.spill.nta [loc3]=f66,-256
586	;;
587	stf.spill.nta [loc2]=f58,-256
588	stf.spill.nta [loc3]=f50,-256
589	adds loc0=96*16-112,in0
590	;;
591	stf.spill.nta [loc2]=f42,-256
592	stf.spill.nta [loc3]=f34,-256
593	adds loc1=96*16-112-128,in0
594	;;
595	stf.spill.nta [loc0]=f121,-256
596	stf.spill.nta [loc1]=f113,-256
597	;;
598	stf.spill.nta [loc0]=f105,-256
599	stf.spill.nta [loc1]=f97,-256
600	;;
601	stf.spill.nta [loc0]=f89,-256
602	stf.spill.nta [loc1]=f81,-256
603	;;
604	stf.spill.nta [loc0]=f73,-256
605	stf.spill.nta [loc1]=f65,-256
606	;;
607	stf.spill.nta [loc0]=f57,-256
608	stf.spill.nta [loc1]=f49,-256
609	adds loc2=96*16-128,in0
610	;;
611	stf.spill.nta [loc0]=f41,-256
612	stf.spill.nta [loc1]=f33,-256
613	adds loc3=96*16-128-128,in0
614	;;
615	stf.spill.nta [loc2]=f120,-256
616	stf.spill.nta [loc3]=f112,-256
617	;;
618	stf.spill.nta [loc2]=f104,-256
619	stf.spill.nta [loc3]=f96,-256
620	;;
621	stf.spill.nta [loc2]=f88,-256
622	stf.spill.nta [loc3]=f80,-256
623	;;
624	stf.spill.nta [loc2]=f72,-256
625	stf.spill.nta [loc3]=f64,-256
626	;;
627	stf.spill.nta [loc2]=f56,-256
628	stf.spill.nta [loc3]=f48,-256
629	;;
630	stf.spill.nta [loc2]=f40
631	stf.spill.nta [loc3]=f32
632	br.ret.sptk.many rp
633	END(__ia64_save_fpu)
634
635	GLOBAL_ENTRY(__ia64_load_fpu)
636	alloc r2=ar.pfs,1,2,0,0
637	adds r3=128,in0
638	adds r14=256,in0
639	adds r15=384,in0
640	mov loc0=512
641	mov loc1=-1024+16
642	;;
643	ldf.fill.nta f32=[in0],loc0
644	ldf.fill.nta f40=[ r3],loc0
645	ldf.fill.nta f48=[r14],loc0
646	ldf.fill.nta f56=[r15],loc0
647	;;
648	ldf.fill.nta f64=[in0],loc0
649	ldf.fill.nta f72=[ r3],loc0
650	ldf.fill.nta f80=[r14],loc0
651	ldf.fill.nta f88=[r15],loc0
652	;;
653	ldf.fill.nta f96=[in0],loc1
654	ldf.fill.nta f104=[ r3],loc1
655	ldf.fill.nta f112=[r14],loc1
656	ldf.fill.nta f120=[r15],loc1
657	;;
658	ldf.fill.nta f33=[in0],loc0
659	ldf.fill.nta f41=[ r3],loc0
660	ldf.fill.nta f49=[r14],loc0
661	ldf.fill.nta f57=[r15],loc0
662	;;
663	ldf.fill.nta f65=[in0],loc0
664	ldf.fill.nta f73=[ r3],loc0
665	ldf.fill.nta f81=[r14],loc0
666	ldf.fill.nta f89=[r15],loc0
667	;;
668	ldf.fill.nta f97=[in0],loc1
669	ldf.fill.nta f105=[ r3],loc1
670	ldf.fill.nta f113=[r14],loc1
671	ldf.fill.nta f121=[r15],loc1
672	;;
673	ldf.fill.nta f34=[in0],loc0
674	ldf.fill.nta f42=[ r3],loc0
675	ldf.fill.nta f50=[r14],loc0
676	ldf.fill.nta f58=[r15],loc0
677	;;
678	ldf.fill.nta f66=[in0],loc0
679	ldf.fill.nta f74=[ r3],loc0
680	ldf.fill.nta f82=[r14],loc0
681	ldf.fill.nta f90=[r15],loc0
682	;;
683	ldf.fill.nta f98=[in0],loc1
684	ldf.fill.nta f106=[ r3],loc1
685	ldf.fill.nta f114=[r14],loc1
686	ldf.fill.nta f122=[r15],loc1
687	;;
688	ldf.fill.nta f35=[in0],loc0
689	ldf.fill.nta f43=[ r3],loc0
690	ldf.fill.nta f51=[r14],loc0
691	ldf.fill.nta f59=[r15],loc0
692	;;
693	ldf.fill.nta f67=[in0],loc0
694	ldf.fill.nta f75=[ r3],loc0
695	ldf.fill.nta f83=[r14],loc0
696	ldf.fill.nta f91=[r15],loc0
697	;;
698	ldf.fill.nta f99=[in0],loc1
699	ldf.fill.nta f107=[ r3],loc1
700	ldf.fill.nta f115=[r14],loc1
701	ldf.fill.nta f123=[r15],loc1
702	;;
703	ldf.fill.nta f36=[in0],loc0
704	ldf.fill.nta f44=[ r3],loc0
705	ldf.fill.nta f52=[r14],loc0
706	ldf.fill.nta f60=[r15],loc0
707	;;
708	ldf.fill.nta f68=[in0],loc0
709	ldf.fill.nta f76=[ r3],loc0
710	ldf.fill.nta f84=[r14],loc0
711	ldf.fill.nta f92=[r15],loc0
712	;;
713	ldf.fill.nta f100=[in0],loc1
714	ldf.fill.nta f108=[ r3],loc1
715	ldf.fill.nta f116=[r14],loc1
716	ldf.fill.nta f124=[r15],loc1
717	;;
718	ldf.fill.nta f37=[in0],loc0
719	ldf.fill.nta f45=[ r3],loc0
720	ldf.fill.nta f53=[r14],loc0
721	ldf.fill.nta f61=[r15],loc0
722	;;
723	ldf.fill.nta f69=[in0],loc0
724	ldf.fill.nta f77=[ r3],loc0
725	ldf.fill.nta f85=[r14],loc0
726	ldf.fill.nta f93=[r15],loc0
727	;;
728	ldf.fill.nta f101=[in0],loc1
729	ldf.fill.nta f109=[ r3],loc1
730	ldf.fill.nta f117=[r14],loc1
731	ldf.fill.nta f125=[r15],loc1
732	;;
733	ldf.fill.nta f38 =[in0],loc0
734	ldf.fill.nta f46 =[ r3],loc0
735	ldf.fill.nta f54 =[r14],loc0
736	ldf.fill.nta f62 =[r15],loc0
737	;;
738	ldf.fill.nta f70 =[in0],loc0
739	ldf.fill.nta f78 =[ r3],loc0
740	ldf.fill.nta f86 =[r14],loc0
741	ldf.fill.nta f94 =[r15],loc0
742	;;
743	ldf.fill.nta f102=[in0],loc1
744	ldf.fill.nta f110=[ r3],loc1
745	ldf.fill.nta f118=[r14],loc1
746	ldf.fill.nta f126=[r15],loc1
747	;;
748	ldf.fill.nta f39 =[in0],loc0
749	ldf.fill.nta f47 =[ r3],loc0
750	ldf.fill.nta f55 =[r14],loc0
751	ldf.fill.nta f63 =[r15],loc0
752	;;
753	ldf.fill.nta f71 =[in0],loc0
754	ldf.fill.nta f79 =[ r3],loc0
755	ldf.fill.nta f87 =[r14],loc0
756	ldf.fill.nta f95 =[r15],loc0
757	;;
758	ldf.fill.nta f103=[in0]
759	ldf.fill.nta f111=[ r3]
760	ldf.fill.nta f119=[r14]
761	ldf.fill.nta f127=[r15]
762	br.ret.sptk.many rp
763	END(__ia64_load_fpu)
764
765	GLOBAL_ENTRY(__ia64_init_fpu)
766	stf.spill [sp]=f0 // M3
767	mov f32=f0 // F
768	nop.b 0
769
770	ldfps f33,f34=[sp] // M0
771	ldfps f35,f36=[sp] // M1
772	mov f37=f0 // F
773	;;
774
775	setf.s f38=r0 // M2
776	setf.s f39=r0 // M3
777	mov f40=f0 // F
778
779	ldfps f41,f42=[sp] // M0
780	ldfps f43,f44=[sp] // M1
781	mov f45=f0 // F
782
783	setf.s f46=r0 // M2
784	setf.s f47=r0 // M3
785	mov f48=f0 // F
786
787	ldfps f49,f50=[sp] // M0
788	ldfps f51,f52=[sp] // M1
789	mov f53=f0 // F
790
791	setf.s f54=r0 // M2
792	setf.s f55=r0 // M3
793	mov f56=f0 // F
794
795	ldfps f57,f58=[sp] // M0
796	ldfps f59,f60=[sp] // M1
797	mov f61=f0 // F
798
799	setf.s f62=r0 // M2
800	setf.s f63=r0 // M3
801	mov f64=f0 // F
802
803	ldfps f65,f66=[sp] // M0
804	ldfps f67,f68=[sp] // M1
805	mov f69=f0 // F
806
807	setf.s f70=r0 // M2
808	setf.s f71=r0 // M3
809	mov f72=f0 // F
810
811	ldfps f73,f74=[sp] // M0
812	ldfps f75,f76=[sp] // M1
813	mov f77=f0 // F
814
815	setf.s f78=r0 // M2
816	setf.s f79=r0 // M3
817	mov f80=f0 // F
818
819	ldfps f81,f82=[sp] // M0
820	ldfps f83,f84=[sp] // M1
821	mov f85=f0 // F
822
823	setf.s f86=r0 // M2
824	setf.s f87=r0 // M3
825	mov f88=f0 // F
826
827	/*
828	* When the instructions are cached, it would be faster to initialize
829	* the remaining registers with simply mov instructions (F-unit).
830	* This gets the time down to ~29 cycles. However, this would use up
831	* 33 bundles, whereas continuing with the above pattern yields
832	* 10 bundles and ~30 cycles.
833	*/
834
835	ldfps f89,f90=[sp] // M0
836	ldfps f91,f92=[sp] // M1
837	mov f93=f0 // F
838
839	setf.s f94=r0 // M2
840	setf.s f95=r0 // M3
841	mov f96=f0 // F
842
843	ldfps f97,f98=[sp] // M0
844	ldfps f99,f100=[sp] // M1
845	mov f101=f0 // F
846
847	setf.s f102=r0 // M2
848	setf.s f103=r0 // M3
849	mov f104=f0 // F
850
851	ldfps f105,f106=[sp] // M0
852	ldfps f107,f108=[sp] // M1
853	mov f109=f0 // F
854
855	setf.s f110=r0 // M2
856	setf.s f111=r0 // M3
857	mov f112=f0 // F
858
859	ldfps f113,f114=[sp] // M0
860	ldfps f115,f116=[sp] // M1
861	mov f117=f0 // F
862
863	setf.s f118=r0 // M2
864	setf.s f119=r0 // M3
865	mov f120=f0 // F
866
867	ldfps f121,f122=[sp] // M0
868	ldfps f123,f124=[sp] // M1
869	mov f125=f0 // F
870
871	setf.s f126=r0 // M2
872	setf.s f127=r0 // M3
873	br.ret.sptk.many rp // F
874	END(__ia64_init_fpu)
875
876	/*
877	* Switch execution mode from virtual to physical
878	*
879	* Inputs:
880	* r16 = new psr to establish
881	* Output:
882	* r19 = old virtual address of ar.bsp
883	* r20 = old virtual address of sp
884	*
885	* Note: RSE must already be in enforced lazy mode
886	*/
887	GLOBAL_ENTRY(ia64_switch_mode_phys)
888	{
889	alloc r2=ar.pfs,0,0,0,0
890	rsm psr.i \| psr.ic // disable interrupts and interrupt collection
891	mov r15=ip
892	}
893	;;
894	{
895	flushrs // must be first insn in group
896	srlz.i
897	}
898	;;
899	mov cr.ipsr=r16 // set new PSR
900	add r3=1f-ia64_switch_mode_phys,r15
901
902	mov r19=ar.bsp
903	mov r20=sp
904	mov r14=rp // get return address into a general register
905	;;
906
907	// going to physical mode, use tpa to translate virt->phys
908	tpa r17=r19
909	tpa r3=r3
910	tpa sp=sp
911	tpa r14=r14
912	;;
913
914	mov r18=ar.rnat // save ar.rnat
915	mov ar.bspstore=r17 // this steps on ar.rnat
916	mov cr.iip=r3
917	mov cr.ifs=r0
918	;;
919	mov ar.rnat=r18 // restore ar.rnat
920	rfi // must be last insn in group
921	;;
922	1: mov rp=r14
923	br.ret.sptk.many rp
924	END(ia64_switch_mode_phys)
925
926	/*
927	* Switch execution mode from physical to virtual
928	*
929	* Inputs:
930	* r16 = new psr to establish
931	* r19 = new bspstore to establish
932	* r20 = new sp to establish
933	*
934	* Note: RSE must already be in enforced lazy mode
935	*/
936	GLOBAL_ENTRY(ia64_switch_mode_virt)
937	{
938	alloc r2=ar.pfs,0,0,0,0
939	rsm psr.i \| psr.ic // disable interrupts and interrupt collection
940	mov r15=ip
941	}
942	;;
943	{
944	flushrs // must be first insn in group
945	srlz.i
946	}
947	;;
948	mov cr.ipsr=r16 // set new PSR
949	add r3=1f-ia64_switch_mode_virt,r15
950
951	mov r14=rp // get return address into a general register
952	;;
953
954	// going to virtual
955	// - for code addresses, set upper bits of addr to KERNEL_START
956	// - for stack addresses, copy from input argument
957	movl r18=KERNEL_START
958	dep r3=0,r3,KERNEL_TR_PAGE_SHIFT,64-KERNEL_TR_PAGE_SHIFT
959	dep r14=0,r14,KERNEL_TR_PAGE_SHIFT,64-KERNEL_TR_PAGE_SHIFT
960	mov sp=r20
961	;;
962	or r3=r3,r18
963	or r14=r14,r18
964	;;
965
966	mov r18=ar.rnat // save ar.rnat
967	mov ar.bspstore=r19 // this steps on ar.rnat
968	mov cr.iip=r3
969	mov cr.ifs=r0
970	;;
971	mov ar.rnat=r18 // restore ar.rnat
972	rfi // must be last insn in group
973	;;
974	1: mov rp=r14
975	br.ret.sptk.many rp
976	END(ia64_switch_mode_virt)
977
978	GLOBAL_ENTRY(ia64_delay_loop)
979	.prologue
980	{ nop 0 // work around GAS unwind info generation bug...
981	.save ar.lc,r2
982	mov r2=ar.lc
983	.body
984	;;
985	mov ar.lc=r32
986	}
987	;;
988	// force loop to be 32-byte aligned (GAS bug means we cannot use .align
989	// inside function body without corrupting unwind info).
990	{ nop 0 }
991	1: br.cloop.sptk.few 1b
992	;;
993	mov ar.lc=r2
994	br.ret.sptk.many rp
995	END(ia64_delay_loop)
996
997	#ifndef XEN
998	/*
999	* Return a CPU-local timestamp in nano-seconds. This timestamp is
1000	* NOT synchronized across CPUs its return value must never be
1001	* compared against the values returned on another CPU. The usage in
1002	* kernel/sched.c ensures that.
1003	*
1004	* The return-value of sched_clock() is NOT supposed to wrap-around.
1005	* If it did, it would cause some scheduling hiccups (at the worst).
1006	* Fortunately, with a 64-bit cycle-counter ticking at 100GHz, even
1007	* that would happen only once every 5+ years.
1008	*
1009	* The code below basically calculates:
1010	*
1011	* (ia64_get_itc() * local_cpu_data->nsec_per_cyc) >> IA64_NSEC_PER_CYC_SHIFT
1012	*
1013	* except that the multiplication and the shift are done with 128-bit
1014	* intermediate precision so that we can produce a full 64-bit result.
1015	*/
1016	GLOBAL_ENTRY(sched_clock)
1017	#ifdef XEN
1018	movl r8=THIS_CPU(cpu_info) + IA64_CPUINFO_NSEC_PER_CYC_OFFSET
1019	#else
1020	addl r8=THIS_CPU(cpu_info) + IA64_CPUINFO_NSEC_PER_CYC_OFFSET,r0
1021	#endif
1022	mov.m r9=ar.itc // fetch cycle-counter (35 cyc)
1023	;;
1024	ldf8 f8=[r8]
1025	;;
1026	setf.sig f9=r9 // certain to stall, so issue it _after_ ldf8...
1027	;;
1028	xmpy.lu f10=f9,f8 // calculate low 64 bits of 128-bit product (4 cyc)
1029	xmpy.hu f11=f9,f8 // calculate high 64 bits of 128-bit product
1030	;;
1031	getf.sig r8=f10 // (5 cyc)
1032	getf.sig r9=f11
1033	;;
1034	shrp r8=r9,r8,IA64_NSEC_PER_CYC_SHIFT
1035	br.ret.sptk.many rp
1036	END(sched_clock)
1037
1038	GLOBAL_ENTRY(start_kernel_thread)
1039	.prologue
1040	.save rp, r0 // this is the end of the call-chain
1041	.body
1042	alloc r2 = ar.pfs, 0, 0, 2, 0
1043	mov out0 = r9
1044	mov out1 = r11;;
1045	br.call.sptk.many rp = kernel_thread_helper;;
1046	mov out0 = r8
1047	br.call.sptk.many rp = sys_exit;;
1048	1: br.sptk.few 1b // not reached
1049	END(start_kernel_thread)
1050	#endif /* XEN */
1051
1052	#ifdef CONFIG_IA64_BRL_EMU
1053
1054	/*
1055	* Assembly routines used by brl_emu.c to set preserved register state.
1056	*/
1057
1058	#define SET_REG(reg) \
1059	GLOBAL_ENTRY(ia64_set_##reg); \
1060	alloc r16=ar.pfs,1,0,0,0; \
1061	mov reg=r32; \
1062	;; \
1063	br.ret.sptk.many rp; \
1064	END(ia64_set_##reg)
1065
1066	SET_REG(b1);
1067	SET_REG(b2);
1068	SET_REG(b3);
1069	SET_REG(b4);
1070	SET_REG(b5);
1071
1072	#endif /* CONFIG_IA64_BRL_EMU */
1073
1074	#ifdef CONFIG_SMP
1075	/*
1076	* This routine handles spinlock contention. It uses a non-standard calling
1077	* convention to avoid converting leaf routines into interior routines. Because
1078	* of this special convention, there are several restrictions:
1079	*
1080	* - do not use gp relative variables, this code is called from the kernel
1081	* and from modules, r1 is undefined.
1082	* - do not use stacked registers, the caller owns them.
1083	* - do not use the scratch stack space, the caller owns it.
1084	* - do not use any registers other than the ones listed below
1085	*
1086	* Inputs:
1087	* ar.pfs - saved CFM of caller
1088	* ar.ccv - 0 (and available for use)
1089	* r27 - flags from spin_lock_irqsave or 0. Must be preserved.
1090	* r28 - available for use.
1091	* r29 - available for use.
1092	* r30 - available for use.
1093	* r31 - address of lock, available for use.
1094	* b6 - return address
1095	* p14 - available for use.
1096	* p15 - used to track flag status.
1097	*
1098	* If you patch this code to use more registers, do not forget to update
1099	* the clobber lists for spin_lock() in include/asm-ia64/spinlock.h.
1100	*/
1101
1102	#if __GNUC__ < 3 \|\| (__GNUC__ == 3 && __GNUC_MINOR__ < 3)
1103
1104	GLOBAL_ENTRY(ia64_spinlock_contention_pre3_4)
1105	.prologue
1106	.save ar.pfs, r0 // this code effectively has a zero frame size
1107	.save rp, r28
1108	.body
1109	nop 0
1110	tbit.nz p15,p0=r27,IA64_PSR_I_BIT
1111	.restore sp // pop existing prologue after next insn
1112	mov b6 = r28
1113	.prologue
1114	.save ar.pfs, r0
1115	.altrp b6
1116	.body
1117	;;
1118	(p15) ssm psr.i // reenable interrupts if they were on
1119	// DavidM says that srlz.d is slow and is not required in this case
1120	.wait:
1121	// exponential backoff, kdb, lockmeter etc. go in here
1122	hint @pause
1123	ld4 r30=[r31] // don't use ld4.bias; if it's contended, we won't write the word
1124	nop 0
1125	;;
1126	cmp4.ne p14,p0=r30,r0
1127	(p14) br.cond.sptk.few .wait
1128	(p15) rsm psr.i // disable interrupts if we reenabled them
1129	br.cond.sptk.few b6 // lock is now free, try to acquire
1130	.global ia64_spinlock_contention_pre3_4_end // for kernprof
1131	ia64_spinlock_contention_pre3_4_end:
1132	END(ia64_spinlock_contention_pre3_4)
1133
1134	#else
1135
1136	GLOBAL_ENTRY(ia64_spinlock_contention)
1137	.prologue
1138	.altrp b6
1139	.body
1140	tbit.nz p15,p0=r27,IA64_PSR_I_BIT
1141	;;
1142	.wait:
1143	(p15) ssm psr.i // reenable interrupts if they were on
1144	// DavidM says that srlz.d is slow and is not required in this case
1145	.wait2:
1146	// exponential backoff, kdb, lockmeter etc. go in here
1147	hint @pause
1148	ld4 r30=[r31] // don't use ld4.bias; if it's contended, we won't write the word
1149	;;
1150	cmp4.ne p14,p0=r30,r0
1151	mov r30 = 1
1152	(p14) br.cond.sptk.few .wait2
1153	(p15) rsm psr.i // disable interrupts if we reenabled them
1154	;;
1155	cmpxchg4.acq r30=[r31], r30, ar.ccv
1156	;;
1157	cmp4.ne p14,p0=r0,r30
1158	(p14) br.cond.sptk.few .wait
1159
1160	br.ret.sptk.many b6 // lock is now taken
1161	END(ia64_spinlock_contention)
1162
1163	#endif
1164
1165	#ifdef CONFIG_HOTPLUG_CPU
1166	GLOBAL_ENTRY(ia64_jump_to_sal)
1167	alloc r16=ar.pfs,1,0,0,0;;
1168	rsm psr.i \| psr.ic
1169	{
1170	flushrs
1171	srlz.i
1172	}
1173	tpa r25=in0
1174	movl r18=tlb_purge_done;;
1175	DATA_VA_TO_PA(r18);;
1176	mov b1=r18 // Return location
1177	movl r18=ia64_do_tlb_purge;;
1178	DATA_VA_TO_PA(r18);;
1179	mov b2=r18 // doing tlb_flush work
1180	mov ar.rsc=0 // Put RSE in enforced lazy, LE mode
1181	movl r17=1f;;
1182	DATA_VA_TO_PA(r17);;
1183	mov cr.iip=r17
1184	movl r16=SAL_PSR_BITS_TO_SET;;
1185	mov cr.ipsr=r16
1186	mov cr.ifs=r0;;
1187	rfi;;
1188	1:
1189	/*
1190	* Invalidate all TLB data/inst
1191	*/
1192	br.sptk.many b2;; // jump to tlb purge code
1193
1194	tlb_purge_done:
1195	RESTORE_REGION_REGS(r25, r17,r18,r19);;
1196	RESTORE_REG(b0, r25, r17);;
1197	RESTORE_REG(b1, r25, r17);;
1198	RESTORE_REG(b2, r25, r17);;
1199	RESTORE_REG(b3, r25, r17);;
1200	RESTORE_REG(b4, r25, r17);;
1201	RESTORE_REG(b5, r25, r17);;
1202	ld8 r1=[r25],0x08;;
1203	ld8 r12=[r25],0x08;;
1204	ld8 r13=[r25],0x08;;
1205	RESTORE_REG(ar.fpsr, r25, r17);;
1206	RESTORE_REG(ar.pfs, r25, r17);;
1207	RESTORE_REG(ar.rnat, r25, r17);;
1208	RESTORE_REG(ar.unat, r25, r17);;
1209	RESTORE_REG(ar.bspstore, r25, r17);;
1210	RESTORE_REG(cr.dcr, r25, r17);;
1211	RESTORE_REG(cr.iva, r25, r17);;
1212	RESTORE_REG(cr.pta, r25, r17);;
1213	RESTORE_REG(cr.itv, r25, r17);;
1214	RESTORE_REG(cr.pmv, r25, r17);;
1215	RESTORE_REG(cr.cmcv, r25, r17);;
1216	RESTORE_REG(cr.lrr0, r25, r17);;
1217	RESTORE_REG(cr.lrr1, r25, r17);;
1218	ld8 r4=[r25],0x08;;
1219	ld8 r5=[r25],0x08;;
1220	ld8 r6=[r25],0x08;;
1221	ld8 r7=[r25],0x08;;
1222	ld8 r17=[r25],0x08;;
1223	mov pr=r17,-1;;
1224	RESTORE_REG(ar.lc, r25, r17);;
1225	/*
1226	* Now Restore floating point regs
1227	*/
1228	ldf.fill.nta f2=[r25],16;;
1229	ldf.fill.nta f3=[r25],16;;
1230	ldf.fill.nta f4=[r25],16;;
1231	ldf.fill.nta f5=[r25],16;;
1232	ldf.fill.nta f16=[r25],16;;
1233	ldf.fill.nta f17=[r25],16;;
1234	ldf.fill.nta f18=[r25],16;;
1235	ldf.fill.nta f19=[r25],16;;
1236	ldf.fill.nta f20=[r25],16;;
1237	ldf.fill.nta f21=[r25],16;;
1238	ldf.fill.nta f22=[r25],16;;
1239	ldf.fill.nta f23=[r25],16;;
1240	ldf.fill.nta f24=[r25],16;;
1241	ldf.fill.nta f25=[r25],16;;
1242	ldf.fill.nta f26=[r25],16;;
1243	ldf.fill.nta f27=[r25],16;;
1244	ldf.fill.nta f28=[r25],16;;
1245	ldf.fill.nta f29=[r25],16;;
1246	ldf.fill.nta f30=[r25],16;;
1247	ldf.fill.nta f31=[r25],16;;
1248
1249	/*
1250	* Now that we have done all the register restores
1251	* we are now ready for the big DIVE to SAL Land
1252	*/
1253	ssm psr.ic;;
1254	srlz.d;;
1255	br.ret.sptk.many b0;;
1256	END(ia64_jump_to_sal)
1257	#endif /* CONFIG_HOTPLUG_CPU */
1258
1259	#endif /* CONFIG_SMP */

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