1 | /* |
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2 | * i386 virtual CPU header |
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3 | * |
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4 | * Copyright (c) 2003 Fabrice Bellard |
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5 | * |
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6 | * This library is free software; you can redistribute it and/or |
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7 | * modify it under the terms of the GNU Lesser General Public |
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8 | * License as published by the Free Software Foundation; either |
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9 | * version 2 of the License, or (at your option) any later version. |
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10 | * |
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11 | * This library is distributed in the hope that it will be useful, |
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12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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14 | * Lesser General Public License for more details. |
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15 | * |
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16 | * You should have received a copy of the GNU Lesser General Public |
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17 | * License along with this library; if not, write to the Free Software |
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18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
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19 | */ |
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20 | #ifndef CPU_I386_H |
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21 | #define CPU_I386_H |
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22 | |
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23 | #include "config.h" |
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24 | |
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25 | #ifdef TARGET_X86_64 |
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26 | #define TARGET_LONG_BITS 64 |
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27 | #else |
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28 | #define TARGET_LONG_BITS 32 |
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29 | #endif |
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30 | |
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31 | /* target supports implicit self modifying code */ |
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32 | #define TARGET_HAS_SMC |
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33 | /* support for self modifying code even if the modified instruction is |
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34 | close to the modifying instruction */ |
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35 | #define TARGET_HAS_PRECISE_SMC |
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36 | |
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37 | #define TARGET_HAS_ICE 1 |
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38 | |
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39 | #include "cpu-defs.h" |
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40 | |
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41 | #include "softfloat.h" |
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42 | |
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43 | #if defined(__i386__) && !defined(CONFIG_SOFTMMU) |
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44 | #define USE_CODE_COPY |
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45 | #endif |
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46 | |
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47 | #define R_EAX 0 |
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48 | #define R_ECX 1 |
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49 | #define R_EDX 2 |
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50 | #define R_EBX 3 |
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51 | #define R_ESP 4 |
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52 | #define R_EBP 5 |
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53 | #define R_ESI 6 |
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54 | #define R_EDI 7 |
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55 | |
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56 | #define R_AL 0 |
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57 | #define R_CL 1 |
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58 | #define R_DL 2 |
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59 | #define R_BL 3 |
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60 | #define R_AH 4 |
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61 | #define R_CH 5 |
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62 | #define R_DH 6 |
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63 | #define R_BH 7 |
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64 | |
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65 | #define R_ES 0 |
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66 | #define R_CS 1 |
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67 | #define R_SS 2 |
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68 | #define R_DS 3 |
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69 | #define R_FS 4 |
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70 | #define R_GS 5 |
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71 | |
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72 | /* segment descriptor fields */ |
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73 | #define DESC_G_MASK (1 << 23) |
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74 | #define DESC_B_SHIFT 22 |
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75 | #define DESC_B_MASK (1 << DESC_B_SHIFT) |
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76 | #define DESC_L_SHIFT 21 /* x86_64 only : 64 bit code segment */ |
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77 | #define DESC_L_MASK (1 << DESC_L_SHIFT) |
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78 | #define DESC_AVL_MASK (1 << 20) |
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79 | #define DESC_P_MASK (1 << 15) |
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80 | #define DESC_DPL_SHIFT 13 |
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81 | #define DESC_S_MASK (1 << 12) |
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82 | #define DESC_TYPE_SHIFT 8 |
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83 | #define DESC_A_MASK (1 << 8) |
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84 | |
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85 | #define DESC_CS_MASK (1 << 11) /* 1=code segment 0=data segment */ |
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86 | #define DESC_C_MASK (1 << 10) /* code: conforming */ |
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87 | #define DESC_R_MASK (1 << 9) /* code: readable */ |
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88 | |
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89 | #define DESC_E_MASK (1 << 10) /* data: expansion direction */ |
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90 | #define DESC_W_MASK (1 << 9) /* data: writable */ |
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91 | |
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92 | #define DESC_TSS_BUSY_MASK (1 << 9) |
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93 | |
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94 | /* eflags masks */ |
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95 | #define CC_C 0x0001 |
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96 | #define CC_P 0x0004 |
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97 | #define CC_A 0x0010 |
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98 | #define CC_Z 0x0040 |
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99 | #define CC_S 0x0080 |
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100 | #define CC_O 0x0800 |
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101 | |
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102 | #define TF_SHIFT 8 |
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103 | #define IOPL_SHIFT 12 |
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104 | #define VM_SHIFT 17 |
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105 | |
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106 | #define TF_MASK 0x00000100 |
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107 | #define IF_MASK 0x00000200 |
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108 | #define DF_MASK 0x00000400 |
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109 | #define IOPL_MASK 0x00003000 |
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110 | #define NT_MASK 0x00004000 |
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111 | #define RF_MASK 0x00010000 |
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112 | #define VM_MASK 0x00020000 |
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113 | #define AC_MASK 0x00040000 |
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114 | #define VIF_MASK 0x00080000 |
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115 | #define VIP_MASK 0x00100000 |
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116 | #define ID_MASK 0x00200000 |
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117 | |
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118 | /* hidden flags - used internally by qemu to represent additionnal cpu |
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119 | states. Only the CPL, INHIBIT_IRQ and HALTED are not redundant. We avoid |
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120 | using the IOPL_MASK, TF_MASK and VM_MASK bit position to ease oring |
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121 | with eflags. */ |
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122 | /* current cpl */ |
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123 | #define HF_CPL_SHIFT 0 |
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124 | /* true if soft mmu is being used */ |
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125 | #define HF_SOFTMMU_SHIFT 2 |
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126 | /* true if hardware interrupts must be disabled for next instruction */ |
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127 | #define HF_INHIBIT_IRQ_SHIFT 3 |
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128 | /* 16 or 32 segments */ |
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129 | #define HF_CS32_SHIFT 4 |
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130 | #define HF_SS32_SHIFT 5 |
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131 | /* zero base for DS, ES and SS : can be '0' only in 32 bit CS segment */ |
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132 | #define HF_ADDSEG_SHIFT 6 |
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133 | /* copy of CR0.PE (protected mode) */ |
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134 | #define HF_PE_SHIFT 7 |
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135 | #define HF_TF_SHIFT 8 /* must be same as eflags */ |
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136 | #define HF_MP_SHIFT 9 /* the order must be MP, EM, TS */ |
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137 | #define HF_EM_SHIFT 10 |
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138 | #define HF_TS_SHIFT 11 |
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139 | #define HF_IOPL_SHIFT 12 /* must be same as eflags */ |
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140 | #define HF_LMA_SHIFT 14 /* only used on x86_64: long mode active */ |
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141 | #define HF_CS64_SHIFT 15 /* only used on x86_64: 64 bit code segment */ |
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142 | #define HF_OSFXSR_SHIFT 16 /* CR4.OSFXSR */ |
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143 | #define HF_VM_SHIFT 17 /* must be same as eflags */ |
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144 | #define HF_HALTED_SHIFT 18 /* CPU halted */ |
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145 | |
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146 | #define HF_CPL_MASK (3 << HF_CPL_SHIFT) |
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147 | #define HF_SOFTMMU_MASK (1 << HF_SOFTMMU_SHIFT) |
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148 | #define HF_INHIBIT_IRQ_MASK (1 << HF_INHIBIT_IRQ_SHIFT) |
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149 | #define HF_CS32_MASK (1 << HF_CS32_SHIFT) |
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150 | #define HF_SS32_MASK (1 << HF_SS32_SHIFT) |
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151 | #define HF_ADDSEG_MASK (1 << HF_ADDSEG_SHIFT) |
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152 | #define HF_PE_MASK (1 << HF_PE_SHIFT) |
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153 | #define HF_TF_MASK (1 << HF_TF_SHIFT) |
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154 | #define HF_MP_MASK (1 << HF_MP_SHIFT) |
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155 | #define HF_EM_MASK (1 << HF_EM_SHIFT) |
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156 | #define HF_TS_MASK (1 << HF_TS_SHIFT) |
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157 | #define HF_LMA_MASK (1 << HF_LMA_SHIFT) |
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158 | #define HF_CS64_MASK (1 << HF_CS64_SHIFT) |
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159 | #define HF_OSFXSR_MASK (1 << HF_OSFXSR_SHIFT) |
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160 | #define HF_HALTED_MASK (1 << HF_HALTED_SHIFT) |
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161 | |
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162 | #define CR0_PE_MASK (1 << 0) |
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163 | #define CR0_MP_MASK (1 << 1) |
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164 | #define CR0_EM_MASK (1 << 2) |
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165 | #define CR0_TS_MASK (1 << 3) |
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166 | #define CR0_ET_MASK (1 << 4) |
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167 | #define CR0_NE_MASK (1 << 5) |
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168 | #define CR0_WP_MASK (1 << 16) |
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169 | #define CR0_AM_MASK (1 << 18) |
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170 | #define CR0_PG_MASK (1 << 31) |
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171 | |
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172 | #define CR4_VME_MASK (1 << 0) |
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173 | #define CR4_PVI_MASK (1 << 1) |
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174 | #define CR4_TSD_MASK (1 << 2) |
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175 | #define CR4_DE_MASK (1 << 3) |
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176 | #define CR4_PSE_MASK (1 << 4) |
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177 | #define CR4_PAE_MASK (1 << 5) |
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178 | #define CR4_PGE_MASK (1 << 7) |
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179 | #define CR4_PCE_MASK (1 << 8) |
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180 | #define CR4_OSFXSR_MASK (1 << 9) |
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181 | #define CR4_OSXMMEXCPT_MASK (1 << 10) |
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182 | |
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183 | #define PG_PRESENT_BIT 0 |
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184 | #define PG_RW_BIT 1 |
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185 | #define PG_USER_BIT 2 |
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186 | #define PG_PWT_BIT 3 |
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187 | #define PG_PCD_BIT 4 |
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188 | #define PG_ACCESSED_BIT 5 |
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189 | #define PG_DIRTY_BIT 6 |
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190 | #define PG_PSE_BIT 7 |
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191 | #define PG_GLOBAL_BIT 8 |
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192 | #define PG_NX_BIT 63 |
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193 | |
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194 | #define PG_PRESENT_MASK (1 << PG_PRESENT_BIT) |
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195 | #define PG_RW_MASK (1 << PG_RW_BIT) |
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196 | #define PG_USER_MASK (1 << PG_USER_BIT) |
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197 | #define PG_PWT_MASK (1 << PG_PWT_BIT) |
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198 | #define PG_PCD_MASK (1 << PG_PCD_BIT) |
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199 | #define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT) |
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200 | #define PG_DIRTY_MASK (1 << PG_DIRTY_BIT) |
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201 | #define PG_PSE_MASK (1 << PG_PSE_BIT) |
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202 | #define PG_GLOBAL_MASK (1 << PG_GLOBAL_BIT) |
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203 | #define PG_NX_MASK (1LL << PG_NX_BIT) |
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204 | |
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205 | #define PG_ERROR_W_BIT 1 |
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206 | |
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207 | #define PG_ERROR_P_MASK 0x01 |
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208 | #define PG_ERROR_W_MASK (1 << PG_ERROR_W_BIT) |
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209 | #define PG_ERROR_U_MASK 0x04 |
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210 | #define PG_ERROR_RSVD_MASK 0x08 |
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211 | #define PG_ERROR_I_D_MASK 0x10 |
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212 | |
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213 | #define MSR_IA32_APICBASE 0x1b |
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214 | #define MSR_IA32_APICBASE_BSP (1<<8) |
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215 | #define MSR_IA32_APICBASE_ENABLE (1<<11) |
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216 | #define MSR_IA32_APICBASE_BASE (0xfffff<<12) |
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217 | |
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218 | #define MSR_IA32_SYSENTER_CS 0x174 |
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219 | #define MSR_IA32_SYSENTER_ESP 0x175 |
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220 | #define MSR_IA32_SYSENTER_EIP 0x176 |
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221 | |
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222 | #define MSR_MCG_CAP 0x179 |
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223 | #define MSR_MCG_STATUS 0x17a |
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224 | #define MSR_MCG_CTL 0x17b |
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225 | |
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226 | #define MSR_PAT 0x277 |
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227 | |
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228 | #define MSR_EFER 0xc0000080 |
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229 | |
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230 | #define MSR_EFER_SCE (1 << 0) |
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231 | #define MSR_EFER_LME (1 << 8) |
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232 | #define MSR_EFER_LMA (1 << 10) |
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233 | #define MSR_EFER_NXE (1 << 11) |
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234 | #define MSR_EFER_FFXSR (1 << 14) |
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235 | |
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236 | #define MSR_STAR 0xc0000081 |
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237 | #define MSR_LSTAR 0xc0000082 |
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238 | #define MSR_CSTAR 0xc0000083 |
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239 | #define MSR_FMASK 0xc0000084 |
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240 | #define MSR_FSBASE 0xc0000100 |
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241 | #define MSR_GSBASE 0xc0000101 |
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242 | #define MSR_KERNELGSBASE 0xc0000102 |
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243 | |
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244 | /* cpuid_features bits */ |
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245 | #define CPUID_FP87 (1 << 0) |
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246 | #define CPUID_VME (1 << 1) |
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247 | #define CPUID_DE (1 << 2) |
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248 | #define CPUID_PSE (1 << 3) |
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249 | #define CPUID_TSC (1 << 4) |
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250 | #define CPUID_MSR (1 << 5) |
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251 | #define CPUID_PAE (1 << 6) |
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252 | #define CPUID_MCE (1 << 7) |
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253 | #define CPUID_CX8 (1 << 8) |
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254 | #define CPUID_APIC (1 << 9) |
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255 | #define CPUID_SEP (1 << 11) /* sysenter/sysexit */ |
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256 | #define CPUID_MTRR (1 << 12) |
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257 | #define CPUID_PGE (1 << 13) |
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258 | #define CPUID_MCA (1 << 14) |
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259 | #define CPUID_CMOV (1 << 15) |
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260 | #define CPUID_PAT (1 << 16) |
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261 | #define CPUID_CLFLUSH (1 << 19) |
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262 | /* ... */ |
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263 | #define CPUID_MMX (1 << 23) |
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264 | #define CPUID_FXSR (1 << 24) |
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265 | #define CPUID_SSE (1 << 25) |
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266 | #define CPUID_SSE2 (1 << 26) |
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267 | |
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268 | #define CPUID_EXT_SSE3 (1 << 0) |
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269 | #define CPUID_EXT_MONITOR (1 << 3) |
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270 | #define CPUID_EXT_CX16 (1 << 13) |
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271 | |
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272 | #define CPUID_EXT2_SYSCALL (1 << 11) |
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273 | #define CPUID_EXT2_NX (1 << 20) |
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274 | #define CPUID_EXT2_FFXSR (1 << 25) |
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275 | #define CPUID_EXT2_LM (1 << 29) |
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276 | |
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277 | #define EXCP00_DIVZ 0 |
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278 | #define EXCP01_SSTP 1 |
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279 | #define EXCP02_NMI 2 |
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280 | #define EXCP03_INT3 3 |
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281 | #define EXCP04_INTO 4 |
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282 | #define EXCP05_BOUND 5 |
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283 | #define EXCP06_ILLOP 6 |
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284 | #define EXCP07_PREX 7 |
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285 | #define EXCP08_DBLE 8 |
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286 | #define EXCP09_XERR 9 |
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287 | #define EXCP0A_TSS 10 |
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288 | #define EXCP0B_NOSEG 11 |
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289 | #define EXCP0C_STACK 12 |
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290 | #define EXCP0D_GPF 13 |
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291 | #define EXCP0E_PAGE 14 |
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292 | #define EXCP10_COPR 16 |
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293 | #define EXCP11_ALGN 17 |
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294 | #define EXCP12_MCHK 18 |
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295 | |
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296 | enum { |
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297 | CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */ |
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298 | CC_OP_EFLAGS, /* all cc are explicitely computed, CC_SRC = flags */ |
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299 | |
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300 | CC_OP_MULB, /* modify all flags, C, O = (CC_SRC != 0) */ |
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301 | CC_OP_MULW, |
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302 | CC_OP_MULL, |
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303 | CC_OP_MULQ, |
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304 | |
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305 | CC_OP_ADDB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ |
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306 | CC_OP_ADDW, |
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307 | CC_OP_ADDL, |
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308 | CC_OP_ADDQ, |
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309 | |
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310 | CC_OP_ADCB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ |
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311 | CC_OP_ADCW, |
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312 | CC_OP_ADCL, |
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313 | CC_OP_ADCQ, |
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314 | |
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315 | CC_OP_SUBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ |
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316 | CC_OP_SUBW, |
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317 | CC_OP_SUBL, |
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318 | CC_OP_SUBQ, |
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319 | |
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320 | CC_OP_SBBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ |
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321 | CC_OP_SBBW, |
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322 | CC_OP_SBBL, |
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323 | CC_OP_SBBQ, |
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324 | |
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325 | CC_OP_LOGICB, /* modify all flags, CC_DST = res */ |
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326 | CC_OP_LOGICW, |
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327 | CC_OP_LOGICL, |
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328 | CC_OP_LOGICQ, |
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329 | |
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330 | CC_OP_INCB, /* modify all flags except, CC_DST = res, CC_SRC = C */ |
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331 | CC_OP_INCW, |
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332 | CC_OP_INCL, |
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333 | CC_OP_INCQ, |
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334 | |
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335 | CC_OP_DECB, /* modify all flags except, CC_DST = res, CC_SRC = C */ |
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336 | CC_OP_DECW, |
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337 | CC_OP_DECL, |
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338 | CC_OP_DECQ, |
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339 | |
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340 | CC_OP_SHLB, /* modify all flags, CC_DST = res, CC_SRC.msb = C */ |
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341 | CC_OP_SHLW, |
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342 | CC_OP_SHLL, |
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343 | CC_OP_SHLQ, |
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344 | |
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345 | CC_OP_SARB, /* modify all flags, CC_DST = res, CC_SRC.lsb = C */ |
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346 | CC_OP_SARW, |
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347 | CC_OP_SARL, |
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348 | CC_OP_SARQ, |
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349 | |
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350 | CC_OP_NB, |
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351 | }; |
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352 | |
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353 | #ifdef FLOATX80 |
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354 | #define USE_X86LDOUBLE |
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355 | #endif |
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356 | |
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357 | #ifdef USE_X86LDOUBLE |
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358 | typedef floatx80 CPU86_LDouble; |
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359 | #else |
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360 | typedef float64 CPU86_LDouble; |
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361 | #endif |
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362 | |
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363 | typedef struct SegmentCache { |
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364 | uint32_t selector; |
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365 | target_ulong base; |
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366 | uint32_t limit; |
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367 | uint32_t flags; |
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368 | } SegmentCache; |
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369 | |
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370 | typedef union { |
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371 | uint8_t _b[16]; |
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372 | uint16_t _w[8]; |
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373 | uint32_t _l[4]; |
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374 | uint64_t _q[2]; |
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375 | float32 _s[4]; |
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376 | float64 _d[2]; |
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377 | } XMMReg; |
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378 | |
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379 | typedef union { |
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380 | uint8_t _b[8]; |
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381 | uint16_t _w[2]; |
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382 | uint32_t _l[1]; |
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383 | uint64_t q; |
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384 | } MMXReg; |
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385 | |
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386 | #ifdef WORDS_BIGENDIAN |
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387 | #define XMM_B(n) _b[15 - (n)] |
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388 | #define XMM_W(n) _w[7 - (n)] |
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389 | #define XMM_L(n) _l[3 - (n)] |
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390 | #define XMM_S(n) _s[3 - (n)] |
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391 | #define XMM_Q(n) _q[1 - (n)] |
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392 | #define XMM_D(n) _d[1 - (n)] |
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393 | |
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394 | #define MMX_B(n) _b[7 - (n)] |
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395 | #define MMX_W(n) _w[3 - (n)] |
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396 | #define MMX_L(n) _l[1 - (n)] |
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397 | #else |
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398 | #define XMM_B(n) _b[n] |
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399 | #define XMM_W(n) _w[n] |
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400 | #define XMM_L(n) _l[n] |
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401 | #define XMM_S(n) _s[n] |
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402 | #define XMM_Q(n) _q[n] |
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403 | #define XMM_D(n) _d[n] |
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404 | |
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405 | #define MMX_B(n) _b[n] |
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406 | #define MMX_W(n) _w[n] |
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407 | #define MMX_L(n) _l[n] |
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408 | #endif |
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409 | #define MMX_Q(n) q |
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410 | |
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411 | #ifdef TARGET_X86_64 |
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412 | #define CPU_NB_REGS 16 |
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413 | #else |
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414 | #define CPU_NB_REGS 8 |
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415 | #endif |
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416 | |
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417 | typedef struct CPUX86State { |
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418 | #if TARGET_LONG_BITS > HOST_LONG_BITS |
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419 | /* temporaries if we cannot store them in host registers */ |
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420 | target_ulong t0, t1, t2; |
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421 | #endif |
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422 | |
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423 | /* standard registers */ |
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424 | target_ulong regs[CPU_NB_REGS]; |
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425 | target_ulong eip; |
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426 | target_ulong eflags; /* eflags register. During CPU emulation, CC |
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427 | flags and DF are set to zero because they are |
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428 | stored elsewhere */ |
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429 | |
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430 | /* emulator internal eflags handling */ |
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431 | target_ulong cc_src; |
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432 | target_ulong cc_dst; |
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433 | uint32_t cc_op; |
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434 | int32_t df; /* D flag : 1 if D = 0, -1 if D = 1 */ |
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435 | uint32_t hflags; /* hidden flags, see HF_xxx constants */ |
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436 | |
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437 | /* segments */ |
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438 | SegmentCache segs[6]; /* selector values */ |
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439 | SegmentCache ldt; |
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440 | SegmentCache tr; |
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441 | SegmentCache gdt; /* only base and limit are used */ |
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442 | SegmentCache idt; /* only base and limit are used */ |
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443 | |
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444 | target_ulong cr[5]; /* NOTE: cr1 is unused */ |
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445 | uint32_t a20_mask; |
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446 | |
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447 | /* FPU state */ |
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448 | unsigned int fpstt; /* top of stack index */ |
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449 | unsigned int fpus; |
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450 | unsigned int fpuc; |
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451 | uint8_t fptags[8]; /* 0 = valid, 1 = empty */ |
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452 | union { |
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453 | #ifdef USE_X86LDOUBLE |
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454 | CPU86_LDouble d __attribute__((aligned(16))); |
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455 | #else |
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456 | CPU86_LDouble d; |
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457 | #endif |
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458 | MMXReg mmx; |
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459 | } fpregs[8]; |
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460 | |
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461 | /* emulator internal variables */ |
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462 | float_status fp_status; |
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463 | CPU86_LDouble ft0; |
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464 | union { |
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465 | float f; |
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466 | double d; |
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467 | int i32; |
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468 | int64_t i64; |
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469 | } fp_convert; |
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470 | |
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471 | float_status sse_status; |
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472 | uint32_t mxcsr; |
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473 | XMMReg xmm_regs[CPU_NB_REGS]; |
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474 | XMMReg xmm_t0; |
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475 | MMXReg mmx_t0; |
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476 | |
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477 | /* sysenter registers */ |
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478 | uint32_t sysenter_cs; |
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479 | uint32_t sysenter_esp; |
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480 | uint32_t sysenter_eip; |
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481 | uint64_t efer; |
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482 | uint64_t star; |
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483 | #ifdef TARGET_X86_64 |
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484 | target_ulong lstar; |
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485 | target_ulong cstar; |
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486 | target_ulong fmask; |
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487 | target_ulong kernelgsbase; |
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488 | #endif |
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489 | |
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490 | uint64_t pat; |
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491 | |
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492 | /* temporary data for USE_CODE_COPY mode */ |
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493 | #ifdef USE_CODE_COPY |
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494 | uint32_t tmp0; |
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495 | uint32_t saved_esp; |
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496 | int native_fp_regs; /* if true, the FPU state is in the native CPU regs */ |
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497 | #endif |
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498 | |
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499 | /* exception/interrupt handling */ |
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500 | jmp_buf jmp_env; |
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501 | int exception_index; |
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502 | int error_code; |
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503 | int exception_is_int; |
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504 | target_ulong exception_next_eip; |
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505 | target_ulong dr[8]; /* debug registers */ |
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506 | int interrupt_request; |
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507 | int user_mode_only; /* user mode only simulation */ |
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508 | |
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509 | CPU_COMMON |
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510 | |
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511 | /* processor features (e.g. for CPUID insn) */ |
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512 | uint32_t cpuid_level; |
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513 | uint32_t cpuid_vendor1; |
---|
514 | uint32_t cpuid_vendor2; |
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515 | uint32_t cpuid_vendor3; |
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516 | uint32_t cpuid_version; |
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517 | uint32_t cpuid_features; |
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518 | uint32_t cpuid_ext_features; |
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519 | uint32_t cpuid_xlevel; |
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520 | uint32_t cpuid_model[12]; |
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521 | uint32_t cpuid_ext2_features; |
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522 | |
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523 | #ifdef USE_KQEMU |
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524 | int kqemu_enabled; |
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525 | int last_io_time; |
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526 | #endif |
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527 | /* in order to simplify APIC support, we leave this pointer to the |
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528 | user */ |
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529 | struct APICState *apic_state; |
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530 | } CPUX86State; |
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531 | |
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532 | CPUX86State *cpu_x86_init(void); |
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533 | int cpu_x86_exec(CPUX86State *s); |
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534 | void cpu_x86_close(CPUX86State *s); |
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535 | int cpu_get_pic_interrupt(CPUX86State *s); |
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536 | /* MSDOS compatibility mode FPU exception support */ |
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537 | void cpu_set_ferr(CPUX86State *s); |
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538 | |
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539 | /* this function must always be used to load data in the segment |
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540 | cache: it synchronizes the hflags with the segment cache values */ |
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541 | static inline void cpu_x86_load_seg_cache(CPUX86State *env, |
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542 | int seg_reg, unsigned int selector, |
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543 | uint32_t base, unsigned int limit, |
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544 | unsigned int flags) |
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545 | { |
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546 | SegmentCache *sc; |
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547 | unsigned int new_hflags; |
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548 | |
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549 | sc = &env->segs[seg_reg]; |
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550 | sc->selector = selector; |
---|
551 | sc->base = base; |
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552 | sc->limit = limit; |
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553 | sc->flags = flags; |
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554 | |
---|
555 | /* update the hidden flags */ |
---|
556 | { |
---|
557 | if (seg_reg == R_CS) { |
---|
558 | #ifdef TARGET_X86_64 |
---|
559 | if ((env->hflags & HF_LMA_MASK) && (flags & DESC_L_MASK)) { |
---|
560 | /* long mode */ |
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561 | env->hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK; |
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562 | env->hflags &= ~(HF_ADDSEG_MASK); |
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563 | } else |
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564 | #endif |
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565 | { |
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566 | /* legacy / compatibility case */ |
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567 | new_hflags = (env->segs[R_CS].flags & DESC_B_MASK) |
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568 | >> (DESC_B_SHIFT - HF_CS32_SHIFT); |
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569 | env->hflags = (env->hflags & ~(HF_CS32_MASK | HF_CS64_MASK)) | |
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570 | new_hflags; |
---|
571 | } |
---|
572 | } |
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573 | new_hflags = (env->segs[R_SS].flags & DESC_B_MASK) |
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574 | >> (DESC_B_SHIFT - HF_SS32_SHIFT); |
---|
575 | if (env->hflags & HF_CS64_MASK) { |
---|
576 | /* zero base assumed for DS, ES and SS in long mode */ |
---|
577 | } else if (!(env->cr[0] & CR0_PE_MASK) || |
---|
578 | (env->eflags & VM_MASK) || |
---|
579 | !(env->hflags & HF_CS32_MASK)) { |
---|
580 | /* XXX: try to avoid this test. The problem comes from the |
---|
581 | fact that is real mode or vm86 mode we only modify the |
---|
582 | 'base' and 'selector' fields of the segment cache to go |
---|
583 | faster. A solution may be to force addseg to one in |
---|
584 | translate-i386.c. */ |
---|
585 | new_hflags |= HF_ADDSEG_MASK; |
---|
586 | } else { |
---|
587 | new_hflags |= ((env->segs[R_DS].base | |
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588 | env->segs[R_ES].base | |
---|
589 | env->segs[R_SS].base) != 0) << |
---|
590 | HF_ADDSEG_SHIFT; |
---|
591 | } |
---|
592 | env->hflags = (env->hflags & |
---|
593 | ~(HF_SS32_MASK | HF_ADDSEG_MASK)) | new_hflags; |
---|
594 | } |
---|
595 | } |
---|
596 | |
---|
597 | /* wrapper, just in case memory mappings must be changed */ |
---|
598 | static inline void cpu_x86_set_cpl(CPUX86State *s, int cpl) |
---|
599 | { |
---|
600 | #if HF_CPL_MASK == 3 |
---|
601 | s->hflags = (s->hflags & ~HF_CPL_MASK) | cpl; |
---|
602 | #else |
---|
603 | #error HF_CPL_MASK is hardcoded |
---|
604 | #endif |
---|
605 | } |
---|
606 | |
---|
607 | /* used for debug or cpu save/restore */ |
---|
608 | void cpu_get_fp80(uint64_t *pmant, uint16_t *pexp, CPU86_LDouble f); |
---|
609 | CPU86_LDouble cpu_set_fp80(uint64_t mant, uint16_t upper); |
---|
610 | |
---|
611 | /* the following helpers are only usable in user mode simulation as |
---|
612 | they can trigger unexpected exceptions */ |
---|
613 | void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector); |
---|
614 | void cpu_x86_fsave(CPUX86State *s, uint8_t *ptr, int data32); |
---|
615 | void cpu_x86_frstor(CPUX86State *s, uint8_t *ptr, int data32); |
---|
616 | |
---|
617 | /* you can call this signal handler from your SIGBUS and SIGSEGV |
---|
618 | signal handlers to inform the virtual CPU of exceptions. non zero |
---|
619 | is returned if the signal was handled by the virtual CPU. */ |
---|
620 | struct siginfo; |
---|
621 | int cpu_x86_signal_handler(int host_signum, struct siginfo *info, |
---|
622 | void *puc); |
---|
623 | void cpu_x86_set_a20(CPUX86State *env, int a20_state); |
---|
624 | |
---|
625 | uint64_t cpu_get_tsc(CPUX86State *env); |
---|
626 | |
---|
627 | void cpu_set_apic_base(CPUX86State *env, uint64_t val); |
---|
628 | uint64_t cpu_get_apic_base(CPUX86State *env); |
---|
629 | void cpu_set_apic_tpr(CPUX86State *env, uint8_t val); |
---|
630 | #ifndef NO_CPU_IO_DEFS |
---|
631 | uint8_t cpu_get_apic_tpr(CPUX86State *env); |
---|
632 | #endif |
---|
633 | |
---|
634 | /* will be suppressed */ |
---|
635 | void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0); |
---|
636 | |
---|
637 | /* used to debug */ |
---|
638 | #define X86_DUMP_FPU 0x0001 /* dump FPU state too */ |
---|
639 | #define X86_DUMP_CCOP 0x0002 /* dump qemu flag cache */ |
---|
640 | |
---|
641 | #ifdef USE_KQEMU |
---|
642 | static inline int cpu_get_time_fast(void) |
---|
643 | { |
---|
644 | int low, high; |
---|
645 | asm volatile("rdtsc" : "=a" (low), "=d" (high)); |
---|
646 | return low; |
---|
647 | } |
---|
648 | #endif |
---|
649 | |
---|
650 | #define TARGET_PAGE_BITS 12 |
---|
651 | #include "cpu-all.h" |
---|
652 | |
---|
653 | #endif /* CPU_I386_H */ |
---|