source: trunk/packages/xen-3.1/xen-3.1/tools/ioemu/target-i386/cpu.h @ 34

Last change on this file since 34 was 34, checked in by hartmans, 18 years ago

Add xen and xen-common
File size: 18.3 KB
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1/*
2 * i386 virtual CPU header
3 *
4 *  Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
19 */
20#ifndef CPU_I386_H
21#define CPU_I386_H
22
23#include "config.h"
24
25#ifdef TARGET_X86_64
26#define TARGET_LONG_BITS 64
27#else
28#define TARGET_LONG_BITS 32
29#endif
30
31/* target supports implicit self modifying code */
32#define TARGET_HAS_SMC
33/* support for self modifying code even if the modified instruction is
34   close to the modifying instruction */
35#define TARGET_HAS_PRECISE_SMC
36
37#define TARGET_HAS_ICE 1
38
39#include "cpu-defs.h"
40
41#include "softfloat.h"
42
43#if defined(__i386__) && !defined(CONFIG_SOFTMMU)
44#define USE_CODE_COPY
45#endif
46
47#define R_EAX 0
48#define R_ECX 1
49#define R_EDX 2
50#define R_EBX 3
51#define R_ESP 4
52#define R_EBP 5
53#define R_ESI 6
54#define R_EDI 7
55
56#define R_AL 0
57#define R_CL 1
58#define R_DL 2
59#define R_BL 3
60#define R_AH 4
61#define R_CH 5
62#define R_DH 6
63#define R_BH 7
64
65#define R_ES 0
66#define R_CS 1
67#define R_SS 2
68#define R_DS 3
69#define R_FS 4
70#define R_GS 5
71
72/* segment descriptor fields */
73#define DESC_G_MASK     (1 << 23)
74#define DESC_B_SHIFT    22
75#define DESC_B_MASK     (1 << DESC_B_SHIFT)
76#define DESC_L_SHIFT    21 /* x86_64 only : 64 bit code segment */
77#define DESC_L_MASK     (1 << DESC_L_SHIFT)
78#define DESC_AVL_MASK   (1 << 20)
79#define DESC_P_MASK     (1 << 15)
80#define DESC_DPL_SHIFT  13
81#define DESC_S_MASK     (1 << 12)
82#define DESC_TYPE_SHIFT 8
83#define DESC_A_MASK     (1 << 8)
84
85#define DESC_CS_MASK    (1 << 11) /* 1=code segment 0=data segment */
86#define DESC_C_MASK     (1 << 10) /* code: conforming */
87#define DESC_R_MASK     (1 << 9)  /* code: readable */
88
89#define DESC_E_MASK     (1 << 10) /* data: expansion direction */
90#define DESC_W_MASK     (1 << 9)  /* data: writable */
91
92#define DESC_TSS_BUSY_MASK (1 << 9)
93
94/* eflags masks */
95#define CC_C    0x0001
96#define CC_P    0x0004
97#define CC_A    0x0010
98#define CC_Z    0x0040
99#define CC_S    0x0080
100#define CC_O    0x0800
101
102#define TF_SHIFT   8
103#define IOPL_SHIFT 12
104#define VM_SHIFT   17
105
106#define TF_MASK                 0x00000100
107#define IF_MASK                 0x00000200
108#define DF_MASK                 0x00000400
109#define IOPL_MASK               0x00003000
110#define NT_MASK                 0x00004000
111#define RF_MASK                 0x00010000
112#define VM_MASK                 0x00020000
113#define AC_MASK                 0x00040000
114#define VIF_MASK                0x00080000
115#define VIP_MASK                0x00100000
116#define ID_MASK                 0x00200000
117
118/* hidden flags - used internally by qemu to represent additionnal cpu
119   states. Only the CPL, INHIBIT_IRQ and HALTED are not redundant. We avoid
120   using the IOPL_MASK, TF_MASK and VM_MASK bit position to ease oring
121   with eflags. */
122/* current cpl */
123#define HF_CPL_SHIFT         0
124/* true if soft mmu is being used */
125#define HF_SOFTMMU_SHIFT     2
126/* true if hardware interrupts must be disabled for next instruction */
127#define HF_INHIBIT_IRQ_SHIFT 3
128/* 16 or 32 segments */
129#define HF_CS32_SHIFT        4
130#define HF_SS32_SHIFT        5
131/* zero base for DS, ES and SS : can be '0' only in 32 bit CS segment */
132#define HF_ADDSEG_SHIFT      6
133/* copy of CR0.PE (protected mode) */
134#define HF_PE_SHIFT          7
135#define HF_TF_SHIFT          8 /* must be same as eflags */
136#define HF_MP_SHIFT          9 /* the order must be MP, EM, TS */
137#define HF_EM_SHIFT         10
138#define HF_TS_SHIFT         11
139#define HF_IOPL_SHIFT       12 /* must be same as eflags */
140#define HF_LMA_SHIFT        14 /* only used on x86_64: long mode active */
141#define HF_CS64_SHIFT       15 /* only used on x86_64: 64 bit code segment  */
142#define HF_OSFXSR_SHIFT     16 /* CR4.OSFXSR */
143#define HF_VM_SHIFT         17 /* must be same as eflags */
144#define HF_HALTED_SHIFT     18 /* CPU halted */
145
146#define HF_CPL_MASK          (3 << HF_CPL_SHIFT)
147#define HF_SOFTMMU_MASK      (1 << HF_SOFTMMU_SHIFT)
148#define HF_INHIBIT_IRQ_MASK  (1 << HF_INHIBIT_IRQ_SHIFT)
149#define HF_CS32_MASK         (1 << HF_CS32_SHIFT)
150#define HF_SS32_MASK         (1 << HF_SS32_SHIFT)
151#define HF_ADDSEG_MASK       (1 << HF_ADDSEG_SHIFT)
152#define HF_PE_MASK           (1 << HF_PE_SHIFT)
153#define HF_TF_MASK           (1 << HF_TF_SHIFT)
154#define HF_MP_MASK           (1 << HF_MP_SHIFT)
155#define HF_EM_MASK           (1 << HF_EM_SHIFT)
156#define HF_TS_MASK           (1 << HF_TS_SHIFT)
157#define HF_LMA_MASK          (1 << HF_LMA_SHIFT)
158#define HF_CS64_MASK         (1 << HF_CS64_SHIFT)
159#define HF_OSFXSR_MASK       (1 << HF_OSFXSR_SHIFT)
160#define HF_HALTED_MASK       (1 << HF_HALTED_SHIFT)
161
162#define CR0_PE_MASK  (1 << 0)
163#define CR0_MP_MASK  (1 << 1)
164#define CR0_EM_MASK  (1 << 2)
165#define CR0_TS_MASK  (1 << 3)
166#define CR0_ET_MASK  (1 << 4)
167#define CR0_NE_MASK  (1 << 5)
168#define CR0_WP_MASK  (1 << 16)
169#define CR0_AM_MASK  (1 << 18)
170#define CR0_PG_MASK  (1 << 31)
171
172#define CR4_VME_MASK  (1 << 0)
173#define CR4_PVI_MASK  (1 << 1)
174#define CR4_TSD_MASK  (1 << 2)
175#define CR4_DE_MASK   (1 << 3)
176#define CR4_PSE_MASK  (1 << 4)
177#define CR4_PAE_MASK  (1 << 5)
178#define CR4_PGE_MASK  (1 << 7)
179#define CR4_PCE_MASK  (1 << 8)
180#define CR4_OSFXSR_MASK (1 << 9)
181#define CR4_OSXMMEXCPT_MASK  (1 << 10)
182
183#define PG_PRESENT_BIT  0
184#define PG_RW_BIT       1
185#define PG_USER_BIT     2
186#define PG_PWT_BIT      3
187#define PG_PCD_BIT      4
188#define PG_ACCESSED_BIT 5
189#define PG_DIRTY_BIT    6
190#define PG_PSE_BIT      7
191#define PG_GLOBAL_BIT   8
192#define PG_NX_BIT       63
193
194#define PG_PRESENT_MASK  (1 << PG_PRESENT_BIT)
195#define PG_RW_MASK       (1 << PG_RW_BIT)
196#define PG_USER_MASK     (1 << PG_USER_BIT)
197#define PG_PWT_MASK      (1 << PG_PWT_BIT)
198#define PG_PCD_MASK      (1 << PG_PCD_BIT)
199#define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT)
200#define PG_DIRTY_MASK    (1 << PG_DIRTY_BIT)
201#define PG_PSE_MASK      (1 << PG_PSE_BIT)
202#define PG_GLOBAL_MASK   (1 << PG_GLOBAL_BIT)
203#define PG_NX_MASK       (1LL << PG_NX_BIT)
204
205#define PG_ERROR_W_BIT     1
206
207#define PG_ERROR_P_MASK    0x01
208#define PG_ERROR_W_MASK    (1 << PG_ERROR_W_BIT)
209#define PG_ERROR_U_MASK    0x04
210#define PG_ERROR_RSVD_MASK 0x08
211#define PG_ERROR_I_D_MASK  0x10
212
213#define MSR_IA32_APICBASE               0x1b
214#define MSR_IA32_APICBASE_BSP           (1<<8)
215#define MSR_IA32_APICBASE_ENABLE        (1<<11)
216#define MSR_IA32_APICBASE_BASE          (0xfffff<<12)
217
218#define MSR_IA32_SYSENTER_CS            0x174
219#define MSR_IA32_SYSENTER_ESP           0x175
220#define MSR_IA32_SYSENTER_EIP           0x176
221
222#define MSR_MCG_CAP                     0x179
223#define MSR_MCG_STATUS                  0x17a
224#define MSR_MCG_CTL                     0x17b
225
226#define MSR_PAT                         0x277
227
228#define MSR_EFER                        0xc0000080
229
230#define MSR_EFER_SCE   (1 << 0)
231#define MSR_EFER_LME   (1 << 8)
232#define MSR_EFER_LMA   (1 << 10)
233#define MSR_EFER_NXE   (1 << 11)
234#define MSR_EFER_FFXSR (1 << 14)
235
236#define MSR_STAR                        0xc0000081
237#define MSR_LSTAR                       0xc0000082
238#define MSR_CSTAR                       0xc0000083
239#define MSR_FMASK                       0xc0000084
240#define MSR_FSBASE                      0xc0000100
241#define MSR_GSBASE                      0xc0000101
242#define MSR_KERNELGSBASE                0xc0000102
243
244/* cpuid_features bits */
245#define CPUID_FP87 (1 << 0)
246#define CPUID_VME  (1 << 1)
247#define CPUID_DE   (1 << 2)
248#define CPUID_PSE  (1 << 3)
249#define CPUID_TSC  (1 << 4)
250#define CPUID_MSR  (1 << 5)
251#define CPUID_PAE  (1 << 6)
252#define CPUID_MCE  (1 << 7)
253#define CPUID_CX8  (1 << 8)
254#define CPUID_APIC (1 << 9)
255#define CPUID_SEP  (1 << 11) /* sysenter/sysexit */
256#define CPUID_MTRR (1 << 12)
257#define CPUID_PGE  (1 << 13)
258#define CPUID_MCA  (1 << 14)
259#define CPUID_CMOV (1 << 15)
260#define CPUID_PAT  (1 << 16)
261#define CPUID_CLFLUSH (1 << 19)
262/* ... */
263#define CPUID_MMX  (1 << 23)
264#define CPUID_FXSR (1 << 24)
265#define CPUID_SSE  (1 << 25)
266#define CPUID_SSE2 (1 << 26)
267
268#define CPUID_EXT_SSE3     (1 << 0)
269#define CPUID_EXT_MONITOR  (1 << 3)
270#define CPUID_EXT_CX16     (1 << 13)
271
272#define CPUID_EXT2_SYSCALL (1 << 11)
273#define CPUID_EXT2_NX      (1 << 20)
274#define CPUID_EXT2_FFXSR   (1 << 25)
275#define CPUID_EXT2_LM      (1 << 29)
276
277#define EXCP00_DIVZ     0
278#define EXCP01_SSTP     1
279#define EXCP02_NMI      2
280#define EXCP03_INT3     3
281#define EXCP04_INTO     4
282#define EXCP05_BOUND    5
283#define EXCP06_ILLOP    6
284#define EXCP07_PREX     7
285#define EXCP08_DBLE     8
286#define EXCP09_XERR     9
287#define EXCP0A_TSS      10
288#define EXCP0B_NOSEG    11
289#define EXCP0C_STACK    12
290#define EXCP0D_GPF      13
291#define EXCP0E_PAGE     14
292#define EXCP10_COPR     16
293#define EXCP11_ALGN     17
294#define EXCP12_MCHK     18
295
296enum {
297    CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */
298    CC_OP_EFLAGS,  /* all cc are explicitely computed, CC_SRC = flags */
299
300    CC_OP_MULB, /* modify all flags, C, O = (CC_SRC != 0) */
301    CC_OP_MULW,
302    CC_OP_MULL,
303    CC_OP_MULQ,
304
305    CC_OP_ADDB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
306    CC_OP_ADDW,
307    CC_OP_ADDL,
308    CC_OP_ADDQ,
309
310    CC_OP_ADCB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
311    CC_OP_ADCW,
312    CC_OP_ADCL,
313    CC_OP_ADCQ,
314
315    CC_OP_SUBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
316    CC_OP_SUBW,
317    CC_OP_SUBL,
318    CC_OP_SUBQ,
319
320    CC_OP_SBBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
321    CC_OP_SBBW,
322    CC_OP_SBBL,
323    CC_OP_SBBQ,
324
325    CC_OP_LOGICB, /* modify all flags, CC_DST = res */
326    CC_OP_LOGICW,
327    CC_OP_LOGICL,
328    CC_OP_LOGICQ,
329
330    CC_OP_INCB, /* modify all flags except, CC_DST = res, CC_SRC = C */
331    CC_OP_INCW,
332    CC_OP_INCL,
333    CC_OP_INCQ,
334
335    CC_OP_DECB, /* modify all flags except, CC_DST = res, CC_SRC = C  */
336    CC_OP_DECW,
337    CC_OP_DECL,
338    CC_OP_DECQ,
339
340    CC_OP_SHLB, /* modify all flags, CC_DST = res, CC_SRC.msb = C */
341    CC_OP_SHLW,
342    CC_OP_SHLL,
343    CC_OP_SHLQ,
344
345    CC_OP_SARB, /* modify all flags, CC_DST = res, CC_SRC.lsb = C */
346    CC_OP_SARW,
347    CC_OP_SARL,
348    CC_OP_SARQ,
349
350    CC_OP_NB,
351};
352
353#ifdef FLOATX80
354#define USE_X86LDOUBLE
355#endif
356
357#ifdef USE_X86LDOUBLE
358typedef floatx80 CPU86_LDouble;
359#else
360typedef float64 CPU86_LDouble;
361#endif
362
363typedef struct SegmentCache {
364    uint32_t selector;
365    target_ulong base;
366    uint32_t limit;
367    uint32_t flags;
368} SegmentCache;
369
370typedef union {
371    uint8_t _b[16];
372    uint16_t _w[8];
373    uint32_t _l[4];
374    uint64_t _q[2];
375    float32 _s[4];
376    float64 _d[2];
377} XMMReg;
378
379typedef union {
380    uint8_t _b[8];
381    uint16_t _w[2];
382    uint32_t _l[1];
383    uint64_t q;
384} MMXReg;
385
386#ifdef WORDS_BIGENDIAN
387#define XMM_B(n) _b[15 - (n)]
388#define XMM_W(n) _w[7 - (n)]
389#define XMM_L(n) _l[3 - (n)]
390#define XMM_S(n) _s[3 - (n)]
391#define XMM_Q(n) _q[1 - (n)]
392#define XMM_D(n) _d[1 - (n)]
393
394#define MMX_B(n) _b[7 - (n)]
395#define MMX_W(n) _w[3 - (n)]
396#define MMX_L(n) _l[1 - (n)]
397#else
398#define XMM_B(n) _b[n]
399#define XMM_W(n) _w[n]
400#define XMM_L(n) _l[n]
401#define XMM_S(n) _s[n]
402#define XMM_Q(n) _q[n]
403#define XMM_D(n) _d[n]
404
405#define MMX_B(n) _b[n]
406#define MMX_W(n) _w[n]
407#define MMX_L(n) _l[n]
408#endif
409#define MMX_Q(n) q
410
411#ifdef TARGET_X86_64
412#define CPU_NB_REGS 16
413#else
414#define CPU_NB_REGS 8
415#endif
416
417typedef struct CPUX86State {
418#if TARGET_LONG_BITS > HOST_LONG_BITS
419    /* temporaries if we cannot store them in host registers */
420    target_ulong t0, t1, t2;
421#endif
422
423    /* standard registers */
424    target_ulong regs[CPU_NB_REGS];
425    target_ulong eip;
426    target_ulong eflags; /* eflags register. During CPU emulation, CC
427                        flags and DF are set to zero because they are
428                        stored elsewhere */
429
430    /* emulator internal eflags handling */
431    target_ulong cc_src;
432    target_ulong cc_dst;
433    uint32_t cc_op;
434    int32_t df; /* D flag : 1 if D = 0, -1 if D = 1 */
435    uint32_t hflags; /* hidden flags, see HF_xxx constants */
436
437    /* segments */
438    SegmentCache segs[6]; /* selector values */
439    SegmentCache ldt;
440    SegmentCache tr;
441    SegmentCache gdt; /* only base and limit are used */
442    SegmentCache idt; /* only base and limit are used */
443
444    target_ulong cr[5]; /* NOTE: cr1 is unused */
445    uint32_t a20_mask;
446
447    /* FPU state */
448    unsigned int fpstt; /* top of stack index */
449    unsigned int fpus;
450    unsigned int fpuc;
451    uint8_t fptags[8];   /* 0 = valid, 1 = empty */
452    union {
453#ifdef USE_X86LDOUBLE
454        CPU86_LDouble d __attribute__((aligned(16)));
455#else
456        CPU86_LDouble d;
457#endif
458        MMXReg mmx;
459    } fpregs[8];
460
461    /* emulator internal variables */
462    float_status fp_status;
463    CPU86_LDouble ft0;
464    union {
465        float f;
466        double d;
467        int i32;
468        int64_t i64;
469    } fp_convert;
470   
471    float_status sse_status;
472    uint32_t mxcsr;
473    XMMReg xmm_regs[CPU_NB_REGS];
474    XMMReg xmm_t0;
475    MMXReg mmx_t0;
476
477    /* sysenter registers */
478    uint32_t sysenter_cs;
479    uint32_t sysenter_esp;
480    uint32_t sysenter_eip;
481    uint64_t efer;
482    uint64_t star;
483#ifdef TARGET_X86_64
484    target_ulong lstar;
485    target_ulong cstar;
486    target_ulong fmask;
487    target_ulong kernelgsbase;
488#endif
489
490    uint64_t pat;
491
492    /* temporary data for USE_CODE_COPY mode */
493#ifdef USE_CODE_COPY
494    uint32_t tmp0;
495    uint32_t saved_esp;
496    int native_fp_regs; /* if true, the FPU state is in the native CPU regs */
497#endif
498   
499    /* exception/interrupt handling */
500    jmp_buf jmp_env;
501    int exception_index;
502    int error_code;
503    int exception_is_int;
504    target_ulong exception_next_eip;
505    target_ulong dr[8]; /* debug registers */
506    int interrupt_request; 
507    int user_mode_only; /* user mode only simulation */
508
509    CPU_COMMON
510
511    /* processor features (e.g. for CPUID insn) */
512    uint32_t cpuid_level;
513    uint32_t cpuid_vendor1;
514    uint32_t cpuid_vendor2;
515    uint32_t cpuid_vendor3;
516    uint32_t cpuid_version;
517    uint32_t cpuid_features;
518    uint32_t cpuid_ext_features;
519    uint32_t cpuid_xlevel;
520    uint32_t cpuid_model[12];
521    uint32_t cpuid_ext2_features;
522   
523#ifdef USE_KQEMU
524    int kqemu_enabled;
525    int last_io_time;
526#endif
527    /* in order to simplify APIC support, we leave this pointer to the
528       user */
529    struct APICState *apic_state;
530} CPUX86State;
531
532CPUX86State *cpu_x86_init(void);
533int cpu_x86_exec(CPUX86State *s);
534void cpu_x86_close(CPUX86State *s);
535int cpu_get_pic_interrupt(CPUX86State *s);
536/* MSDOS compatibility mode FPU exception support */
537void cpu_set_ferr(CPUX86State *s);
538
539/* this function must always be used to load data in the segment
540   cache: it synchronizes the hflags with the segment cache values */
541static inline void cpu_x86_load_seg_cache(CPUX86State *env, 
542                                          int seg_reg, unsigned int selector,
543                                          uint32_t base, unsigned int limit, 
544                                          unsigned int flags)
545{
546    SegmentCache *sc;
547    unsigned int new_hflags;
548   
549    sc = &env->segs[seg_reg];
550    sc->selector = selector;
551    sc->base = base;
552    sc->limit = limit;
553    sc->flags = flags;
554
555    /* update the hidden flags */
556    {
557        if (seg_reg == R_CS) {
558#ifdef TARGET_X86_64
559            if ((env->hflags & HF_LMA_MASK) && (flags & DESC_L_MASK)) {
560                /* long mode */
561                env->hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
562                env->hflags &= ~(HF_ADDSEG_MASK);
563            } else 
564#endif
565            {
566                /* legacy / compatibility case */
567                new_hflags = (env->segs[R_CS].flags & DESC_B_MASK)
568                    >> (DESC_B_SHIFT - HF_CS32_SHIFT);
569                env->hflags = (env->hflags & ~(HF_CS32_MASK | HF_CS64_MASK)) |
570                    new_hflags;
571            }
572        }
573        new_hflags = (env->segs[R_SS].flags & DESC_B_MASK)
574            >> (DESC_B_SHIFT - HF_SS32_SHIFT);
575        if (env->hflags & HF_CS64_MASK) {
576            /* zero base assumed for DS, ES and SS in long mode */
577        } else if (!(env->cr[0] & CR0_PE_MASK) || 
578                   (env->eflags & VM_MASK) ||
579                   !(env->hflags & HF_CS32_MASK)) {
580            /* XXX: try to avoid this test. The problem comes from the
581               fact that is real mode or vm86 mode we only modify the
582               'base' and 'selector' fields of the segment cache to go
583               faster. A solution may be to force addseg to one in
584               translate-i386.c. */
585            new_hflags |= HF_ADDSEG_MASK;
586        } else {
587            new_hflags |= ((env->segs[R_DS].base | 
588                            env->segs[R_ES].base |
589                            env->segs[R_SS].base) != 0) << 
590                HF_ADDSEG_SHIFT;
591        }
592        env->hflags = (env->hflags & 
593                       ~(HF_SS32_MASK | HF_ADDSEG_MASK)) | new_hflags;
594    }
595}
596
597/* wrapper, just in case memory mappings must be changed */
598static inline void cpu_x86_set_cpl(CPUX86State *s, int cpl)
599{
600#if HF_CPL_MASK == 3
601    s->hflags = (s->hflags & ~HF_CPL_MASK) | cpl;
602#else
603#error HF_CPL_MASK is hardcoded
604#endif
605}
606
607/* used for debug or cpu save/restore */
608void cpu_get_fp80(uint64_t *pmant, uint16_t *pexp, CPU86_LDouble f);
609CPU86_LDouble cpu_set_fp80(uint64_t mant, uint16_t upper);
610
611/* the following helpers are only usable in user mode simulation as
612   they can trigger unexpected exceptions */
613void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector);
614void cpu_x86_fsave(CPUX86State *s, uint8_t *ptr, int data32);
615void cpu_x86_frstor(CPUX86State *s, uint8_t *ptr, int data32);
616
617/* you can call this signal handler from your SIGBUS and SIGSEGV
618   signal handlers to inform the virtual CPU of exceptions. non zero
619   is returned if the signal was handled by the virtual CPU.  */
620struct siginfo;
621int cpu_x86_signal_handler(int host_signum, struct siginfo *info, 
622                           void *puc);
623void cpu_x86_set_a20(CPUX86State *env, int a20_state);
624
625uint64_t cpu_get_tsc(CPUX86State *env);
626
627void cpu_set_apic_base(CPUX86State *env, uint64_t val);
628uint64_t cpu_get_apic_base(CPUX86State *env);
629void cpu_set_apic_tpr(CPUX86State *env, uint8_t val);
630#ifndef NO_CPU_IO_DEFS
631uint8_t cpu_get_apic_tpr(CPUX86State *env);
632#endif
633
634/* will be suppressed */
635void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0);
636
637/* used to debug */
638#define X86_DUMP_FPU  0x0001 /* dump FPU state too */
639#define X86_DUMP_CCOP 0x0002 /* dump qemu flag cache */
640
641#ifdef USE_KQEMU
642static inline int cpu_get_time_fast(void)
643{
644    int low, high;
645    asm volatile("rdtsc" : "=a" (low), "=d" (high));
646    return low;
647}
648#endif
649
650#define TARGET_PAGE_BITS 12
651#include "cpu-all.h"
652
653#endif /* CPU_I386_H */
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