1 | /* |
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2 | * virtual page mapping and translated block handling |
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3 | * |
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4 | * Copyright (c) 2003 Fabrice Bellard |
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5 | * |
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6 | * This library is free software; you can redistribute it and/or |
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7 | * modify it under the terms of the GNU Lesser General Public |
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8 | * License as published by the Free Software Foundation; either |
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9 | * version 2 of the License, or (at your option) any later version. |
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10 | * |
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11 | * This library is distributed in the hope that it will be useful, |
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12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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14 | * Lesser General Public License for more details. |
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15 | * |
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16 | * You should have received a copy of the GNU Lesser General Public |
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17 | * License along with this library; if not, write to the Free Software |
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18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
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19 | */ |
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20 | #include "config.h" |
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21 | #ifdef _WIN32 |
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22 | #include <windows.h> |
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23 | #else |
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24 | #include <sys/types.h> |
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25 | #include <sys/mman.h> |
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26 | #endif |
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27 | #include <stdlib.h> |
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28 | #include <stdio.h> |
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29 | #include <stdarg.h> |
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30 | #include <string.h> |
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31 | #include <errno.h> |
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32 | #include <unistd.h> |
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33 | #include <inttypes.h> |
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34 | |
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35 | #include <xen/hvm/e820.h> |
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36 | |
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37 | #include "cpu.h" |
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38 | #include "exec-all.h" |
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39 | #include "vl.h" |
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40 | |
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41 | //#define DEBUG_TB_INVALIDATE |
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42 | //#define DEBUG_FLUSH |
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43 | //#define DEBUG_TLB |
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44 | |
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45 | /* make various TB consistency checks */ |
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46 | //#define DEBUG_TB_CHECK |
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47 | //#define DEBUG_TLB_CHECK |
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48 | |
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49 | #ifndef CONFIG_DM |
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50 | /* threshold to flush the translated code buffer */ |
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51 | #define CODE_GEN_BUFFER_MAX_SIZE (CODE_GEN_BUFFER_SIZE - CODE_GEN_MAX_SIZE) |
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52 | |
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53 | #define SMC_BITMAP_USE_THRESHOLD 10 |
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54 | |
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55 | #define MMAP_AREA_START 0x00000000 |
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56 | #define MMAP_AREA_END 0xa8000000 |
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57 | |
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58 | TranslationBlock tbs[CODE_GEN_MAX_BLOCKS]; |
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59 | TranslationBlock *tb_hash[CODE_GEN_HASH_SIZE]; |
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60 | TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE]; |
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61 | int nb_tbs; |
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62 | /* any access to the tbs or the page table must use this lock */ |
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63 | spinlock_t tb_lock = SPIN_LOCK_UNLOCKED; |
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64 | |
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65 | uint8_t code_gen_buffer[CODE_GEN_BUFFER_SIZE]; |
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66 | uint8_t *code_gen_ptr; |
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67 | #endif /* !CONFIG_DM */ |
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68 | |
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69 | uint64_t phys_ram_size; |
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70 | extern uint64_t ram_size; |
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71 | int phys_ram_fd; |
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72 | uint8_t *phys_ram_base; |
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73 | uint8_t *phys_ram_dirty; |
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74 | |
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75 | CPUState *first_cpu; |
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76 | /* current CPU in the current thread. It is only valid inside |
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77 | cpu_exec() */ |
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78 | CPUState *cpu_single_env; |
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79 | |
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80 | typedef struct PageDesc { |
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81 | /* list of TBs intersecting this ram page */ |
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82 | TranslationBlock *first_tb; |
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83 | /* in order to optimize self modifying code, we count the number |
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84 | of lookups we do to a given page to use a bitmap */ |
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85 | unsigned int code_write_count; |
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86 | uint8_t *code_bitmap; |
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87 | #if defined(CONFIG_USER_ONLY) |
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88 | unsigned long flags; |
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89 | #endif |
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90 | } PageDesc; |
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91 | |
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92 | typedef struct PhysPageDesc { |
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93 | /* offset in host memory of the page + io_index in the low 12 bits */ |
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94 | unsigned long phys_offset; |
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95 | } PhysPageDesc; |
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96 | |
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97 | typedef struct VirtPageDesc { |
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98 | /* physical address of code page. It is valid only if 'valid_tag' |
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99 | matches 'virt_valid_tag' */ |
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100 | target_ulong phys_addr; |
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101 | unsigned int valid_tag; |
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102 | #if !defined(CONFIG_SOFTMMU) |
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103 | /* original page access rights. It is valid only if 'valid_tag' |
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104 | matches 'virt_valid_tag' */ |
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105 | unsigned int prot; |
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106 | #endif |
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107 | } VirtPageDesc; |
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108 | |
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109 | #define L2_BITS 10 |
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110 | #define L1_BITS (32 - L2_BITS - TARGET_PAGE_BITS) |
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111 | |
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112 | #define L1_SIZE (1 << L1_BITS) |
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113 | #define L2_SIZE (1 << L2_BITS) |
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114 | |
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115 | unsigned long qemu_real_host_page_size; |
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116 | unsigned long qemu_host_page_bits; |
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117 | unsigned long qemu_host_page_size; |
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118 | unsigned long qemu_host_page_mask; |
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119 | |
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120 | /* io memory support */ |
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121 | CPUWriteMemoryFunc *io_mem_write[IO_MEM_NB_ENTRIES][4]; |
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122 | CPUReadMemoryFunc *io_mem_read[IO_MEM_NB_ENTRIES][4]; |
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123 | void *io_mem_opaque[IO_MEM_NB_ENTRIES]; |
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124 | static int io_mem_nb = 1; |
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125 | |
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126 | /* log support */ |
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127 | char *logfilename = "/tmp/qemu.log"; |
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128 | FILE *logfile; |
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129 | int loglevel; |
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130 | |
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131 | #ifdef MAPCACHE |
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132 | pthread_mutex_t mapcache_mutex; |
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133 | #endif |
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134 | |
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135 | void cpu_exec_init(CPUState *env) |
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136 | { |
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137 | CPUState **penv; |
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138 | int cpu_index; |
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139 | #ifdef MAPCACHE |
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140 | pthread_mutexattr_t mxattr; |
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141 | #endif |
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142 | |
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143 | env->next_cpu = NULL; |
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144 | penv = &first_cpu; |
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145 | cpu_index = 0; |
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146 | while (*penv != NULL) { |
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147 | penv = (CPUState **)&(*penv)->next_cpu; |
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148 | cpu_index++; |
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149 | } |
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150 | env->cpu_index = cpu_index; |
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151 | *penv = env; |
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152 | |
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153 | /* alloc dirty bits array */ |
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154 | phys_ram_dirty = qemu_malloc(phys_ram_size >> TARGET_PAGE_BITS); |
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155 | |
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156 | #ifdef MAPCACHE |
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157 | /* setup memory access mutex to protect mapcache */ |
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158 | pthread_mutexattr_init(&mxattr); |
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159 | pthread_mutexattr_settype(&mxattr, PTHREAD_MUTEX_RECURSIVE); |
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160 | pthread_mutex_init(&mapcache_mutex, &mxattr); |
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161 | pthread_mutexattr_destroy(&mxattr); |
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162 | #endif |
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163 | } |
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164 | |
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165 | /* enable or disable low levels log */ |
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166 | void cpu_set_log(int log_flags) |
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167 | { |
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168 | loglevel = log_flags; |
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169 | if (!logfile) { |
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170 | logfile = fopen(logfilename, "w"); |
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171 | if (!logfile) { |
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172 | perror(logfilename); |
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173 | _exit(1); |
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174 | } |
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175 | #if !defined(CONFIG_SOFTMMU) |
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176 | /* must avoid mmap() usage of glibc by setting a buffer "by hand" */ |
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177 | { |
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178 | static uint8_t logfile_buf[4096]; |
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179 | setvbuf(logfile, logfile_buf, _IOLBF, sizeof(logfile_buf)); |
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180 | } |
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181 | #else |
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182 | setvbuf(logfile, NULL, _IOLBF, 0); |
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183 | #endif |
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184 | stdout = logfile; |
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185 | stderr = logfile; |
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186 | } |
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187 | } |
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188 | |
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189 | void cpu_set_log_filename(const char *filename) |
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190 | { |
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191 | logfilename = strdup(filename); |
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192 | } |
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193 | |
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194 | /* mask must never be zero, except for A20 change call */ |
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195 | void cpu_interrupt(CPUState *env, int mask) |
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196 | { |
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197 | env->interrupt_request |= mask; |
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198 | } |
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199 | |
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200 | void cpu_reset_interrupt(CPUState *env, int mask) |
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201 | { |
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202 | env->interrupt_request &= ~mask; |
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203 | } |
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204 | |
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205 | CPULogItem cpu_log_items[] = { |
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206 | { CPU_LOG_TB_OUT_ASM, "out_asm", |
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207 | "show generated host assembly code for each compiled TB" }, |
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208 | { CPU_LOG_TB_IN_ASM, "in_asm", |
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209 | "show target assembly code for each compiled TB" }, |
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210 | { CPU_LOG_TB_OP, "op", |
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211 | "show micro ops for each compiled TB (only usable if 'in_asm' used)" }, |
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212 | #ifdef TARGET_I386 |
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213 | { CPU_LOG_TB_OP_OPT, "op_opt", |
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214 | "show micro ops after optimization for each compiled TB" }, |
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215 | #endif |
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216 | { CPU_LOG_INT, "int", |
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217 | "show interrupts/exceptions in short format" }, |
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218 | { CPU_LOG_EXEC, "exec", |
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219 | "show trace before each executed TB (lots of logs)" }, |
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220 | { CPU_LOG_TB_CPU, "cpu", |
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221 | "show CPU state before bloc translation" }, |
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222 | #ifdef TARGET_I386 |
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223 | { CPU_LOG_PCALL, "pcall", |
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224 | "show protected mode far calls/returns/exceptions" }, |
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225 | #endif |
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226 | #ifdef DEBUG_IOPORT |
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227 | { CPU_LOG_IOPORT, "ioport", |
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228 | "show all i/o ports accesses" }, |
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229 | #endif |
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230 | { 0, NULL, NULL }, |
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231 | }; |
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232 | |
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233 | static int cmp1(const char *s1, int n, const char *s2) |
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234 | { |
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235 | if (strlen(s2) != n) |
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236 | return 0; |
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237 | return memcmp(s1, s2, n) == 0; |
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238 | } |
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239 | |
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240 | /* takes a comma separated list of log masks. Return 0 if error. */ |
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241 | int cpu_str_to_log_mask(const char *str) |
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242 | { |
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243 | CPULogItem *item; |
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244 | int mask; |
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245 | const char *p, *p1; |
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246 | |
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247 | p = str; |
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248 | mask = 0; |
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249 | for(;;) { |
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250 | p1 = strchr(p, ','); |
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251 | if (!p1) |
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252 | p1 = p + strlen(p); |
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253 | if(cmp1(p,p1-p,"all")) { |
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254 | for(item = cpu_log_items; item->mask != 0; item++) { |
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255 | mask |= item->mask; |
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256 | } |
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257 | } else { |
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258 | for(item = cpu_log_items; item->mask != 0; item++) { |
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259 | if (cmp1(p, p1 - p, item->name)) |
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260 | goto found; |
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261 | } |
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262 | return 0; |
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263 | } |
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264 | found: |
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265 | mask |= item->mask; |
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266 | if (*p1 != ',') |
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267 | break; |
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268 | p = p1 + 1; |
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269 | } |
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270 | return mask; |
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271 | } |
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272 | |
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273 | void cpu_abort(CPUState *env, const char *fmt, ...) |
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274 | { |
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275 | va_list ap; |
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276 | |
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277 | va_start(ap, fmt); |
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278 | fprintf(stderr, "qemu: fatal: "); |
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279 | vfprintf(stderr, fmt, ap); |
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280 | fprintf(stderr, "\n"); |
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281 | va_end(ap); |
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282 | abort(); |
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283 | } |
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284 | |
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285 | |
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286 | /* XXX: Simple implementation. Fix later */ |
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287 | #define MAX_MMIO 32 |
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288 | struct mmio_space { |
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289 | target_phys_addr_t start; |
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290 | unsigned long size; |
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291 | unsigned long io_index; |
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292 | } mmio[MAX_MMIO]; |
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293 | unsigned long mmio_cnt; |
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294 | |
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295 | /* register physical memory. 'size' must be a multiple of the target |
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296 | page size. If (phys_offset & ~TARGET_PAGE_MASK) != 0, then it is an |
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297 | io memory page */ |
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298 | void cpu_register_physical_memory(target_phys_addr_t start_addr, |
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299 | unsigned long size, |
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300 | unsigned long phys_offset) |
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301 | { |
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302 | int i; |
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303 | |
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304 | for (i = 0; i < mmio_cnt; i++) { |
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305 | if(mmio[i].start == start_addr) { |
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306 | mmio[i].io_index = phys_offset; |
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307 | mmio[i].size = size; |
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308 | return; |
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309 | } |
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310 | } |
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311 | |
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312 | if (mmio_cnt == MAX_MMIO) { |
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313 | fprintf(logfile, "too many mmio regions\n"); |
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314 | exit(-1); |
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315 | } |
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316 | |
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317 | mmio[mmio_cnt].io_index = phys_offset; |
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318 | mmio[mmio_cnt].start = start_addr; |
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319 | mmio[mmio_cnt++].size = size; |
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320 | } |
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321 | |
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322 | /* mem_read and mem_write are arrays of functions containing the |
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323 | function to access byte (index 0), word (index 1) and dword (index |
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324 | 2). All functions must be supplied. If io_index is non zero, the |
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325 | corresponding io zone is modified. If it is zero, a new io zone is |
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326 | allocated. The return value can be used with |
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327 | cpu_register_physical_memory(). (-1) is returned if error. */ |
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328 | int cpu_register_io_memory(int io_index, |
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329 | CPUReadMemoryFunc **mem_read, |
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330 | CPUWriteMemoryFunc **mem_write, |
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331 | void *opaque) |
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332 | { |
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333 | int i; |
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334 | |
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335 | if (io_index <= 0) { |
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336 | if (io_index >= IO_MEM_NB_ENTRIES) |
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337 | return -1; |
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338 | io_index = io_mem_nb++; |
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339 | } else { |
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340 | if (io_index >= IO_MEM_NB_ENTRIES) |
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341 | return -1; |
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342 | } |
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343 | |
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344 | for(i = 0;i < 3; i++) { |
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345 | io_mem_read[io_index][i] = mem_read[i]; |
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346 | io_mem_write[io_index][i] = mem_write[i]; |
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347 | } |
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348 | io_mem_opaque[io_index] = opaque; |
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349 | return io_index << IO_MEM_SHIFT; |
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350 | } |
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351 | |
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352 | CPUWriteMemoryFunc **cpu_get_io_memory_write(int io_index) |
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353 | { |
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354 | return io_mem_write[io_index >> IO_MEM_SHIFT]; |
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355 | } |
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356 | |
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357 | CPUReadMemoryFunc **cpu_get_io_memory_read(int io_index) |
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358 | { |
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359 | return io_mem_read[io_index >> IO_MEM_SHIFT]; |
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360 | } |
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361 | |
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362 | #ifdef __ia64__ |
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363 | /* IA64 has seperate I/D cache, with coherence maintained by DMA controller. |
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364 | * So to emulate right behavior that guest OS is assumed, we need to flush |
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365 | * I/D cache here. |
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366 | */ |
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367 | static void sync_icache(unsigned long address, int len) |
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368 | { |
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369 | int l; |
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370 | |
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371 | for(l = 0; l < (len + 32); l += 32) |
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372 | __ia64_fc(address + l); |
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373 | |
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374 | ia64_sync_i(); |
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375 | ia64_srlz_i(); |
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376 | } |
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377 | #endif |
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378 | |
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379 | /* physical memory access (slow version, mainly for debug) */ |
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380 | #if defined(CONFIG_USER_ONLY) |
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381 | void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf, |
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382 | int len, int is_write) |
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383 | { |
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384 | int l, flags; |
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385 | target_ulong page; |
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386 | |
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387 | while (len > 0) { |
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388 | page = addr & TARGET_PAGE_MASK; |
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389 | l = (page + TARGET_PAGE_SIZE) - addr; |
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390 | if (l > len) |
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391 | l = len; |
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392 | flags = page_get_flags(page); |
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393 | if (!(flags & PAGE_VALID)) |
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394 | return; |
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395 | if (is_write) { |
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396 | if (!(flags & PAGE_WRITE)) |
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397 | return; |
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398 | memcpy((uint8_t *)addr, buf, len); |
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399 | } else { |
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400 | if (!(flags & PAGE_READ)) |
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401 | return; |
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402 | memcpy(buf, (uint8_t *)addr, len); |
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403 | } |
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404 | len -= l; |
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405 | buf += l; |
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406 | addr += l; |
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407 | } |
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408 | } |
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409 | #else |
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410 | |
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411 | int iomem_index(target_phys_addr_t addr) |
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412 | { |
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413 | int i; |
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414 | |
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415 | for (i = 0; i < mmio_cnt; i++) { |
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416 | unsigned long start, end; |
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417 | |
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418 | start = mmio[i].start; |
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419 | end = mmio[i].start + mmio[i].size; |
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420 | |
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421 | if ((addr >= start) && (addr < end)){ |
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422 | return (mmio[i].io_index >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1); |
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423 | } |
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424 | } |
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425 | return 0; |
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426 | } |
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427 | |
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428 | #if defined(__i386__) || defined(__x86_64__) |
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429 | #define phys_ram_addr(x) (qemu_map_cache(x)) |
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430 | #elif defined(__ia64__) |
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431 | #define phys_ram_addr(x) ((addr < ram_size) ? (phys_ram_base + (x)) : NULL) |
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432 | #endif |
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433 | |
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434 | extern unsigned long *logdirty_bitmap; |
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435 | extern unsigned long logdirty_bitmap_size; |
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436 | |
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437 | void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf, |
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438 | int len, int is_write) |
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439 | { |
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440 | int l, io_index; |
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441 | uint8_t *ptr; |
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442 | uint32_t val; |
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443 | |
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444 | mapcache_lock(); |
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445 | |
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446 | while (len > 0) { |
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447 | /* How much can we copy before the next page boundary? */ |
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448 | l = TARGET_PAGE_SIZE - (addr & ~TARGET_PAGE_MASK); |
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449 | if (l > len) |
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450 | l = len; |
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451 | |
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452 | io_index = iomem_index(addr); |
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453 | if (is_write) { |
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454 | if (io_index) { |
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455 | if (l >= 4 && ((addr & 3) == 0)) { |
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456 | /* 32 bit read access */ |
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457 | val = ldl_raw(buf); |
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458 | io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val); |
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459 | l = 4; |
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460 | } else if (l >= 2 && ((addr & 1) == 0)) { |
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461 | /* 16 bit read access */ |
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462 | val = lduw_raw(buf); |
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463 | io_mem_write[io_index][1](io_mem_opaque[io_index], addr, val); |
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464 | l = 2; |
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465 | } else { |
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466 | /* 8 bit access */ |
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467 | val = ldub_raw(buf); |
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468 | io_mem_write[io_index][0](io_mem_opaque[io_index], addr, val); |
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469 | l = 1; |
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470 | } |
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471 | } else if ((ptr = phys_ram_addr(addr)) != NULL) { |
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472 | /* Writing to RAM */ |
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473 | memcpy(ptr, buf, l); |
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474 | if (logdirty_bitmap != NULL) { |
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475 | /* Record that we have dirtied this frame */ |
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476 | unsigned long pfn = addr >> TARGET_PAGE_BITS; |
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477 | if (pfn / 8 >= logdirty_bitmap_size) { |
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478 | fprintf(logfile, "dirtying pfn %lx >= bitmap " |
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479 | "size %lx\n", pfn, logdirty_bitmap_size * 8); |
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480 | } else { |
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481 | logdirty_bitmap[pfn / HOST_LONG_BITS] |
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482 | |= 1UL << pfn % HOST_LONG_BITS; |
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483 | } |
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484 | } |
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485 | #ifdef __ia64__ |
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486 | sync_icache(ptr, l); |
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487 | #endif |
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488 | } |
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489 | } else { |
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490 | if (io_index) { |
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491 | if (l >= 4 && ((addr & 3) == 0)) { |
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492 | /* 32 bit read access */ |
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493 | val = io_mem_read[io_index][2](io_mem_opaque[io_index], addr); |
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494 | stl_raw(buf, val); |
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495 | l = 4; |
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496 | } else if (l >= 2 && ((addr & 1) == 0)) { |
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497 | /* 16 bit read access */ |
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498 | val = io_mem_read[io_index][1](io_mem_opaque[io_index], addr); |
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499 | stw_raw(buf, val); |
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500 | l = 2; |
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501 | } else { |
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502 | /* 8 bit access */ |
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503 | val = io_mem_read[io_index][0](io_mem_opaque[io_index], addr); |
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504 | stb_raw(buf, val); |
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505 | l = 1; |
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506 | } |
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507 | } else if ((ptr = phys_ram_addr(addr)) != NULL) { |
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508 | /* Reading from RAM */ |
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509 | memcpy(buf, ptr, l); |
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510 | } else { |
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511 | /* Neither RAM nor known MMIO space */ |
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512 | memset(buf, 0xff, len); |
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513 | } |
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514 | } |
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515 | len -= l; |
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516 | buf += l; |
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517 | addr += l; |
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518 | } |
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519 | |
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520 | mapcache_unlock(); |
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521 | } |
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522 | #endif |
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523 | |
---|
524 | /* virtual memory access for debug */ |
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525 | int cpu_memory_rw_debug(CPUState *env, target_ulong addr, |
---|
526 | uint8_t *buf, int len, int is_write) |
---|
527 | { |
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528 | int l; |
---|
529 | target_ulong page, phys_addr; |
---|
530 | |
---|
531 | while (len > 0) { |
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532 | page = addr & TARGET_PAGE_MASK; |
---|
533 | phys_addr = cpu_get_phys_page_debug(env, page); |
---|
534 | /* if no physical page mapped, return an error */ |
---|
535 | if (phys_addr == -1) |
---|
536 | return -1; |
---|
537 | l = (page + TARGET_PAGE_SIZE) - addr; |
---|
538 | if (l > len) |
---|
539 | l = len; |
---|
540 | cpu_physical_memory_rw(phys_addr + (addr & ~TARGET_PAGE_MASK), |
---|
541 | buf, l, is_write); |
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542 | len -= l; |
---|
543 | buf += l; |
---|
544 | addr += l; |
---|
545 | } |
---|
546 | return 0; |
---|
547 | } |
---|
548 | |
---|
549 | void cpu_physical_memory_reset_dirty(ram_addr_t start, ram_addr_t end, |
---|
550 | int dirty_flags) |
---|
551 | { |
---|
552 | unsigned long length; |
---|
553 | int i, mask, len; |
---|
554 | uint8_t *p; |
---|
555 | |
---|
556 | start &= TARGET_PAGE_MASK; |
---|
557 | end = TARGET_PAGE_ALIGN(end); |
---|
558 | |
---|
559 | length = end - start; |
---|
560 | if (length == 0) |
---|
561 | return; |
---|
562 | mask = ~dirty_flags; |
---|
563 | p = phys_ram_dirty + (start >> TARGET_PAGE_BITS); |
---|
564 | len = length >> TARGET_PAGE_BITS; |
---|
565 | for(i = 0; i < len; i++) |
---|
566 | p[i] &= mask; |
---|
567 | |
---|
568 | return; |
---|
569 | } |
---|