1 | # HG changeset patch |
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2 | # User kfraser@localhost.localdomain |
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3 | # Node ID a8d31d5ce2589762c3226185deeca3afca47a698 |
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4 | # Parent b8cc9ffda0a3dc449b026c72c97f78dea2e6f114 |
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5 | [HVM] Move PCI and PCI-ISA bridge setup to hvmloader. |
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6 | Signed-off-by: Keir Fraser <keir@xensource.com> |
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7 | |
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8 | Index: ioemu/target-i386-dm/piix_pci-dm.c |
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9 | =================================================================== |
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10 | --- ioemu.orig/target-i386-dm/piix_pci-dm.c 2006-12-08 18:22:35.000000000 +0000 |
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11 | +++ ioemu/target-i386-dm/piix_pci-dm.c 2006-12-08 18:22:50.000000000 +0000 |
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12 | @@ -84,12 +84,6 @@ |
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13 | |
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14 | static PCIDevice *piix3_dev; |
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15 | |
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16 | -static int pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num) |
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17 | -{ |
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18 | - /* This is the barber's pole mapping used by Xen. */ |
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19 | - return (irq_num + (pci_dev->devfn >> 3)) & 3; |
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20 | -} |
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21 | - |
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22 | static void piix3_write_config(PCIDevice *d, |
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23 | uint32_t address, uint32_t val, int len) |
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24 | { |
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25 | @@ -114,12 +108,9 @@ |
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26 | uint8_t *pci_conf = d->config; |
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27 | |
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28 | pci_conf[0x04] = 0x07; // master, memory and I/O |
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29 | - pci_conf[0x05] = 0x00; |
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30 | - pci_conf[0x06] = 0x00; |
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31 | pci_conf[0x07] = 0x02; // PCI_status_devsel_medium |
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32 | pci_conf[0x4c] = 0x4d; |
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33 | pci_conf[0x4e] = 0x03; |
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34 | - pci_conf[0x4f] = 0x00; |
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35 | pci_conf[0x60] = 0x80; |
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36 | pci_conf[0x61] = 0x80; |
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37 | pci_conf[0x62] = 0x80; |
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38 | @@ -129,22 +120,9 @@ |
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39 | pci_conf[0x76] = 0x0c; |
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40 | pci_conf[0x77] = 0x0c; |
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41 | pci_conf[0x78] = 0x02; |
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42 | - pci_conf[0x79] = 0x00; |
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43 | - pci_conf[0x80] = 0x00; |
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44 | - pci_conf[0x82] = 0x00; |
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45 | pci_conf[0xa0] = 0x08; |
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46 | pci_conf[0xa0] = 0x08; |
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47 | - pci_conf[0xa2] = 0x00; |
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48 | - pci_conf[0xa3] = 0x00; |
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49 | - pci_conf[0xa4] = 0x00; |
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50 | - pci_conf[0xa5] = 0x00; |
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51 | - pci_conf[0xa6] = 0x00; |
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52 | - pci_conf[0xa7] = 0x00; |
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53 | pci_conf[0xa8] = 0x0f; |
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54 | - pci_conf[0xaa] = 0x00; |
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55 | - pci_conf[0xab] = 0x00; |
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56 | - pci_conf[0xac] = 0x00; |
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57 | - pci_conf[0xae] = 0x00; |
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58 | } |
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59 | |
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60 | int piix3_init(PCIBus *bus) |
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61 | @@ -171,227 +149,4 @@ |
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62 | return d->devfn; |
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63 | } |
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64 | |
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65 | -/***********************************************************/ |
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66 | -/* XXX: the following should be moved to the PC BIOS */ |
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67 | - |
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68 | -static __attribute__((unused)) uint32_t isa_inb(uint32_t addr) |
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69 | -{ |
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70 | - return cpu_inb(NULL, addr); |
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71 | -} |
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72 | - |
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73 | -static void isa_outb(uint32_t val, uint32_t addr) |
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74 | -{ |
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75 | - cpu_outb(NULL, addr, val); |
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76 | -} |
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77 | - |
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78 | -static __attribute__((unused)) uint32_t isa_inw(uint32_t addr) |
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79 | -{ |
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80 | - return cpu_inw(NULL, addr); |
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81 | -} |
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82 | - |
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83 | -static __attribute__((unused)) void isa_outw(uint32_t val, uint32_t addr) |
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84 | -{ |
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85 | - cpu_outw(NULL, addr, val); |
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86 | -} |
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87 | - |
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88 | -static __attribute__((unused)) uint32_t isa_inl(uint32_t addr) |
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89 | -{ |
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90 | - return cpu_inl(NULL, addr); |
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91 | -} |
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92 | - |
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93 | -static __attribute__((unused)) void isa_outl(uint32_t val, uint32_t addr) |
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94 | -{ |
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95 | - cpu_outl(NULL, addr, val); |
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96 | -} |
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97 | - |
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98 | -static uint32_t pci_bios_io_addr; |
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99 | -static uint32_t pci_bios_mem_addr; |
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100 | -/* host irqs corresponding to PCI irqs A-D */ |
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101 | -static uint8_t pci_irqs[4] = { 10, 11, 10, 11 }; |
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102 | - |
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103 | -static void pci_config_writel(PCIDevice *d, uint32_t addr, uint32_t val) |
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104 | -{ |
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105 | - PCIBus *s = d->bus; |
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106 | - addr |= (pci_bus_num(s) << 16) | (d->devfn << 8); |
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107 | - pci_data_write(s, addr, val, 4); |
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108 | -} |
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109 | - |
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110 | -static void pci_config_writew(PCIDevice *d, uint32_t addr, uint32_t val) |
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111 | -{ |
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112 | - PCIBus *s = d->bus; |
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113 | - addr |= (pci_bus_num(s) << 16) | (d->devfn << 8); |
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114 | - pci_data_write(s, addr, val, 2); |
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115 | -} |
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116 | - |
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117 | -static void pci_config_writeb(PCIDevice *d, uint32_t addr, uint32_t val) |
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118 | -{ |
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119 | - PCIBus *s = d->bus; |
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120 | - addr |= (pci_bus_num(s) << 16) | (d->devfn << 8); |
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121 | - pci_data_write(s, addr, val, 1); |
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122 | -} |
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123 | - |
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124 | -static __attribute__((unused)) uint32_t pci_config_readl(PCIDevice *d, uint32_t addr) |
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125 | -{ |
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126 | - PCIBus *s = d->bus; |
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127 | - addr |= (pci_bus_num(s) << 16) | (d->devfn << 8); |
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128 | - return pci_data_read(s, addr, 4); |
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129 | -} |
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130 | - |
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131 | -static uint32_t pci_config_readw(PCIDevice *d, uint32_t addr) |
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132 | -{ |
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133 | - PCIBus *s = d->bus; |
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134 | - addr |= (pci_bus_num(s) << 16) | (d->devfn << 8); |
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135 | - return pci_data_read(s, addr, 2); |
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136 | -} |
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137 | - |
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138 | -static uint32_t pci_config_readb(PCIDevice *d, uint32_t addr) |
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139 | -{ |
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140 | - PCIBus *s = d->bus; |
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141 | - addr |= (pci_bus_num(s) << 16) | (d->devfn << 8); |
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142 | - return pci_data_read(s, addr, 1); |
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143 | -} |
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144 | - |
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145 | -static void pci_set_io_region_addr(PCIDevice *d, int region_num, uint32_t addr) |
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146 | -{ |
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147 | - PCIIORegion *r; |
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148 | - uint16_t cmd; |
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149 | - uint32_t ofs; |
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150 | - |
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151 | - if ( region_num == PCI_ROM_SLOT ) { |
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152 | - ofs = 0x30; |
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153 | - }else{ |
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154 | - ofs = 0x10 + region_num * 4; |
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155 | - } |
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156 | - |
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157 | - pci_config_writel(d, ofs, addr); |
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158 | - r = &d->io_regions[region_num]; |
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159 | - |
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160 | - /* enable memory mappings */ |
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161 | - cmd = pci_config_readw(d, PCI_COMMAND); |
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162 | - if ( region_num == PCI_ROM_SLOT ) |
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163 | - cmd |= 2; |
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164 | - else if (r->type & PCI_ADDRESS_SPACE_IO) |
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165 | - cmd |= 1; |
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166 | - else |
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167 | - cmd |= 2; |
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168 | - pci_config_writew(d, PCI_COMMAND, cmd); |
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169 | -} |
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170 | - |
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171 | -static void pci_bios_init_device(PCIDevice *d) |
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172 | -{ |
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173 | - int class; |
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174 | - PCIIORegion *r; |
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175 | - uint32_t *paddr; |
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176 | - int i, pin, pic_irq, vendor_id, device_id; |
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177 | - |
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178 | - class = pci_config_readw(d, PCI_CLASS_DEVICE); |
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179 | - vendor_id = pci_config_readw(d, PCI_VENDOR_ID); |
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180 | - device_id = pci_config_readw(d, PCI_DEVICE_ID); |
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181 | - switch(class) { |
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182 | - case 0x0101: |
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183 | - if (vendor_id == 0x8086 && device_id == 0x7010) { |
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184 | - /* PIIX3 IDE */ |
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185 | - pci_config_writew(d, 0x40, 0x8000); // enable IDE0 |
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186 | - pci_config_writew(d, 0x42, 0x8000); // enable IDE1 |
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187 | - goto default_map; |
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188 | - } else { |
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189 | - /* IDE: we map it as in ISA mode */ |
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190 | - pci_set_io_region_addr(d, 0, 0x1f0); |
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191 | - pci_set_io_region_addr(d, 1, 0x3f4); |
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192 | - pci_set_io_region_addr(d, 2, 0x170); |
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193 | - pci_set_io_region_addr(d, 3, 0x374); |
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194 | - } |
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195 | - break; |
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196 | - case 0x0680: |
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197 | - if (vendor_id == 0x8086 && device_id == 0x7113) { |
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198 | - /* |
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199 | - * PIIX4 ACPI PM. |
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200 | - * Special device with special PCI config space. No ordinary BARs. |
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201 | - */ |
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202 | - pci_config_writew(d, 0x20, 0x0000); // No smb bus IO enable |
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203 | - pci_config_writew(d, 0x22, 0x0000); |
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204 | - pci_config_writew(d, 0x3c, 0x0009); // Hardcoded IRQ9 |
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205 | - pci_config_writew(d, 0x3d, 0x0001); |
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206 | - } |
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207 | - break; |
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208 | - case 0x0300: |
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209 | - if (vendor_id != 0x1234) |
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210 | - goto default_map; |
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211 | - /* VGA: map frame buffer to default Bochs VBE address */ |
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212 | - pci_set_io_region_addr(d, 0, 0xE0000000); |
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213 | - break; |
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214 | - case 0x0800: |
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215 | - /* PIC */ |
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216 | - vendor_id = pci_config_readw(d, PCI_VENDOR_ID); |
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217 | - device_id = pci_config_readw(d, PCI_DEVICE_ID); |
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218 | - if (vendor_id == 0x1014) { |
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219 | - /* IBM */ |
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220 | - if (device_id == 0x0046 || device_id == 0xFFFF) { |
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221 | - /* MPIC & MPIC2 */ |
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222 | - pci_set_io_region_addr(d, 0, 0x80800000 + 0x00040000); |
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223 | - } |
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224 | - } |
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225 | - break; |
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226 | - case 0xff00: |
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227 | - if (vendor_id == 0x0106b && |
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228 | - (device_id == 0x0017 || device_id == 0x0022)) { |
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229 | - /* macio bridge */ |
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230 | - pci_set_io_region_addr(d, 0, 0x80800000); |
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231 | - } |
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232 | - break; |
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233 | - default: |
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234 | - default_map: |
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235 | - /* default memory mappings */ |
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236 | - for(i = 0; i < PCI_NUM_REGIONS; i++) { |
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237 | - r = &d->io_regions[i]; |
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238 | - if (r->size) { |
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239 | - if (r->type & PCI_ADDRESS_SPACE_IO) |
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240 | - paddr = &pci_bios_io_addr; |
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241 | - else |
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242 | - paddr = &pci_bios_mem_addr; |
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243 | - *paddr = (*paddr + r->size - 1) & ~(r->size - 1); |
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244 | - pci_set_io_region_addr(d, i, *paddr); |
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245 | - *paddr += r->size; |
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246 | - } |
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247 | - } |
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248 | - break; |
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249 | - } |
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250 | - |
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251 | - /* map the interrupt */ |
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252 | - pin = pci_config_readb(d, PCI_INTERRUPT_PIN); |
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253 | - if (pin != 0) { |
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254 | - pin = pci_slot_get_pirq(d, pin - 1); |
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255 | - pic_irq = pci_irqs[pin]; |
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256 | - pci_config_writeb(d, PCI_INTERRUPT_LINE, pic_irq); |
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257 | - } |
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258 | -} |
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259 | - |
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260 | -/* |
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261 | - * This function initializes the PCI devices as a normal PCI BIOS |
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262 | - * would do. It is provided just in case the BIOS has no support for |
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263 | - * PCI. |
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264 | - */ |
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265 | -void pci_bios_init(void) |
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266 | -{ |
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267 | - int i, irq; |
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268 | - uint8_t elcr[2]; |
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269 | - |
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270 | - pci_bios_io_addr = 0xc000; |
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271 | - pci_bios_mem_addr = HVM_BELOW_4G_MMIO_START; |
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272 | - |
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273 | - /* activate IRQ mappings */ |
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274 | - elcr[0] = 0x00; |
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275 | - elcr[1] = 0x00; |
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276 | - for(i = 0; i < 4; i++) { |
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277 | - irq = pci_irqs[i]; |
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278 | - /* set to trigger level */ |
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279 | - elcr[irq >> 3] |= (1 << (irq & 7)); |
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280 | - /* activate irq remapping in PIIX */ |
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281 | - pci_config_writeb(piix3_dev, 0x60 + i, irq); |
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282 | - } |
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283 | - isa_outb(elcr[0], 0x4d0); |
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284 | - isa_outb(elcr[1], 0x4d1); |
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285 | - |
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286 | - pci_for_each_device(pci_bios_init_device); |
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287 | -} |
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288 | - |
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289 | +void pci_bios_init(void) {} |
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