source: trunk/packages/xen-3.1/xen-3.1/tools/ioemu/patches/remove-pci-bridge-setup @ 34

Last change on this file since 34 was 34, checked in by hartmans, 18 years ago

Add xen and xen-common
File size: 8.3 KB
Line 
1# HG changeset patch
2# User kfraser@localhost.localdomain
3# Node ID a8d31d5ce2589762c3226185deeca3afca47a698
4# Parent  b8cc9ffda0a3dc449b026c72c97f78dea2e6f114
5[HVM] Move PCI and PCI-ISA bridge setup to hvmloader.
6Signed-off-by: Keir Fraser <keir@xensource.com>
7
8Index: ioemu/target-i386-dm/piix_pci-dm.c
9===================================================================
10--- ioemu.orig/target-i386-dm/piix_pci-dm.c     2006-12-08 18:22:35.000000000 +0000
11+++ ioemu/target-i386-dm/piix_pci-dm.c  2006-12-08 18:22:50.000000000 +0000
12@@ -84,12 +84,6 @@
13 
14 static PCIDevice *piix3_dev;
15 
16-static int pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num)
17-{
18-    /* This is the barber's pole mapping used by Xen. */
19-    return (irq_num + (pci_dev->devfn >> 3)) & 3;
20-}
21-
22 static void piix3_write_config(PCIDevice *d,
23                                uint32_t address, uint32_t val, int len)
24 {
25@@ -114,12 +108,9 @@
26     uint8_t *pci_conf = d->config;
27 
28     pci_conf[0x04] = 0x07; // master, memory and I/O
29-    pci_conf[0x05] = 0x00;
30-    pci_conf[0x06] = 0x00;
31     pci_conf[0x07] = 0x02; // PCI_status_devsel_medium
32     pci_conf[0x4c] = 0x4d;
33     pci_conf[0x4e] = 0x03;
34-    pci_conf[0x4f] = 0x00;
35     pci_conf[0x60] = 0x80;
36     pci_conf[0x61] = 0x80;
37     pci_conf[0x62] = 0x80;
38@@ -129,22 +120,9 @@
39     pci_conf[0x76] = 0x0c;
40     pci_conf[0x77] = 0x0c;
41     pci_conf[0x78] = 0x02;
42-    pci_conf[0x79] = 0x00;
43-    pci_conf[0x80] = 0x00;
44-    pci_conf[0x82] = 0x00;
45     pci_conf[0xa0] = 0x08;
46     pci_conf[0xa0] = 0x08;
47-    pci_conf[0xa2] = 0x00;
48-    pci_conf[0xa3] = 0x00;
49-    pci_conf[0xa4] = 0x00;
50-    pci_conf[0xa5] = 0x00;
51-    pci_conf[0xa6] = 0x00;
52-    pci_conf[0xa7] = 0x00;
53     pci_conf[0xa8] = 0x0f;
54-    pci_conf[0xaa] = 0x00;
55-    pci_conf[0xab] = 0x00;
56-    pci_conf[0xac] = 0x00;
57-    pci_conf[0xae] = 0x00;
58 }
59 
60 int piix3_init(PCIBus *bus)
61@@ -171,227 +149,4 @@
62     return d->devfn;
63 }
64 
65-/***********************************************************/
66-/* XXX: the following should be moved to the PC BIOS */
67-
68-static __attribute__((unused)) uint32_t isa_inb(uint32_t addr)
69-{
70-    return cpu_inb(NULL, addr);
71-}
72-
73-static void isa_outb(uint32_t val, uint32_t addr)
74-{
75-    cpu_outb(NULL, addr, val);
76-}
77-
78-static __attribute__((unused)) uint32_t isa_inw(uint32_t addr)
79-{
80-    return cpu_inw(NULL, addr);
81-}
82-
83-static __attribute__((unused)) void isa_outw(uint32_t val, uint32_t addr)
84-{
85-    cpu_outw(NULL, addr, val);
86-}
87-
88-static __attribute__((unused)) uint32_t isa_inl(uint32_t addr)
89-{
90-    return cpu_inl(NULL, addr);
91-}
92-
93-static __attribute__((unused)) void isa_outl(uint32_t val, uint32_t addr)
94-{
95-    cpu_outl(NULL, addr, val);
96-}
97-
98-static uint32_t pci_bios_io_addr;
99-static uint32_t pci_bios_mem_addr;
100-/* host irqs corresponding to PCI irqs A-D */
101-static uint8_t pci_irqs[4] = { 10, 11, 10, 11 };
102-
103-static void pci_config_writel(PCIDevice *d, uint32_t addr, uint32_t val)
104-{
105-    PCIBus *s = d->bus;
106-    addr |= (pci_bus_num(s) << 16) | (d->devfn << 8);
107-    pci_data_write(s, addr, val, 4);
108-}
109-
110-static void pci_config_writew(PCIDevice *d, uint32_t addr, uint32_t val)
111-{
112-    PCIBus *s = d->bus;
113-    addr |= (pci_bus_num(s) << 16) | (d->devfn << 8);
114-    pci_data_write(s, addr, val, 2);
115-}
116-
117-static void pci_config_writeb(PCIDevice *d, uint32_t addr, uint32_t val)
118-{
119-    PCIBus *s = d->bus;
120-    addr |= (pci_bus_num(s) << 16) | (d->devfn << 8);
121-    pci_data_write(s, addr, val, 1);
122-}
123-
124-static __attribute__((unused)) uint32_t pci_config_readl(PCIDevice *d, uint32_t addr)
125-{
126-    PCIBus *s = d->bus;
127-    addr |= (pci_bus_num(s) << 16) | (d->devfn << 8);
128-    return pci_data_read(s, addr, 4);
129-}
130-
131-static uint32_t pci_config_readw(PCIDevice *d, uint32_t addr)
132-{
133-    PCIBus *s = d->bus;
134-    addr |= (pci_bus_num(s) << 16) | (d->devfn << 8);
135-    return pci_data_read(s, addr, 2);
136-}
137-
138-static uint32_t pci_config_readb(PCIDevice *d, uint32_t addr)
139-{
140-    PCIBus *s = d->bus;
141-    addr |= (pci_bus_num(s) << 16) | (d->devfn << 8);
142-    return pci_data_read(s, addr, 1);
143-}
144-
145-static void pci_set_io_region_addr(PCIDevice *d, int region_num, uint32_t addr)
146-{
147-    PCIIORegion *r;
148-    uint16_t cmd;
149-    uint32_t ofs;
150-
151-    if ( region_num == PCI_ROM_SLOT ) {
152-        ofs = 0x30;
153-    }else{
154-        ofs = 0x10 + region_num * 4;
155-    }
156-
157-    pci_config_writel(d, ofs, addr);
158-    r = &d->io_regions[region_num];
159-
160-    /* enable memory mappings */
161-    cmd = pci_config_readw(d, PCI_COMMAND);
162-    if ( region_num == PCI_ROM_SLOT )
163-        cmd |= 2;
164-    else if (r->type & PCI_ADDRESS_SPACE_IO)
165-        cmd |= 1;
166-    else
167-        cmd |= 2;
168-    pci_config_writew(d, PCI_COMMAND, cmd);
169-}
170-
171-static void pci_bios_init_device(PCIDevice *d)
172-{
173-    int class;
174-    PCIIORegion *r;
175-    uint32_t *paddr;
176-    int i, pin, pic_irq, vendor_id, device_id;
177-
178-    class = pci_config_readw(d, PCI_CLASS_DEVICE);
179-    vendor_id = pci_config_readw(d, PCI_VENDOR_ID);
180-    device_id = pci_config_readw(d, PCI_DEVICE_ID);
181-    switch(class) {
182-    case 0x0101:
183-        if (vendor_id == 0x8086 && device_id == 0x7010) {
184-            /* PIIX3 IDE */
185-            pci_config_writew(d, 0x40, 0x8000); // enable IDE0
186-            pci_config_writew(d, 0x42, 0x8000); // enable IDE1
187-            goto default_map;
188-        } else {
189-            /* IDE: we map it as in ISA mode */
190-            pci_set_io_region_addr(d, 0, 0x1f0);
191-            pci_set_io_region_addr(d, 1, 0x3f4);
192-            pci_set_io_region_addr(d, 2, 0x170);
193-            pci_set_io_region_addr(d, 3, 0x374);
194-        }
195-        break;
196-    case 0x0680:
197-        if (vendor_id == 0x8086 && device_id == 0x7113) {
198-            /*
199-             * PIIX4 ACPI PM.
200-             * Special device with special PCI config space. No ordinary BARs.
201-             */
202-            pci_config_writew(d, 0x20, 0x0000); // No smb bus IO enable
203-            pci_config_writew(d, 0x22, 0x0000);
204-            pci_config_writew(d, 0x3c, 0x0009); // Hardcoded IRQ9
205-            pci_config_writew(d, 0x3d, 0x0001);
206-        }
207-        break;
208-    case 0x0300:
209-        if (vendor_id != 0x1234)
210-            goto default_map;
211-        /* VGA: map frame buffer to default Bochs VBE address */
212-        pci_set_io_region_addr(d, 0, 0xE0000000);
213-        break;
214-    case 0x0800:
215-        /* PIC */
216-        vendor_id = pci_config_readw(d, PCI_VENDOR_ID);
217-        device_id = pci_config_readw(d, PCI_DEVICE_ID);
218-        if (vendor_id == 0x1014) {
219-            /* IBM */
220-            if (device_id == 0x0046 || device_id == 0xFFFF) {
221-                /* MPIC & MPIC2 */
222-                pci_set_io_region_addr(d, 0, 0x80800000 + 0x00040000);
223-            }
224-        }
225-        break;
226-    case 0xff00:
227-        if (vendor_id == 0x0106b &&
228-            (device_id == 0x0017 || device_id == 0x0022)) {
229-            /* macio bridge */
230-            pci_set_io_region_addr(d, 0, 0x80800000);
231-        }
232-        break;
233-    default:
234-    default_map:
235-        /* default memory mappings */
236-        for(i = 0; i < PCI_NUM_REGIONS; i++) {
237-            r = &d->io_regions[i];
238-            if (r->size) {
239-                if (r->type & PCI_ADDRESS_SPACE_IO)
240-                    paddr = &pci_bios_io_addr;
241-                else
242-                    paddr = &pci_bios_mem_addr;
243-                *paddr = (*paddr + r->size - 1) & ~(r->size - 1);
244-                pci_set_io_region_addr(d, i, *paddr);
245-                *paddr += r->size;
246-            }
247-        }
248-        break;
249-    }
250-
251-    /* map the interrupt */
252-    pin = pci_config_readb(d, PCI_INTERRUPT_PIN);
253-    if (pin != 0) {
254-        pin = pci_slot_get_pirq(d, pin - 1);
255-        pic_irq = pci_irqs[pin];
256-        pci_config_writeb(d, PCI_INTERRUPT_LINE, pic_irq);
257-    }
258-}
259-
260-/*
261- * This function initializes the PCI devices as a normal PCI BIOS
262- * would do. It is provided just in case the BIOS has no support for
263- * PCI.
264- */
265-void pci_bios_init(void)
266-{
267-    int i, irq;
268-    uint8_t elcr[2];
269-
270-    pci_bios_io_addr = 0xc000;
271-    pci_bios_mem_addr = HVM_BELOW_4G_MMIO_START;
272-
273-    /* activate IRQ mappings */
274-    elcr[0] = 0x00;
275-    elcr[1] = 0x00;
276-    for(i = 0; i < 4; i++) {
277-        irq = pci_irqs[i];
278-        /* set to trigger level */
279-        elcr[irq >> 3] |= (1 << (irq & 7));
280-        /* activate irq remapping in PIIX */
281-        pci_config_writeb(piix3_dev, 0x60 + i, irq);
282-    }
283-    isa_outb(elcr[0], 0x4d0);
284-    isa_outb(elcr[1], 0x4d1);
285-
286-    pci_for_each_device(pci_bios_init_device);
287-}
288-
289+void pci_bios_init(void) {}
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