1 | Index: ioemu/hw/iommu.c |
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2 | =================================================================== |
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3 | --- ioemu.orig/hw/iommu.c 2007-05-03 09:56:32.000000000 +0100 |
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4 | +++ ioemu/hw/iommu.c 2007-05-03 10:05:51.000000000 +0100 |
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5 | @@ -82,7 +82,11 @@ |
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6 | #define IOPTE_VALID 0x00000002 /* IOPTE is valid */ |
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7 | #define IOPTE_WAZ 0x00000001 /* Write as zeros */ |
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8 | |
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9 | +#if defined(__i386__) || defined(__x86_64__) |
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10 | #define PAGE_SHIFT 12 |
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11 | +#elif defined(__ia64__) |
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12 | +#define PAGE_SHIFT 14 |
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13 | +#endif |
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14 | #define PAGE_SIZE (1 << PAGE_SHIFT) |
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15 | #define PAGE_MASK (PAGE_SIZE - 1) |
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16 | |
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17 | Index: ioemu/cpu-all.h |
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18 | =================================================================== |
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19 | --- ioemu.orig/cpu-all.h 2007-05-03 09:56:32.000000000 +0100 |
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20 | +++ ioemu/cpu-all.h 2007-05-03 10:05:51.000000000 +0100 |
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21 | @@ -835,6 +835,31 @@ |
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22 | :"=m" (*(volatile long *)addr) |
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23 | :"dIr" (nr)); |
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24 | } |
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25 | +#elif defined(__ia64__) |
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26 | +#include "ia64_intrinsic.h" |
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27 | +#define atomic_set_bit(nr, addr) ({ \ |
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28 | + typeof(*addr) bit, old, new; \ |
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29 | + volatile typeof(*addr) *m; \ |
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30 | + \ |
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31 | + m = (volatile typeof(*addr)*)(addr + nr / (8*sizeof(*addr))); \ |
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32 | + bit = 1 << (nr % (8*sizeof(*addr))); \ |
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33 | + do { \ |
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34 | + old = *m; \ |
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35 | + new = old | bit; \ |
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36 | + } while (cmpxchg_acq(m, old, new) != old); \ |
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37 | +}) |
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38 | + |
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39 | +#define atomic_clear_bit(nr, addr) ({ \ |
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40 | + typeof(*addr) bit, old, new; \ |
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41 | + volatile typeof(*addr) *m; \ |
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42 | + \ |
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43 | + m = (volatile typeof(*addr)*)(addr + nr / (8*sizeof(*addr))); \ |
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44 | + bit = ~(1 << (nr % (8*sizeof(*addr)))); \ |
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45 | + do { \ |
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46 | + old = *m; \ |
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47 | + new = old & bit; \ |
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48 | + } while (cmpxchg_acq(m, old, new) != old); \ |
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49 | +}) |
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50 | #endif |
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51 | |
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52 | /* memory API */ |
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53 | Index: ioemu/vl.c |
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54 | =================================================================== |
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55 | --- ioemu.orig/vl.c 2007-05-03 10:04:06.000000000 +0100 |
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56 | +++ ioemu/vl.c 2007-05-03 10:25:23.000000000 +0100 |
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57 | @@ -6142,6 +6142,11 @@ |
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58 | exit(1); |
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59 | } |
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60 | |
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61 | +#if defined (__ia64__) |
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62 | + if (ram_size > MMIO_START) |
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63 | + ram_size += 1 * MEM_G; /* skip 3G-4G MMIO, LEGACY_IO_SPACE etc. */ |
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64 | +#endif |
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65 | + |
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66 | /* init the memory */ |
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67 | phys_ram_size = ram_size + vga_ram_size + bios_size; |
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68 | |
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69 | @@ -6182,6 +6187,44 @@ |
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70 | |
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71 | free(page_array); |
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72 | |
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73 | +#elif defined(__ia64__) |
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74 | + |
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75 | + nr_pages = ram_size/PAGE_SIZE; |
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76 | + |
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77 | + page_array = (xen_pfn_t *)malloc(nr_pages * sizeof(xen_pfn_t)); |
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78 | + if (page_array == NULL) { |
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79 | + fprintf(logfile, "malloc returned error %d\n", errno); |
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80 | + exit(-1); |
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81 | + } |
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82 | + |
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83 | + shared_page = xc_map_foreign_range(xc_handle, domid, PAGE_SIZE, |
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84 | + PROT_READ|PROT_WRITE, |
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85 | + IO_PAGE_START >> PAGE_SHIFT); |
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86 | + |
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87 | + buffered_io_page =xc_map_foreign_range(xc_handle, domid, PAGE_SIZE, |
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88 | + PROT_READ|PROT_WRITE, |
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89 | + BUFFER_IO_PAGE_START >> PAGE_SHIFT); |
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90 | + |
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91 | + for (i = 0; i < nr_pages; i++) |
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92 | + page_array[i] = i; |
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93 | + |
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94 | + /* VTI will not use memory between 3G~4G, so we just pass a legal pfn |
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95 | + to make QEMU map continuous virtual memory space */ |
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96 | + if (ram_size > MMIO_START) { |
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97 | + for (i = 0 ; i < (MEM_G >> PAGE_SHIFT); i++) |
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98 | + page_array[(MMIO_START >> PAGE_SHIFT) + i] = |
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99 | + (STORE_PAGE_START >> PAGE_SHIFT); |
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100 | + } |
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101 | + |
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102 | + phys_ram_base = xc_map_foreign_batch(xc_handle, domid, |
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103 | + PROT_READ|PROT_WRITE, |
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104 | + page_array, nr_pages); |
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105 | + if (phys_ram_base == 0) { |
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106 | + fprintf(logfile, "xc_map_foreign_batch returned error %d\n", errno); |
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107 | + exit(-1); |
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108 | + } |
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109 | + free(page_array); |
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110 | +#endif |
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111 | #else /* !CONFIG_DM */ |
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112 | |
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113 | phys_ram_base = qemu_vmalloc(phys_ram_size); |
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114 | Index: ioemu/exec-all.h |
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115 | =================================================================== |
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116 | --- ioemu.orig/exec-all.h 2007-05-03 09:56:32.000000000 +0100 |
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117 | +++ ioemu/exec-all.h 2007-05-03 10:05:51.000000000 +0100 |
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118 | @@ -462,12 +462,13 @@ |
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119 | } |
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120 | #endif |
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121 | |
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122 | -#ifdef __ia64 |
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123 | -#include <ia64intrin.h> |
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124 | +#ifdef __ia64__ |
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125 | +#include "ia64_intrinsic.h" |
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126 | |
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127 | static inline int testandset (int *p) |
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128 | { |
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129 | - return __sync_lock_test_and_set (p, 1); |
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130 | + uint32_t o = 0, n = 1; |
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131 | + return (int)cmpxchg_acq(p, o, n); |
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132 | } |
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133 | #endif |
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134 | |
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135 | Index: ioemu/target-i386-dm/cpu.h |
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136 | =================================================================== |
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137 | --- ioemu.orig/target-i386-dm/cpu.h 2007-05-03 09:56:32.000000000 +0100 |
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138 | +++ ioemu/target-i386-dm/cpu.h 2007-05-03 10:25:13.000000000 +0100 |
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139 | @@ -78,7 +78,11 @@ |
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140 | /* helper2.c */ |
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141 | int main_loop(void); |
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142 | |
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143 | +#if defined(__i386__) || defined(__x86_64__) |
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144 | #define TARGET_PAGE_BITS 12 |
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145 | +#elif defined(__ia64__) |
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146 | +#define TARGET_PAGE_BITS 14 |
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147 | +#endif |
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148 | #include "cpu-all.h" |
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149 | |
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150 | #endif /* CPU_I386_H */ |
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151 | Index: ioemu/ia64_intrinsic.h |
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152 | =================================================================== |
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153 | --- /dev/null 1970-01-01 00:00:00.000000000 +0000 |
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154 | +++ ioemu/ia64_intrinsic.h 2007-05-03 10:05:51.000000000 +0100 |
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155 | @@ -0,0 +1,276 @@ |
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156 | +#ifndef IA64_INTRINSIC_H |
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157 | +#define IA64_INTRINSIC_H |
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158 | + |
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159 | +/* |
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160 | + * Compiler-dependent Intrinsics |
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161 | + * |
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162 | + * Copyright (C) 2002,2003 Jun Nakajima <jun.nakajima@intel.com> |
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163 | + * Copyright (C) 2002,2003 Suresh Siddha <suresh.b.siddha@intel.com> |
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164 | + * |
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165 | + */ |
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166 | +extern long ia64_cmpxchg_called_with_bad_pointer (void); |
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167 | +extern void ia64_bad_param_for_getreg (void); |
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168 | +#define ia64_cmpxchg(sem,ptr,o,n,s) ({ \ |
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169 | + uint64_t _o, _r; \ |
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170 | + switch(s) { \ |
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171 | + case 1: _o = (uint8_t)(long)(o); break; \ |
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172 | + case 2: _o = (uint16_t)(long)(o); break; \ |
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173 | + case 4: _o = (uint32_t)(long)(o); break; \ |
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174 | + case 8: _o = (uint64_t)(long)(o); break; \ |
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175 | + default: break; \ |
---|
176 | + } \ |
---|
177 | + switch(s) { \ |
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178 | + case 1: \ |
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179 | + _r = ia64_cmpxchg1_##sem((uint8_t*)ptr,n,_o); break; \ |
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180 | + case 2: \ |
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181 | + _r = ia64_cmpxchg2_##sem((uint16_t*)ptr,n,_o); break; \ |
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182 | + case 4: \ |
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183 | + _r = ia64_cmpxchg4_##sem((uint32_t*)ptr,n,_o); break; \ |
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184 | + case 8: \ |
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185 | + _r = ia64_cmpxchg8_##sem((uint64_t*)ptr,n,_o); break; \ |
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186 | + default: \ |
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187 | + _r = ia64_cmpxchg_called_with_bad_pointer(); break; \ |
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188 | + } \ |
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189 | + (__typeof__(o)) _r; \ |
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190 | +}) |
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191 | + |
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192 | +#define cmpxchg_acq(ptr,o,n) ia64_cmpxchg(acq,ptr,o,n,sizeof(*ptr)) |
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193 | +#define cmpxchg_rel(ptr,o,n) ia64_cmpxchg(rel,ptr,o,n,sizeof(*ptr)) |
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194 | + |
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195 | +/* |
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196 | + * Register Names for getreg() and setreg(). |
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197 | + * |
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198 | + * The "magic" numbers happen to match the values used by the Intel compiler's |
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199 | + * getreg()/setreg() intrinsics. |
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200 | + */ |
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201 | + |
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202 | +/* Special Registers */ |
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203 | + |
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204 | +#define _IA64_REG_IP 1016 /* getreg only */ |
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205 | +#define _IA64_REG_PSR 1019 |
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206 | +#define _IA64_REG_PSR_L 1019 |
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207 | + |
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208 | +/* General Integer Registers */ |
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209 | + |
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210 | +#define _IA64_REG_GP 1025 /* R1 */ |
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211 | +#define _IA64_REG_R8 1032 /* R8 */ |
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212 | +#define _IA64_REG_R9 1033 /* R9 */ |
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213 | +#define _IA64_REG_SP 1036 /* R12 */ |
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214 | +#define _IA64_REG_TP 1037 /* R13 */ |
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215 | + |
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216 | +/* Application Registers */ |
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217 | + |
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218 | +#define _IA64_REG_AR_KR0 3072 |
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219 | +#define _IA64_REG_AR_KR1 3073 |
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220 | +#define _IA64_REG_AR_KR2 3074 |
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221 | +#define _IA64_REG_AR_KR3 3075 |
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222 | +#define _IA64_REG_AR_KR4 3076 |
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223 | +#define _IA64_REG_AR_KR5 3077 |
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224 | +#define _IA64_REG_AR_KR6 3078 |
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225 | +#define _IA64_REG_AR_KR7 3079 |
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226 | +#define _IA64_REG_AR_RSC 3088 |
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227 | +#define _IA64_REG_AR_BSP 3089 |
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228 | +#define _IA64_REG_AR_BSPSTORE 3090 |
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229 | +#define _IA64_REG_AR_RNAT 3091 |
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230 | +#define _IA64_REG_AR_FCR 3093 |
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231 | +#define _IA64_REG_AR_EFLAG 3096 |
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232 | +#define _IA64_REG_AR_CSD 3097 |
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233 | +#define _IA64_REG_AR_SSD 3098 |
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234 | +#define _IA64_REG_AR_CFLAG 3099 |
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235 | +#define _IA64_REG_AR_FSR 3100 |
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236 | +#define _IA64_REG_AR_FIR 3101 |
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237 | +#define _IA64_REG_AR_FDR 3102 |
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238 | +#define _IA64_REG_AR_CCV 3104 |
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239 | +#define _IA64_REG_AR_UNAT 3108 |
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240 | +#define _IA64_REG_AR_FPSR 3112 |
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241 | +#define _IA64_REG_AR_ITC 3116 |
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242 | +#define _IA64_REG_AR_PFS 3136 |
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243 | +#define _IA64_REG_AR_LC 3137 |
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244 | +#define _IA64_REG_AR_EC 3138 |
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245 | + |
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246 | +/* Control Registers */ |
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247 | + |
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248 | +#define _IA64_REG_CR_DCR 4096 |
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249 | +#define _IA64_REG_CR_ITM 4097 |
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250 | +#define _IA64_REG_CR_IVA 4098 |
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251 | +#define _IA64_REG_CR_PTA 4104 |
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252 | +#define _IA64_REG_CR_IPSR 4112 |
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253 | +#define _IA64_REG_CR_ISR 4113 |
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254 | +#define _IA64_REG_CR_IIP 4115 |
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255 | +#define _IA64_REG_CR_IFA 4116 |
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256 | +#define _IA64_REG_CR_ITIR 4117 |
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257 | +#define _IA64_REG_CR_IIPA 4118 |
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258 | +#define _IA64_REG_CR_IFS 4119 |
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259 | +#define _IA64_REG_CR_IIM 4120 |
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260 | +#define _IA64_REG_CR_IHA 4121 |
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261 | +#define _IA64_REG_CR_LID 4160 |
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262 | +#define _IA64_REG_CR_IVR 4161 /* getreg only */ |
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263 | +#define _IA64_REG_CR_TPR 4162 |
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264 | +#define _IA64_REG_CR_EOI 4163 |
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265 | +#define _IA64_REG_CR_IRR0 4164 /* getreg only */ |
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266 | +#define _IA64_REG_CR_IRR1 4165 /* getreg only */ |
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267 | +#define _IA64_REG_CR_IRR2 4166 /* getreg only */ |
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268 | +#define _IA64_REG_CR_IRR3 4167 /* getreg only */ |
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269 | +#define _IA64_REG_CR_ITV 4168 |
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270 | +#define _IA64_REG_CR_PMV 4169 |
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271 | +#define _IA64_REG_CR_CMCV 4170 |
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272 | +#define _IA64_REG_CR_LRR0 4176 |
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273 | +#define _IA64_REG_CR_LRR1 4177 |
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274 | + |
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275 | +/* Indirect Registers for getindreg() and setindreg() */ |
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276 | + |
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277 | +#define _IA64_REG_INDR_CPUID 9000 /* getindreg only */ |
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278 | +#define _IA64_REG_INDR_DBR 9001 |
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279 | +#define _IA64_REG_INDR_IBR 9002 |
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280 | +#define _IA64_REG_INDR_PKR 9003 |
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281 | +#define _IA64_REG_INDR_PMC 9004 |
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282 | +#define _IA64_REG_INDR_PMD 9005 |
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283 | +#define _IA64_REG_INDR_RR 9006 |
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284 | + |
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285 | +#ifdef __INTEL_COMPILER |
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286 | +void __fc(uint64_t *addr); |
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287 | +void __synci(void); |
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288 | +void __isrlz(void); |
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289 | +void __dsrlz(void); |
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290 | +uint64_t __getReg(const int whichReg); |
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291 | +uint64_t _InterlockedCompareExchange8_rel(volatile uint8_t *dest, uint64_t xchg, uint64_t comp); |
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292 | +uint64_t _InterlockedCompareExchange8_acq(volatile uint8_t *dest, uint64_t xchg, uint64_t comp); |
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293 | +uint64_t _InterlockedCompareExchange16_rel(volatile uint16_t *dest, uint64_t xchg, uint64_t comp); |
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294 | +uint64_t _InterlockedCompareExchange16_acq(volatile uint16_t *dest, uint64_t xchg, uint64_t comp); |
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295 | +uint64_t _InterlockedCompareExchange_rel(volatile uint32_t *dest, uint64_t xchg, uint64_t comp); |
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296 | +uint64_t _InterlockedCompareExchange_acq(volatile uint32_t *dest, uint64_t xchg, uint64_t comp); |
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297 | +uint64_t _InterlockedCompareExchange64_rel(volatile uint64_t *dest, uint64_t xchg, uint64_t comp); |
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298 | +u64_t _InterlockedCompareExchange64_acq(volatile uint64_t *dest, uint64_t xchg, uint64_t comp); |
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299 | + |
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300 | +#define ia64_cmpxchg1_rel _InterlockedCompareExchange8_rel |
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301 | +#define ia64_cmpxchg1_acq _InterlockedCompareExchange8_acq |
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302 | +#define ia64_cmpxchg2_rel _InterlockedCompareExchange16_rel |
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303 | +#define ia64_cmpxchg2_acq _InterlockedCompareExchange16_acq |
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304 | +#define ia64_cmpxchg4_rel _InterlockedCompareExchange_rel |
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305 | +#define ia64_cmpxchg4_acq _InterlockedCompareExchange_acq |
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306 | +#define ia64_cmpxchg8_rel _InterlockedCompareExchange64_rel |
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307 | +#define ia64_cmpxchg8_acq _InterlockedCompareExchange64_acq |
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308 | + |
---|
309 | +#define ia64_srlz_d __dsrlz |
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310 | +#define ia64_srlz_i __isrlz |
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311 | +#define __ia64_fc __fc |
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312 | +#define ia64_sync_i __synci |
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313 | +#define __ia64_getreg __getReg |
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314 | +#else /* __INTEL_COMPILER */ |
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315 | +#define ia64_cmpxchg1_acq(ptr, new, old) \ |
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316 | +({ \ |
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317 | + uint64_t ia64_intri_res; \ |
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318 | + asm volatile ("mov ar.ccv=%0;;" :: "rO"(old)); \ |
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319 | + asm volatile ("cmpxchg1.acq %0=[%1],%2,ar.ccv": \ |
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320 | + "=r"(ia64_intri_res) : "r"(ptr), "r"(new) : "memory"); \ |
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321 | + ia64_intri_res; \ |
---|
322 | +}) |
---|
323 | + |
---|
324 | +#define ia64_cmpxchg1_rel(ptr, new, old) \ |
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325 | +({ \ |
---|
326 | + uint64_t ia64_intri_res; \ |
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327 | + asm volatile ("mov ar.ccv=%0;;" :: "rO"(old)); \ |
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328 | + asm volatile ("cmpxchg1.rel %0=[%1],%2,ar.ccv": \ |
---|
329 | + "=r"(ia64_intri_res) : "r"(ptr), "r"(new) : "memory"); \ |
---|
330 | + ia64_intri_res; \ |
---|
331 | +}) |
---|
332 | + |
---|
333 | +#define ia64_cmpxchg2_acq(ptr, new, old) \ |
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334 | +({ \ |
---|
335 | + uint64_t ia64_intri_res; \ |
---|
336 | + asm volatile ("mov ar.ccv=%0;;" :: "rO"(old)); \ |
---|
337 | + asm volatile ("cmpxchg2.acq %0=[%1],%2,ar.ccv": \ |
---|
338 | + "=r"(ia64_intri_res) : "r"(ptr), "r"(new) : "memory"); \ |
---|
339 | + ia64_intri_res; \ |
---|
340 | +}) |
---|
341 | + |
---|
342 | +#define ia64_cmpxchg2_rel(ptr, new, old) \ |
---|
343 | +({ \ |
---|
344 | + uint64_t ia64_intri_res; \ |
---|
345 | + asm volatile ("mov ar.ccv=%0;;" :: "rO"(old)); \ |
---|
346 | + \ |
---|
347 | + asm volatile ("cmpxchg2.rel %0=[%1],%2,ar.ccv": \ |
---|
348 | + "=r"(ia64_intri_res) : "r"(ptr), "r"(new) : "memory"); \ |
---|
349 | + ia64_intri_res; \ |
---|
350 | +}) |
---|
351 | + |
---|
352 | +#define ia64_cmpxchg4_acq(ptr, new, old) \ |
---|
353 | +({ \ |
---|
354 | + uint64_t ia64_intri_res; \ |
---|
355 | + asm volatile ("mov ar.ccv=%0;;" :: "rO"(old)); \ |
---|
356 | + asm volatile ("cmpxchg4.acq %0=[%1],%2,ar.ccv": \ |
---|
357 | + "=r"(ia64_intri_res) : "r"(ptr), "r"(new) : "memory"); \ |
---|
358 | + ia64_intri_res; \ |
---|
359 | +}) |
---|
360 | + |
---|
361 | +#define ia64_cmpxchg4_rel(ptr, new, old) \ |
---|
362 | +({ \ |
---|
363 | + uint64_t ia64_intri_res; \ |
---|
364 | + asm volatile ("mov ar.ccv=%0;;" :: "rO"(old)); \ |
---|
365 | + asm volatile ("cmpxchg4.rel %0=[%1],%2,ar.ccv": \ |
---|
366 | + "=r"(ia64_intri_res) : "r"(ptr), "r"(new) : "memory"); \ |
---|
367 | + ia64_intri_res; \ |
---|
368 | +}) |
---|
369 | + |
---|
370 | +#define ia64_cmpxchg8_acq(ptr, new, old) \ |
---|
371 | +({ \ |
---|
372 | + uint64_t ia64_intri_res; \ |
---|
373 | + asm volatile ("mov ar.ccv=%0;;" :: "rO"(old)); \ |
---|
374 | + asm volatile ("cmpxchg8.acq %0=[%1],%2,ar.ccv": \ |
---|
375 | + "=r"(ia64_intri_res) : "r"(ptr), "r"(new) : "memory"); \ |
---|
376 | + ia64_intri_res; \ |
---|
377 | +}) |
---|
378 | + |
---|
379 | +#define ia64_cmpxchg8_rel(ptr, new, old) \ |
---|
380 | +({ \ |
---|
381 | + uint64_t ia64_intri_res; \ |
---|
382 | + asm volatile ("mov ar.ccv=%0;;" :: "rO"(old)); \ |
---|
383 | + \ |
---|
384 | + asm volatile ("cmpxchg8.rel %0=[%1],%2,ar.ccv": \ |
---|
385 | + "=r"(ia64_intri_res) : "r"(ptr), "r"(new) : "memory"); \ |
---|
386 | + ia64_intri_res; \ |
---|
387 | +}) |
---|
388 | + |
---|
389 | +#define ia64_srlz_i() asm volatile (";; srlz.i ;;" ::: "memory") |
---|
390 | +#define ia64_srlz_d() asm volatile (";; srlz.d" ::: "memory"); |
---|
391 | +#define __ia64_fc(addr) asm volatile ("fc %0" :: "r"(addr) : "memory") |
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392 | +#define ia64_sync_i() asm volatile (";; sync.i" ::: "memory") |
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393 | + |
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394 | +register unsigned long ia64_r13 asm ("r13") __attribute_used__; |
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395 | +#define __ia64_getreg(regnum) \ |
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396 | +({ \ |
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397 | + uint64_t ia64_intri_res; \ |
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398 | + \ |
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399 | + switch (regnum) { \ |
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400 | + case _IA64_REG_GP: \ |
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401 | + asm volatile ("mov %0=gp" : "=r"(ia64_intri_res)); \ |
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402 | + break; \ |
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403 | + case _IA64_REG_IP: \ |
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404 | + asm volatile ("mov %0=ip" : "=r"(ia64_intri_res)); \ |
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405 | + break; \ |
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406 | + case _IA64_REG_PSR: \ |
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407 | + asm volatile ("mov %0=psr" : "=r"(ia64_intri_res)); \ |
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408 | + break; \ |
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409 | + case _IA64_REG_TP: /* for current() */ \ |
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410 | + ia64_intri_res = ia64_r13; \ |
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411 | + break; \ |
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412 | + case _IA64_REG_AR_KR0 ... _IA64_REG_AR_EC: \ |
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413 | + asm volatile ("mov %0=ar%1" : "=r" (ia64_intri_res) \ |
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414 | + : "i"(regnum - _IA64_REG_AR_KR0)); \ |
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415 | + break; \ |
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416 | + case _IA64_REG_CR_DCR ... _IA64_REG_CR_LRR1: \ |
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417 | + asm volatile ("mov %0=cr%1" : "=r" (ia64_intri_res) \ |
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418 | + : "i" (regnum - _IA64_REG_CR_DCR)); \ |
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419 | + break; \ |
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420 | + case _IA64_REG_SP: \ |
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421 | + asm volatile ("mov %0=sp" : "=r" (ia64_intri_res)); \ |
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422 | + break; \ |
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423 | + default: \ |
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424 | + ia64_bad_param_for_getreg(); \ |
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425 | + break; \ |
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426 | + } \ |
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427 | + ia64_intri_res; \ |
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428 | +}) |
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429 | + |
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430 | +#endif /* __INTEL_COMPILER */ |
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431 | +#endif /* IA64_INTRINSIC_H */ |
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