1 | # HG changeset patch |
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2 | # User kfraser@localhost.localdomain |
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3 | # Node ID f555a90bcc373a7379bc18f875eac5e7c7122ae9 |
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4 | # Parent b80f00215bbaf2050765e557f1a017a71e1e8529 |
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5 | [HVM] Reworked interrupt distribution logic. |
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6 | |
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7 | TODO: |
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8 | 1. Fix IO-APIC ID to not conflict with LAPIC IDS. |
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9 | 2. Fix i8259 device model (seems to work already though!). |
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10 | 3. Add INTSRC overrides in MPBIOS and ACPI tables so |
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11 | that PCI legacy IRQ routing always ends up at an |
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12 | IO-APIC input with level trigger. Restricting link |
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13 | routing to {5,6,10,11} and setting overrides for all |
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14 | four of those would work. |
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15 | |
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16 | Signed-off-by: Keir Fraser <keir@xensource.com> |
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17 | |
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18 | Index: ioemu/Makefile.target |
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19 | =================================================================== |
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20 | --- ioemu.orig/Makefile.target 2006-12-20 15:04:55.000000000 +0000 |
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21 | +++ ioemu/Makefile.target 2006-12-20 15:08:16.000000000 +0000 |
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22 | @@ -296,9 +296,9 @@ |
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23 | |
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24 | # qemu-dm objects |
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25 | ifeq ($(ARCH),ia64) |
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26 | -LIBOBJS=helper2.o exec-dm.o i8259-dm.o |
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27 | +LIBOBJS=helper2.o exec-dm.o i8259-dm.o piix_pci-dm.o |
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28 | else |
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29 | -LIBOBJS=helper2.o exec-dm.o i8259-dm.o rtc-dm.o |
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30 | +LIBOBJS=helper2.o exec-dm.o i8259-dm.o rtc-dm.o piix_pci-dm.o |
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31 | endif |
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32 | |
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33 | all: $(PROGS) |
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34 | @@ -364,7 +364,7 @@ |
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35 | else |
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36 | VL_OBJS+= fdc.o serial.o pc.o |
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37 | endif |
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38 | -VL_OBJS+= cirrus_vga.o mixeng.o parallel.o acpi.o piix_pci.o |
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39 | +VL_OBJS+= cirrus_vga.o mixeng.o parallel.o acpi.o |
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40 | VL_OBJS+= usb-uhci.o |
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41 | VL_OBJS+= piix4acpi.o |
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42 | VL_OBJS+= xenstore.o |
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43 | Index: ioemu/target-i386-dm/i8259-dm.c |
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44 | =================================================================== |
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45 | --- ioemu.orig/target-i386-dm/i8259-dm.c 2006-12-20 15:04:54.000000000 +0000 |
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46 | +++ ioemu/target-i386-dm/i8259-dm.c 2006-12-20 15:04:55.000000000 +0000 |
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47 | @@ -33,7 +33,7 @@ |
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48 | |
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49 | void pic_set_irq_new(void *opaque, int irq, int level) |
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50 | { |
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51 | - xc_hvm_set_irq_level(xc_handle, domid, irq, level); |
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52 | + xc_hvm_set_isa_irq_level(xc_handle, domid, irq, level); |
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53 | } |
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54 | |
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55 | /* obsolete function */ |
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56 | Index: ioemu/target-i386-dm/piix_pci-dm.c |
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57 | =================================================================== |
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58 | --- /dev/null 1970-01-01 00:00:00.000000000 +0000 |
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59 | +++ ioemu/target-i386-dm/piix_pci-dm.c 2006-12-20 15:08:13.000000000 +0000 |
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60 | @@ -0,0 +1,397 @@ |
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61 | +/* |
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62 | + * QEMU i440FX/PIIX3 PCI Bridge Emulation |
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63 | + * |
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64 | + * Copyright (c) 2006 Fabrice Bellard |
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65 | + * |
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66 | + * Permission is hereby granted, free of charge, to any person obtaining a copy |
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67 | + * of this software and associated documentation files (the "Software"), to deal |
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68 | + * in the Software without restriction, including without limitation the rights |
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69 | + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
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70 | + * copies of the Software, and to permit persons to whom the Software is |
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71 | + * furnished to do so, subject to the following conditions: |
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72 | + * |
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73 | + * The above copyright notice and this permission notice shall be included in |
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74 | + * all copies or substantial portions of the Software. |
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75 | + * |
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76 | + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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77 | + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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78 | + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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79 | + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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80 | + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
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81 | + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
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82 | + * THE SOFTWARE. |
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83 | + */ |
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84 | + |
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85 | +#include "vl.h" |
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86 | +typedef uint32_t pci_addr_t; |
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87 | +#include "hw/pci_host.h" |
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88 | + |
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89 | +typedef PCIHostState I440FXState; |
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90 | + |
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91 | +static void i440fx_addr_writel(void* opaque, uint32_t addr, uint32_t val) |
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92 | +{ |
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93 | + I440FXState *s = opaque; |
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94 | + s->config_reg = val; |
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95 | +} |
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96 | + |
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97 | +static uint32_t i440fx_addr_readl(void* opaque, uint32_t addr) |
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98 | +{ |
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99 | + I440FXState *s = opaque; |
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100 | + return s->config_reg; |
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101 | +} |
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102 | + |
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103 | +static void i440fx_set_irq(PCIDevice *pci_dev, void *pic, int intx, int level) |
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104 | +{ |
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105 | + xc_hvm_set_pci_intx_level(xc_handle, domid, 0, 0, pci_dev->devfn >> 3, |
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106 | + intx, level); |
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107 | +} |
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108 | + |
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109 | +PCIBus *i440fx_init(void) |
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110 | +{ |
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111 | + PCIBus *b; |
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112 | + PCIDevice *d; |
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113 | + I440FXState *s; |
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114 | + |
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115 | + s = qemu_mallocz(sizeof(I440FXState)); |
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116 | + b = pci_register_bus(i440fx_set_irq, NULL, 0); |
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117 | + s->bus = b; |
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118 | + |
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119 | + register_ioport_write(0xcf8, 4, 4, i440fx_addr_writel, s); |
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120 | + register_ioport_read(0xcf8, 4, 4, i440fx_addr_readl, s); |
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121 | + |
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122 | + register_ioport_write(0xcfc, 4, 1, pci_host_data_writeb, s); |
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123 | + register_ioport_write(0xcfc, 4, 2, pci_host_data_writew, s); |
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124 | + register_ioport_write(0xcfc, 4, 4, pci_host_data_writel, s); |
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125 | + register_ioport_read(0xcfc, 4, 1, pci_host_data_readb, s); |
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126 | + register_ioport_read(0xcfc, 4, 2, pci_host_data_readw, s); |
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127 | + register_ioport_read(0xcfc, 4, 4, pci_host_data_readl, s); |
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128 | + |
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129 | + d = pci_register_device(b, "i440FX", sizeof(PCIDevice), 0, |
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130 | + NULL, NULL); |
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131 | + |
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132 | + d->config[0x00] = 0x86; // vendor_id |
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133 | + d->config[0x01] = 0x80; |
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134 | + d->config[0x02] = 0x37; // device_id |
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135 | + d->config[0x03] = 0x12; |
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136 | + d->config[0x08] = 0x02; // revision |
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137 | + d->config[0x0a] = 0x00; // class_sub = host2pci |
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138 | + d->config[0x0b] = 0x06; // class_base = PCI_bridge |
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139 | + d->config[0x0e] = 0x00; // header_type |
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140 | + return b; |
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141 | +} |
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142 | + |
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143 | +/* PIIX3 PCI to ISA bridge */ |
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144 | + |
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145 | +static PCIDevice *piix3_dev; |
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146 | + |
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147 | +static int pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num) |
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148 | +{ |
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149 | + /* This is the barber's pole mapping used by Xen. */ |
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150 | + return (irq_num + (pci_dev->devfn >> 3)) & 3; |
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151 | +} |
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152 | + |
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153 | +static void piix3_write_config(PCIDevice *d, |
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154 | + uint32_t address, uint32_t val, int len) |
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155 | +{ |
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156 | + int i; |
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157 | + |
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158 | + /* Scan for updates to PCI link routes (0x60-0x63). */ |
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159 | + for (i = 0; i < len; i++) { |
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160 | + uint8_t v = (val >> (8*i)) & 0xff; |
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161 | + if (v & 0x80) |
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162 | + v = 0; |
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163 | + v &= 0xf; |
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164 | + if (((address+i) >= 0x60) && ((address+i) <= 0x63)) |
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165 | + xc_hvm_set_pci_link_route(xc_handle, domid, address + i - 0x60, v); |
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166 | + } |
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167 | + |
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168 | + /* Hand off to default logic. */ |
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169 | + pci_default_write_config(d, address, val, len); |
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170 | +} |
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171 | + |
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172 | +static void piix3_reset(PCIDevice *d) |
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173 | +{ |
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174 | + uint8_t *pci_conf = d->config; |
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175 | + |
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176 | + pci_conf[0x04] = 0x07; // master, memory and I/O |
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177 | + pci_conf[0x05] = 0x00; |
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178 | + pci_conf[0x06] = 0x00; |
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179 | + pci_conf[0x07] = 0x02; // PCI_status_devsel_medium |
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180 | + pci_conf[0x4c] = 0x4d; |
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181 | + pci_conf[0x4e] = 0x03; |
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182 | + pci_conf[0x4f] = 0x00; |
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183 | + pci_conf[0x60] = 0x80; |
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184 | + pci_conf[0x61] = 0x80; |
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185 | + pci_conf[0x62] = 0x80; |
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186 | + pci_conf[0x63] = 0x80; |
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187 | + pci_conf[0x69] = 0x02; |
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188 | + pci_conf[0x70] = 0x80; |
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189 | + pci_conf[0x76] = 0x0c; |
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190 | + pci_conf[0x77] = 0x0c; |
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191 | + pci_conf[0x78] = 0x02; |
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192 | + pci_conf[0x79] = 0x00; |
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193 | + pci_conf[0x80] = 0x00; |
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194 | + pci_conf[0x82] = 0x00; |
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195 | + pci_conf[0xa0] = 0x08; |
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196 | + pci_conf[0xa0] = 0x08; |
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197 | + pci_conf[0xa2] = 0x00; |
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198 | + pci_conf[0xa3] = 0x00; |
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199 | + pci_conf[0xa4] = 0x00; |
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200 | + pci_conf[0xa5] = 0x00; |
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201 | + pci_conf[0xa6] = 0x00; |
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202 | + pci_conf[0xa7] = 0x00; |
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203 | + pci_conf[0xa8] = 0x0f; |
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204 | + pci_conf[0xaa] = 0x00; |
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205 | + pci_conf[0xab] = 0x00; |
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206 | + pci_conf[0xac] = 0x00; |
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207 | + pci_conf[0xae] = 0x00; |
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208 | +} |
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209 | + |
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210 | +int piix3_init(PCIBus *bus) |
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211 | +{ |
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212 | + PCIDevice *d; |
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213 | + uint8_t *pci_conf; |
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214 | + |
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215 | + d = pci_register_device(bus, "PIIX3", sizeof(PCIDevice), |
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216 | + -1, NULL, piix3_write_config); |
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217 | + register_savevm("PIIX3", 0, 1, generic_pci_save, generic_pci_load, d); |
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218 | + |
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219 | + piix3_dev = d; |
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220 | + pci_conf = d->config; |
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221 | + |
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222 | + pci_conf[0x00] = 0x86; // Intel |
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223 | + pci_conf[0x01] = 0x80; |
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224 | + pci_conf[0x02] = 0x00; // 82371SB PIIX3 PCI-to-ISA bridge (Step A1) |
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225 | + pci_conf[0x03] = 0x70; |
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226 | + pci_conf[0x0a] = 0x01; // class_sub = PCI_ISA |
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227 | + pci_conf[0x0b] = 0x06; // class_base = PCI_bridge |
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228 | + pci_conf[0x0e] = 0x80; // header_type = PCI_multifunction, generic |
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229 | + |
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230 | + piix3_reset(d); |
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231 | + return d->devfn; |
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232 | +} |
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233 | + |
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234 | +/***********************************************************/ |
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235 | +/* XXX: the following should be moved to the PC BIOS */ |
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236 | + |
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237 | +static __attribute__((unused)) uint32_t isa_inb(uint32_t addr) |
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238 | +{ |
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239 | + return cpu_inb(NULL, addr); |
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240 | +} |
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241 | + |
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242 | +static void isa_outb(uint32_t val, uint32_t addr) |
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243 | +{ |
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244 | + cpu_outb(NULL, addr, val); |
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245 | +} |
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246 | + |
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247 | +static __attribute__((unused)) uint32_t isa_inw(uint32_t addr) |
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248 | +{ |
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249 | + return cpu_inw(NULL, addr); |
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250 | +} |
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251 | + |
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252 | +static __attribute__((unused)) void isa_outw(uint32_t val, uint32_t addr) |
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253 | +{ |
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254 | + cpu_outw(NULL, addr, val); |
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255 | +} |
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256 | + |
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257 | +static __attribute__((unused)) uint32_t isa_inl(uint32_t addr) |
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258 | +{ |
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259 | + return cpu_inl(NULL, addr); |
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260 | +} |
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261 | + |
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262 | +static __attribute__((unused)) void isa_outl(uint32_t val, uint32_t addr) |
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263 | +{ |
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264 | + cpu_outl(NULL, addr, val); |
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265 | +} |
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266 | + |
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267 | +static uint32_t pci_bios_io_addr; |
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268 | +static uint32_t pci_bios_mem_addr; |
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269 | +/* host irqs corresponding to PCI irqs A-D */ |
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270 | +static uint8_t pci_irqs[4] = { 10, 11, 10, 11 }; |
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271 | + |
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272 | +static void pci_config_writel(PCIDevice *d, uint32_t addr, uint32_t val) |
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273 | +{ |
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274 | + PCIBus *s = d->bus; |
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275 | + addr |= (pci_bus_num(s) << 16) | (d->devfn << 8); |
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276 | + pci_data_write(s, addr, val, 4); |
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277 | +} |
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278 | + |
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279 | +static void pci_config_writew(PCIDevice *d, uint32_t addr, uint32_t val) |
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280 | +{ |
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281 | + PCIBus *s = d->bus; |
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282 | + addr |= (pci_bus_num(s) << 16) | (d->devfn << 8); |
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283 | + pci_data_write(s, addr, val, 2); |
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284 | +} |
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285 | + |
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286 | +static void pci_config_writeb(PCIDevice *d, uint32_t addr, uint32_t val) |
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287 | +{ |
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288 | + PCIBus *s = d->bus; |
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289 | + addr |= (pci_bus_num(s) << 16) | (d->devfn << 8); |
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290 | + pci_data_write(s, addr, val, 1); |
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291 | +} |
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292 | + |
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293 | +static __attribute__((unused)) uint32_t pci_config_readl(PCIDevice *d, uint32_t addr) |
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294 | +{ |
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295 | + PCIBus *s = d->bus; |
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296 | + addr |= (pci_bus_num(s) << 16) | (d->devfn << 8); |
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297 | + return pci_data_read(s, addr, 4); |
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298 | +} |
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299 | + |
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300 | +static uint32_t pci_config_readw(PCIDevice *d, uint32_t addr) |
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301 | +{ |
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302 | + PCIBus *s = d->bus; |
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303 | + addr |= (pci_bus_num(s) << 16) | (d->devfn << 8); |
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304 | + return pci_data_read(s, addr, 2); |
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305 | +} |
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306 | + |
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307 | +static uint32_t pci_config_readb(PCIDevice *d, uint32_t addr) |
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308 | +{ |
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309 | + PCIBus *s = d->bus; |
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310 | + addr |= (pci_bus_num(s) << 16) | (d->devfn << 8); |
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311 | + return pci_data_read(s, addr, 1); |
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312 | +} |
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313 | + |
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314 | +static void pci_set_io_region_addr(PCIDevice *d, int region_num, uint32_t addr) |
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315 | +{ |
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316 | + PCIIORegion *r; |
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317 | + uint16_t cmd; |
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318 | + uint32_t ofs; |
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319 | + |
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320 | + if ( region_num == PCI_ROM_SLOT ) { |
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321 | + ofs = 0x30; |
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322 | + }else{ |
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323 | + ofs = 0x10 + region_num * 4; |
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324 | + } |
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325 | + |
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326 | + pci_config_writel(d, ofs, addr); |
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327 | + r = &d->io_regions[region_num]; |
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328 | + |
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329 | + /* enable memory mappings */ |
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330 | + cmd = pci_config_readw(d, PCI_COMMAND); |
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331 | + if ( region_num == PCI_ROM_SLOT ) |
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332 | + cmd |= 2; |
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333 | + else if (r->type & PCI_ADDRESS_SPACE_IO) |
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334 | + cmd |= 1; |
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335 | + else |
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336 | + cmd |= 2; |
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337 | + pci_config_writew(d, PCI_COMMAND, cmd); |
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338 | +} |
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339 | + |
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340 | +static void pci_bios_init_device(PCIDevice *d) |
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341 | +{ |
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342 | + int class; |
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343 | + PCIIORegion *r; |
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344 | + uint32_t *paddr; |
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345 | + int i, pin, pic_irq, vendor_id, device_id; |
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346 | + |
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347 | + class = pci_config_readw(d, PCI_CLASS_DEVICE); |
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348 | + vendor_id = pci_config_readw(d, PCI_VENDOR_ID); |
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349 | + device_id = pci_config_readw(d, PCI_DEVICE_ID); |
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350 | + switch(class) { |
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351 | + case 0x0101: |
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352 | + if (vendor_id == 0x8086 && device_id == 0x7010) { |
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353 | + /* PIIX3 IDE */ |
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354 | + pci_config_writew(d, 0x40, 0x8000); // enable IDE0 |
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355 | + pci_config_writew(d, 0x42, 0x8000); // enable IDE1 |
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356 | + goto default_map; |
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357 | + } else { |
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358 | + /* IDE: we map it as in ISA mode */ |
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359 | + pci_set_io_region_addr(d, 0, 0x1f0); |
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360 | + pci_set_io_region_addr(d, 1, 0x3f4); |
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361 | + pci_set_io_region_addr(d, 2, 0x170); |
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362 | + pci_set_io_region_addr(d, 3, 0x374); |
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363 | + } |
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364 | + break; |
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365 | + case 0x0680: |
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366 | + if (vendor_id == 0x8086 && device_id == 0x7113) { |
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367 | + /* |
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368 | + * PIIX4 ACPI PM. |
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369 | + * Special device with special PCI config space. No ordinary BARs. |
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370 | + */ |
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371 | + pci_config_writew(d, 0x20, 0x0000); // No smb bus IO enable |
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372 | + pci_config_writew(d, 0x22, 0x0000); |
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373 | + pci_config_writew(d, 0x3c, 0x0009); // Hardcoded IRQ9 |
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374 | + pci_config_writew(d, 0x3d, 0x0001); |
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375 | + } |
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376 | + break; |
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377 | + case 0x0300: |
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378 | + if (vendor_id != 0x1234) |
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379 | + goto default_map; |
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380 | + /* VGA: map frame buffer to default Bochs VBE address */ |
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381 | + pci_set_io_region_addr(d, 0, 0xE0000000); |
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382 | + break; |
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383 | + case 0x0800: |
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384 | + /* PIC */ |
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385 | + vendor_id = pci_config_readw(d, PCI_VENDOR_ID); |
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386 | + device_id = pci_config_readw(d, PCI_DEVICE_ID); |
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387 | + if (vendor_id == 0x1014) { |
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388 | + /* IBM */ |
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389 | + if (device_id == 0x0046 || device_id == 0xFFFF) { |
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390 | + /* MPIC & MPIC2 */ |
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391 | + pci_set_io_region_addr(d, 0, 0x80800000 + 0x00040000); |
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392 | + } |
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393 | + } |
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394 | + break; |
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395 | + case 0xff00: |
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396 | + if (vendor_id == 0x0106b && |
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397 | + (device_id == 0x0017 || device_id == 0x0022)) { |
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398 | + /* macio bridge */ |
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399 | + pci_set_io_region_addr(d, 0, 0x80800000); |
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400 | + } |
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401 | + break; |
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402 | + default: |
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403 | + default_map: |
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404 | + /* default memory mappings */ |
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405 | + for(i = 0; i < PCI_NUM_REGIONS; i++) { |
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406 | + r = &d->io_regions[i]; |
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407 | + if (r->size) { |
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408 | + if (r->type & PCI_ADDRESS_SPACE_IO) |
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409 | + paddr = &pci_bios_io_addr; |
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410 | + else |
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411 | + paddr = &pci_bios_mem_addr; |
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412 | + *paddr = (*paddr + r->size - 1) & ~(r->size - 1); |
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413 | + pci_set_io_region_addr(d, i, *paddr); |
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414 | + *paddr += r->size; |
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415 | + } |
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416 | + } |
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417 | + break; |
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418 | + } |
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419 | + |
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420 | + /* map the interrupt */ |
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421 | + pin = pci_config_readb(d, PCI_INTERRUPT_PIN); |
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422 | + if (pin != 0) { |
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423 | + pin = pci_slot_get_pirq(d, pin - 1); |
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424 | + pic_irq = pci_irqs[pin]; |
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425 | + pci_config_writeb(d, PCI_INTERRUPT_LINE, pic_irq); |
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426 | + } |
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427 | +} |
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428 | + |
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429 | +/* |
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430 | + * This function initializes the PCI devices as a normal PCI BIOS |
---|
431 | + * would do. It is provided just in case the BIOS has no support for |
---|
432 | + * PCI. |
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433 | + */ |
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434 | +void pci_bios_init(void) |
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435 | +{ |
---|
436 | + int i, irq; |
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437 | + uint8_t elcr[2]; |
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438 | + |
---|
439 | + pci_bios_io_addr = 0xc000; |
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440 | + pci_bios_mem_addr = HVM_BELOW_4G_MMIO_START; |
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441 | + |
---|
442 | + /* activate IRQ mappings */ |
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443 | + elcr[0] = 0x00; |
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444 | + elcr[1] = 0x00; |
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445 | + for(i = 0; i < 4; i++) { |
---|
446 | + irq = pci_irqs[i]; |
---|
447 | + /* set to trigger level */ |
---|
448 | + elcr[irq >> 3] |= (1 << (irq & 7)); |
---|
449 | + /* activate irq remapping in PIIX */ |
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450 | + pci_config_writeb(piix3_dev, 0x60 + i, irq); |
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451 | + } |
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452 | + isa_outb(elcr[0], 0x4d0); |
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453 | + isa_outb(elcr[1], 0x4d1); |
---|
454 | + |
---|
455 | + pci_for_each_device(pci_bios_init_device); |
---|
456 | +} |
---|
457 | + |
---|