source: trunk/packages/xen-3.1/xen-3.1/tools/ioemu/patches/fix-interrupt-routing @ 34

Last change on this file since 34 was 34, checked in by hartmans, 18 years ago

Add xen and xen-common

File size: 13.9 KB
Line 
1# HG changeset patch
2# User kfraser@localhost.localdomain
3# Node ID f555a90bcc373a7379bc18f875eac5e7c7122ae9
4# Parent  b80f00215bbaf2050765e557f1a017a71e1e8529
5[HVM] Reworked interrupt distribution logic.
6
7TODO:
8 1. Fix IO-APIC ID to not conflict with LAPIC IDS.
9 2. Fix i8259 device model (seems to work already though!).
10 3. Add INTSRC overrides in MPBIOS and ACPI tables so
11    that PCI legacy IRQ routing always ends up at an
12    IO-APIC input with level trigger. Restricting link
13    routing to {5,6,10,11} and setting overrides for all
14    four of those would work.
15
16Signed-off-by: Keir Fraser <keir@xensource.com>
17
18Index: ioemu/Makefile.target
19===================================================================
20--- ioemu.orig/Makefile.target  2006-12-20 15:04:55.000000000 +0000
21+++ ioemu/Makefile.target       2006-12-20 15:08:16.000000000 +0000
22@@ -296,9 +296,9 @@
23 
24 # qemu-dm objects
25 ifeq ($(ARCH),ia64)
26-LIBOBJS=helper2.o exec-dm.o i8259-dm.o
27+LIBOBJS=helper2.o exec-dm.o i8259-dm.o piix_pci-dm.o
28 else
29-LIBOBJS=helper2.o exec-dm.o i8259-dm.o rtc-dm.o
30+LIBOBJS=helper2.o exec-dm.o i8259-dm.o rtc-dm.o piix_pci-dm.o
31 endif
32 
33 all: $(PROGS)
34@@ -364,7 +364,7 @@
35 else
36 VL_OBJS+= fdc.o serial.o pc.o
37 endif
38-VL_OBJS+= cirrus_vga.o mixeng.o parallel.o acpi.o piix_pci.o
39+VL_OBJS+= cirrus_vga.o mixeng.o parallel.o acpi.o
40 VL_OBJS+= usb-uhci.o
41 VL_OBJS+= piix4acpi.o
42 VL_OBJS+= xenstore.o
43Index: ioemu/target-i386-dm/i8259-dm.c
44===================================================================
45--- ioemu.orig/target-i386-dm/i8259-dm.c        2006-12-20 15:04:54.000000000 +0000
46+++ ioemu/target-i386-dm/i8259-dm.c     2006-12-20 15:04:55.000000000 +0000
47@@ -33,7 +33,7 @@
48 
49 void pic_set_irq_new(void *opaque, int irq, int level)
50 {
51-    xc_hvm_set_irq_level(xc_handle, domid, irq, level);
52+    xc_hvm_set_isa_irq_level(xc_handle, domid, irq, level);
53 }
54 
55 /* obsolete function */
56Index: ioemu/target-i386-dm/piix_pci-dm.c
57===================================================================
58--- /dev/null   1970-01-01 00:00:00.000000000 +0000
59+++ ioemu/target-i386-dm/piix_pci-dm.c  2006-12-20 15:08:13.000000000 +0000
60@@ -0,0 +1,397 @@
61+/*
62+ * QEMU i440FX/PIIX3 PCI Bridge Emulation
63+ *
64+ * Copyright (c) 2006 Fabrice Bellard
65+ *
66+ * Permission is hereby granted, free of charge, to any person obtaining a copy
67+ * of this software and associated documentation files (the "Software"), to deal
68+ * in the Software without restriction, including without limitation the rights
69+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
70+ * copies of the Software, and to permit persons to whom the Software is
71+ * furnished to do so, subject to the following conditions:
72+ *
73+ * The above copyright notice and this permission notice shall be included in
74+ * all copies or substantial portions of the Software.
75+ *
76+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
77+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
78+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
79+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
80+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
81+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
82+ * THE SOFTWARE.
83+ */
84+
85+#include "vl.h"
86+typedef uint32_t pci_addr_t;
87+#include "hw/pci_host.h"
88+
89+typedef PCIHostState I440FXState;
90+
91+static void i440fx_addr_writel(void* opaque, uint32_t addr, uint32_t val)
92+{
93+    I440FXState *s = opaque;
94+    s->config_reg = val;
95+}
96+
97+static uint32_t i440fx_addr_readl(void* opaque, uint32_t addr)
98+{
99+    I440FXState *s = opaque;
100+    return s->config_reg;
101+}
102+
103+static void i440fx_set_irq(PCIDevice *pci_dev, void *pic, int intx, int level)
104+{
105+    xc_hvm_set_pci_intx_level(xc_handle, domid, 0, 0, pci_dev->devfn >> 3,
106+                              intx, level);
107+}
108+
109+PCIBus *i440fx_init(void)
110+{
111+    PCIBus *b;
112+    PCIDevice *d;
113+    I440FXState *s;
114+
115+    s = qemu_mallocz(sizeof(I440FXState));
116+    b = pci_register_bus(i440fx_set_irq, NULL, 0);
117+    s->bus = b;
118+
119+    register_ioport_write(0xcf8, 4, 4, i440fx_addr_writel, s);
120+    register_ioport_read(0xcf8, 4, 4, i440fx_addr_readl, s);
121+
122+    register_ioport_write(0xcfc, 4, 1, pci_host_data_writeb, s);
123+    register_ioport_write(0xcfc, 4, 2, pci_host_data_writew, s);
124+    register_ioport_write(0xcfc, 4, 4, pci_host_data_writel, s);
125+    register_ioport_read(0xcfc, 4, 1, pci_host_data_readb, s);
126+    register_ioport_read(0xcfc, 4, 2, pci_host_data_readw, s);
127+    register_ioport_read(0xcfc, 4, 4, pci_host_data_readl, s);
128+
129+    d = pci_register_device(b, "i440FX", sizeof(PCIDevice), 0,
130+                            NULL, NULL);
131+
132+    d->config[0x00] = 0x86; // vendor_id
133+    d->config[0x01] = 0x80;
134+    d->config[0x02] = 0x37; // device_id
135+    d->config[0x03] = 0x12;
136+    d->config[0x08] = 0x02; // revision
137+    d->config[0x0a] = 0x00; // class_sub = host2pci
138+    d->config[0x0b] = 0x06; // class_base = PCI_bridge
139+    d->config[0x0e] = 0x00; // header_type
140+    return b;
141+}
142+
143+/* PIIX3 PCI to ISA bridge */
144+
145+static PCIDevice *piix3_dev;
146+
147+static int pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num)
148+{
149+    /* This is the barber's pole mapping used by Xen. */
150+    return (irq_num + (pci_dev->devfn >> 3)) & 3;
151+}
152+
153+static void piix3_write_config(PCIDevice *d,
154+                               uint32_t address, uint32_t val, int len)
155+{
156+    int i;
157+
158+    /* Scan for updates to PCI link routes (0x60-0x63). */
159+    for (i = 0; i < len; i++) {
160+        uint8_t v = (val >> (8*i)) & 0xff;
161+        if (v & 0x80)
162+            v = 0;
163+        v &= 0xf;
164+        if (((address+i) >= 0x60) && ((address+i) <= 0x63))
165+            xc_hvm_set_pci_link_route(xc_handle, domid, address + i - 0x60, v);
166+    }
167+
168+    /* Hand off to default logic. */
169+    pci_default_write_config(d, address, val, len);
170+}
171+
172+static void piix3_reset(PCIDevice *d)
173+{
174+    uint8_t *pci_conf = d->config;
175+
176+    pci_conf[0x04] = 0x07; // master, memory and I/O
177+    pci_conf[0x05] = 0x00;
178+    pci_conf[0x06] = 0x00;
179+    pci_conf[0x07] = 0x02; // PCI_status_devsel_medium
180+    pci_conf[0x4c] = 0x4d;
181+    pci_conf[0x4e] = 0x03;
182+    pci_conf[0x4f] = 0x00;
183+    pci_conf[0x60] = 0x80;
184+    pci_conf[0x61] = 0x80;
185+    pci_conf[0x62] = 0x80;
186+    pci_conf[0x63] = 0x80;
187+    pci_conf[0x69] = 0x02;
188+    pci_conf[0x70] = 0x80;
189+    pci_conf[0x76] = 0x0c;
190+    pci_conf[0x77] = 0x0c;
191+    pci_conf[0x78] = 0x02;
192+    pci_conf[0x79] = 0x00;
193+    pci_conf[0x80] = 0x00;
194+    pci_conf[0x82] = 0x00;
195+    pci_conf[0xa0] = 0x08;
196+    pci_conf[0xa0] = 0x08;
197+    pci_conf[0xa2] = 0x00;
198+    pci_conf[0xa3] = 0x00;
199+    pci_conf[0xa4] = 0x00;
200+    pci_conf[0xa5] = 0x00;
201+    pci_conf[0xa6] = 0x00;
202+    pci_conf[0xa7] = 0x00;
203+    pci_conf[0xa8] = 0x0f;
204+    pci_conf[0xaa] = 0x00;
205+    pci_conf[0xab] = 0x00;
206+    pci_conf[0xac] = 0x00;
207+    pci_conf[0xae] = 0x00;
208+}
209+
210+int piix3_init(PCIBus *bus)
211+{
212+    PCIDevice *d;
213+    uint8_t *pci_conf;
214+
215+    d = pci_register_device(bus, "PIIX3", sizeof(PCIDevice),
216+                                    -1, NULL, piix3_write_config);
217+    register_savevm("PIIX3", 0, 1, generic_pci_save, generic_pci_load, d);
218+
219+    piix3_dev = d;
220+    pci_conf = d->config;
221+
222+    pci_conf[0x00] = 0x86; // Intel
223+    pci_conf[0x01] = 0x80;
224+    pci_conf[0x02] = 0x00; // 82371SB PIIX3 PCI-to-ISA bridge (Step A1)
225+    pci_conf[0x03] = 0x70;
226+    pci_conf[0x0a] = 0x01; // class_sub = PCI_ISA
227+    pci_conf[0x0b] = 0x06; // class_base = PCI_bridge
228+    pci_conf[0x0e] = 0x80; // header_type = PCI_multifunction, generic
229+
230+    piix3_reset(d);
231+    return d->devfn;
232+}
233+
234+/***********************************************************/
235+/* XXX: the following should be moved to the PC BIOS */
236+
237+static __attribute__((unused)) uint32_t isa_inb(uint32_t addr)
238+{
239+    return cpu_inb(NULL, addr);
240+}
241+
242+static void isa_outb(uint32_t val, uint32_t addr)
243+{
244+    cpu_outb(NULL, addr, val);
245+}
246+
247+static __attribute__((unused)) uint32_t isa_inw(uint32_t addr)
248+{
249+    return cpu_inw(NULL, addr);
250+}
251+
252+static __attribute__((unused)) void isa_outw(uint32_t val, uint32_t addr)
253+{
254+    cpu_outw(NULL, addr, val);
255+}
256+
257+static __attribute__((unused)) uint32_t isa_inl(uint32_t addr)
258+{
259+    return cpu_inl(NULL, addr);
260+}
261+
262+static __attribute__((unused)) void isa_outl(uint32_t val, uint32_t addr)
263+{
264+    cpu_outl(NULL, addr, val);
265+}
266+
267+static uint32_t pci_bios_io_addr;
268+static uint32_t pci_bios_mem_addr;
269+/* host irqs corresponding to PCI irqs A-D */
270+static uint8_t pci_irqs[4] = { 10, 11, 10, 11 };
271+
272+static void pci_config_writel(PCIDevice *d, uint32_t addr, uint32_t val)
273+{
274+    PCIBus *s = d->bus;
275+    addr |= (pci_bus_num(s) << 16) | (d->devfn << 8);
276+    pci_data_write(s, addr, val, 4);
277+}
278+
279+static void pci_config_writew(PCIDevice *d, uint32_t addr, uint32_t val)
280+{
281+    PCIBus *s = d->bus;
282+    addr |= (pci_bus_num(s) << 16) | (d->devfn << 8);
283+    pci_data_write(s, addr, val, 2);
284+}
285+
286+static void pci_config_writeb(PCIDevice *d, uint32_t addr, uint32_t val)
287+{
288+    PCIBus *s = d->bus;
289+    addr |= (pci_bus_num(s) << 16) | (d->devfn << 8);
290+    pci_data_write(s, addr, val, 1);
291+}
292+
293+static __attribute__((unused)) uint32_t pci_config_readl(PCIDevice *d, uint32_t addr)
294+{
295+    PCIBus *s = d->bus;
296+    addr |= (pci_bus_num(s) << 16) | (d->devfn << 8);
297+    return pci_data_read(s, addr, 4);
298+}
299+
300+static uint32_t pci_config_readw(PCIDevice *d, uint32_t addr)
301+{
302+    PCIBus *s = d->bus;
303+    addr |= (pci_bus_num(s) << 16) | (d->devfn << 8);
304+    return pci_data_read(s, addr, 2);
305+}
306+
307+static uint32_t pci_config_readb(PCIDevice *d, uint32_t addr)
308+{
309+    PCIBus *s = d->bus;
310+    addr |= (pci_bus_num(s) << 16) | (d->devfn << 8);
311+    return pci_data_read(s, addr, 1);
312+}
313+
314+static void pci_set_io_region_addr(PCIDevice *d, int region_num, uint32_t addr)
315+{
316+    PCIIORegion *r;
317+    uint16_t cmd;
318+    uint32_t ofs;
319+
320+    if ( region_num == PCI_ROM_SLOT ) {
321+        ofs = 0x30;
322+    }else{
323+        ofs = 0x10 + region_num * 4;
324+    }
325+
326+    pci_config_writel(d, ofs, addr);
327+    r = &d->io_regions[region_num];
328+
329+    /* enable memory mappings */
330+    cmd = pci_config_readw(d, PCI_COMMAND);
331+    if ( region_num == PCI_ROM_SLOT )
332+        cmd |= 2;
333+    else if (r->type & PCI_ADDRESS_SPACE_IO)
334+        cmd |= 1;
335+    else
336+        cmd |= 2;
337+    pci_config_writew(d, PCI_COMMAND, cmd);
338+}
339+
340+static void pci_bios_init_device(PCIDevice *d)
341+{
342+    int class;
343+    PCIIORegion *r;
344+    uint32_t *paddr;
345+    int i, pin, pic_irq, vendor_id, device_id;
346+
347+    class = pci_config_readw(d, PCI_CLASS_DEVICE);
348+    vendor_id = pci_config_readw(d, PCI_VENDOR_ID);
349+    device_id = pci_config_readw(d, PCI_DEVICE_ID);
350+    switch(class) {
351+    case 0x0101:
352+        if (vendor_id == 0x8086 && device_id == 0x7010) {
353+            /* PIIX3 IDE */
354+            pci_config_writew(d, 0x40, 0x8000); // enable IDE0
355+            pci_config_writew(d, 0x42, 0x8000); // enable IDE1
356+            goto default_map;
357+        } else {
358+            /* IDE: we map it as in ISA mode */
359+            pci_set_io_region_addr(d, 0, 0x1f0);
360+            pci_set_io_region_addr(d, 1, 0x3f4);
361+            pci_set_io_region_addr(d, 2, 0x170);
362+            pci_set_io_region_addr(d, 3, 0x374);
363+        }
364+        break;
365+    case 0x0680:
366+        if (vendor_id == 0x8086 && device_id == 0x7113) {
367+            /*
368+             * PIIX4 ACPI PM.
369+             * Special device with special PCI config space. No ordinary BARs.
370+             */
371+            pci_config_writew(d, 0x20, 0x0000); // No smb bus IO enable
372+            pci_config_writew(d, 0x22, 0x0000);
373+            pci_config_writew(d, 0x3c, 0x0009); // Hardcoded IRQ9
374+            pci_config_writew(d, 0x3d, 0x0001);
375+        }
376+        break;
377+    case 0x0300:
378+        if (vendor_id != 0x1234)
379+            goto default_map;
380+        /* VGA: map frame buffer to default Bochs VBE address */
381+        pci_set_io_region_addr(d, 0, 0xE0000000);
382+        break;
383+    case 0x0800:
384+        /* PIC */
385+        vendor_id = pci_config_readw(d, PCI_VENDOR_ID);
386+        device_id = pci_config_readw(d, PCI_DEVICE_ID);
387+        if (vendor_id == 0x1014) {
388+            /* IBM */
389+            if (device_id == 0x0046 || device_id == 0xFFFF) {
390+                /* MPIC & MPIC2 */
391+                pci_set_io_region_addr(d, 0, 0x80800000 + 0x00040000);
392+            }
393+        }
394+        break;
395+    case 0xff00:
396+        if (vendor_id == 0x0106b &&
397+            (device_id == 0x0017 || device_id == 0x0022)) {
398+            /* macio bridge */
399+            pci_set_io_region_addr(d, 0, 0x80800000);
400+        }
401+        break;
402+    default:
403+    default_map:
404+        /* default memory mappings */
405+        for(i = 0; i < PCI_NUM_REGIONS; i++) {
406+            r = &d->io_regions[i];
407+            if (r->size) {
408+                if (r->type & PCI_ADDRESS_SPACE_IO)
409+                    paddr = &pci_bios_io_addr;
410+                else
411+                    paddr = &pci_bios_mem_addr;
412+                *paddr = (*paddr + r->size - 1) & ~(r->size - 1);
413+                pci_set_io_region_addr(d, i, *paddr);
414+                *paddr += r->size;
415+            }
416+        }
417+        break;
418+    }
419+
420+    /* map the interrupt */
421+    pin = pci_config_readb(d, PCI_INTERRUPT_PIN);
422+    if (pin != 0) {
423+        pin = pci_slot_get_pirq(d, pin - 1);
424+        pic_irq = pci_irqs[pin];
425+        pci_config_writeb(d, PCI_INTERRUPT_LINE, pic_irq);
426+    }
427+}
428+
429+/*
430+ * This function initializes the PCI devices as a normal PCI BIOS
431+ * would do. It is provided just in case the BIOS has no support for
432+ * PCI.
433+ */
434+void pci_bios_init(void)
435+{
436+    int i, irq;
437+    uint8_t elcr[2];
438+
439+    pci_bios_io_addr = 0xc000;
440+    pci_bios_mem_addr = HVM_BELOW_4G_MMIO_START;
441+
442+    /* activate IRQ mappings */
443+    elcr[0] = 0x00;
444+    elcr[1] = 0x00;
445+    for(i = 0; i < 4; i++) {
446+        irq = pci_irqs[i];
447+        /* set to trigger level */
448+        elcr[irq >> 3] |= (1 << (irq & 7));
449+        /* activate irq remapping in PIIX */
450+        pci_config_writeb(piix3_dev, 0x60 + i, irq);
451+    }
452+    isa_outb(elcr[0], 0x4d0);
453+    isa_outb(elcr[1], 0x4d1);
454+
455+    pci_for_each_device(pci_bios_init_device);
456+}
457+
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