source: trunk/packages/xen-3.1/xen-3.1/tools/ioemu/patches/acpi-support @ 34

Last change on this file since 34 was 34, checked in by hartmans, 18 years ago

Add xen and xen-common

File size: 10.5 KB
Line 
1Index: ioemu/Makefile.target
2===================================================================
3--- ioemu.orig/Makefile.target  2007-05-03 15:06:42.000000000 +0100
4+++ ioemu/Makefile.target       2007-05-03 15:07:21.000000000 +0100
5@@ -358,6 +358,7 @@
6 VL_OBJS+= fdc.o mc146818rtc.o serial.o pc.o
7 VL_OBJS+= cirrus_vga.o mixeng.o parallel.o acpi.o piix_pci.o
8 VL_OBJS+= usb-uhci.o
9+VL_OBJS+= piix4acpi.o
10 DEFINES += -DHAS_AUDIO
11 endif
12 ifeq ($(TARGET_BASE_ARCH), ppc)
13Index: ioemu/hw/pc.c
14===================================================================
15--- ioemu.orig/hw/pc.c  2007-05-03 15:06:42.000000000 +0100
16+++ ioemu/hw/pc.c       2007-05-03 15:07:21.000000000 +0100
17@@ -873,13 +873,19 @@
18 
19     cmos_init(ram_size, boot_device, bs_table);
20 
21+    /* using PIIX4 acpi model */
22+    if (pci_enabled && acpi_enabled)
23+        pci_piix4_acpi_init(pci_bus, piix3_devfn + 2);
24+
25     if (pci_enabled && usb_enabled) {
26-        usb_uhci_init(pci_bus, piix3_devfn + 2);
27+        usb_uhci_init(pci_bus, piix3_devfn + (acpi_enabled ? 3 : 2));
28     }
29 
30+#ifndef CONFIG_DM
31     if (pci_enabled && acpi_enabled) {
32         piix4_pm_init(pci_bus, piix3_devfn + 3);
33     }
34+#endif /* !CONFIG_DM */
35 
36 #if 0
37     /* ??? Need to figure out some way for the user to
38@@ -902,8 +908,10 @@
39     /* XXX: should be done in the Bochs BIOS */
40     if (pci_enabled) {
41         pci_bios_init();
42+#ifndef CONFIG_DM
43         if (acpi_enabled)
44             acpi_bios_init();
45+#endif /* !CONFIG_DM */
46     }
47 }
48 
49Index: ioemu/hw/piix4acpi.c
50===================================================================
51--- /dev/null   1970-01-01 00:00:00.000000000 +0000
52+++ ioemu/hw/piix4acpi.c        2007-05-03 15:07:31.000000000 +0100
53@@ -0,0 +1,186 @@
54+/*
55+ * PIIX4 ACPI controller emulation
56+ *
57+ * Winston liwen Wang, winston.l.wang@intel.com
58+ * Copyright (c) 2006 , Intel Corporation.
59+ *
60+ * Permission is hereby granted, free of charge, to any person obtaining a copy
61+ * of this software and associated documentation files (the "Software"), to deal
62+ * in the Software without restriction, including without limitation the rights
63+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
64+ * copies of the Software, and to permit persons to whom the Software is
65+ * furnished to do so, subject to the following conditions:
66+ *
67+ * The above copyright notice and this permission notice shall be included in
68+ * all copies or substantial portions of the Software.
69+ *
70+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
71+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
72+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
73+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
74+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
75+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
76+ * THE SOFTWARE.
77+ */
78+
79+#include "vl.h"
80+#define FREQUENCE_PMTIMER  3753425
81+/* acpi register bit define here  */
82+
83+/* PM1_STS                                             */
84+#define TMROF_STS        (1 << 0)
85+#define BM_STS                   (1 << 4)
86+#define GBL_STS          (1 << 5)
87+#define PWRBTN_STS       (1 << 8)
88+#define RTC_STS          (1 << 10)
89+#define PRBTNOR_STS       (1 << 11)
90+#define WAK_STS          (1 << 15)
91+/* PM1_EN                                              */
92+#define TMROF_EN          (1 << 0)
93+#define GBL_EN            (1 << 5)
94+#define PWRBTN_EN         (1 << 8)
95+#define RTC_EN           (1 << 10)
96+/* PM1_CNT                                             */
97+#define SCI_EN            (1 << 0)
98+#define GBL_RLS           (1 << 2)
99+#define SLP_EN           (1 << 13)
100+
101+typedef struct AcpiDeviceState AcpiDeviceState;
102+AcpiDeviceState *acpi_device_table;
103+
104+typedef struct PCIAcpiState {
105+    PCIDevice dev;
106+    uint16_t pm1_control; /* pm1a_ECNT_BLK */
107+} PCIAcpiState;
108+
109+static inline void acpi_set_irq(PCIAcpiState *s)
110+{
111+/* no real SCI event need for now, so comment the following line out */
112+/*  pic_set_irq(s->irq, 1); */
113+    printf("acpi_set_irq: s->irq %x \n",s->irq);
114+}
115+
116+static void acpiPm1Control_writeb(void *opaque, uint32_t addr, uint32_t val)
117+{
118+    PCIAcpiState *s = opaque;
119+
120+    s->pm1_control = (s->pm1_control & 0xff00) | (val & 0xff);
121+/*  printf("acpiPm1Control_writeb \n addr %x val:%x\n", addr, val); */
122+
123+}
124+
125+static uint32_t acpiPm1Control_readb(void *opaque, uint32_t addr)
126+{
127+    PCIAcpiState *s = opaque;
128+    uint32_t val;
129+
130+    /* Mask out the write-only bits */
131+    val = s->pm1_control & ~(GBL_RLS|SLP_EN) & 0xff;
132+/*    printf("acpiPm1Control_readb \n addr %x val:%x\n", addr, val); */
133+
134+    return val;
135+}
136+
137+static void acpiPm1ControlP1_writeb(void *opaque, uint32_t addr, uint32_t val)
138+{
139+    PCIAcpiState *s = opaque;
140+
141+    s->pm1_control = (s->pm1_control & 0xff) | (val << 8);
142+/*    printf("acpiPm1ControlP1_writeb \n addr %x val:%x\n", addr, val); */
143+
144+}
145+
146+static uint32_t acpiPm1ControlP1_readb(void *opaque, uint32_t addr)
147+{
148+    PCIAcpiState *s = opaque;
149+    uint32_t val;
150+
151+    /* Mask out the write-only bits */
152+    val = (s->pm1_control & ~(GBL_RLS|SLP_EN)) >> 8;
153+/*    printf("acpiPm1ControlP1_readb \n addr %x val:%x\n", addr, val); */
154+
155+    return val;
156+}
157+
158+
159+/* word access   */
160+
161+static void acpiPm1Control_writew(void *opaque, uint32_t addr, uint32_t val)
162+{
163+    PCIAcpiState *s = opaque;
164+
165+    s->pm1_control = val;
166+/*    printf("acpiPm1Control_writew \n addr %x val:%x\n", addr, val); */
167+
168+}
169+
170+static uint32_t acpiPm1Control_readw(void *opaque, uint32_t addr)
171+{
172+    PCIAcpiState *s = opaque;
173+    uint32_t val;
174+
175+    /* Mask out the write-only bits */
176+    val = s->pm1_control & ~(GBL_RLS|SLP_EN);
177+/*    printf("acpiPm1Control_readw \n addr %x val:%x\n", addr, val);  */
178+
179+    return val;
180+}
181+
182+
183+static void acpi_map(PCIDevice *pci_dev, int region_num,
184+                    uint32_t addr, uint32_t size, int type)
185+{
186+    PCIAcpiState *d = (PCIAcpiState *)pci_dev;
187+
188+    printf("register acpi io \n");
189+
190+    /* Byte access */
191+    register_ioport_write(addr + 4, 1, 1, acpiPm1Control_writeb, d);
192+    register_ioport_read(addr + 4, 1, 1, acpiPm1Control_readb, d);
193+    register_ioport_write(addr + 4 + 1, 1, 1, acpiPm1ControlP1_writeb, d);
194+    register_ioport_read(addr + 4 +1, 1, 1, acpiPm1ControlP1_readb, d);
195+
196+    /* Word access */
197+    register_ioport_write(addr + 4, 2, 2, acpiPm1Control_writew, d);
198+    register_ioport_read(addr + 4, 2, 2, acpiPm1Control_readw, d);
199+}
200+
201+/* PIIX4 acpi pci configuration space, func 2 */
202+void pci_piix4_acpi_init(PCIBus *bus, int devfn)
203+{
204+    PCIAcpiState *d;
205+    uint8_t *pci_conf;
206+
207+    /* register a function 2 of PIIX4 */
208+    d = (PCIAcpiState *)pci_register_device(
209+        bus, "PIIX4 ACPI", sizeof(PCIAcpiState),
210+        devfn, NULL, NULL);
211+
212+    pci_conf = d->dev.config;
213+    pci_conf[0x00] = 0x86;  /* Intel */
214+    pci_conf[0x01] = 0x80;
215+    pci_conf[0x02] = 0x13;
216+    pci_conf[0x03] = 0x71;
217+    pci_conf[0x08] = 0x01;  /* B0 stepping */
218+    pci_conf[0x09] = 0x00;  /* base class */
219+    pci_conf[0x0a] = 0x80;  /* Sub class */
220+    pci_conf[0x0b] = 0x06;
221+    pci_conf[0x0e] = 0x00;
222+    pci_conf[0x3d] = 0x01;  /* Hardwired to PIRQA is used */
223+
224+
225+    /* PMBA POWER MANAGEMENT BASE ADDRESS, hardcoded to 0x1f40
226+     * to make shutdown work for IPF, due to IPF Guest Firmware
227+     * will enumerate pci devices.
228+     *
229+     * TODO:  if Guest Firmware or Guest OS will change this PMBA,
230+     * More logic will be added.
231+     */
232+    pci_conf[0x40] = 0x41; /* Special device-specific BAR at 0x40 */
233+    pci_conf[0x41] = 0x1f;
234+    pci_conf[0x42] = 0x00;
235+    pci_conf[0x43] = 0x00;
236+    d->pm1_control = SCI_EN;
237+
238+    acpi_map(d, 0, 0x1f40, 0x10, PCI_ADDRESS_SPACE_IO);
239+}
240Index: ioemu/vl.c
241===================================================================
242--- ioemu.orig/vl.c     2007-05-03 15:06:42.000000000 +0100
243+++ ioemu/vl.c  2007-05-03 15:07:21.000000000 +0100
244@@ -157,7 +157,7 @@
245 #else
246 #define MAX_CPUS 1
247 #endif
248-int acpi_enabled = 1;
249+int acpi_enabled = 0;
250 int fd_bootchk = 1;
251 
252 extern int vcpus;
253@@ -5415,6 +5415,7 @@
254 #endif
255            "-loadvm file    start right away with a saved state (loadvm in monitor)\n"
256           "-vnc display    start a VNC server on display\n"
257+           "-acpi           disable or enable ACPI of HVM domain \n"
258            "\n"
259            "During emulation, the following keys are useful:\n"
260            "ctrl-alt-f      toggle full screen\n"
261@@ -5499,6 +5500,7 @@
262 
263     QEMU_OPTION_d,
264     QEMU_OPTION_vcpus,
265+    QEMU_OPTION_acpi,
266 };
267 
268 typedef struct QEMUOption {
269@@ -5581,6 +5583,7 @@
270     
271     { "d", HAS_ARG, QEMU_OPTION_d },
272     { "vcpus", 1, QEMU_OPTION_vcpus },
273+    { "acpi", 0, QEMU_OPTION_acpi },
274     { NULL },
275 };
276 
277@@ -6322,6 +6325,9 @@
278                 vcpus = atoi(optarg);
279                 fprintf(logfile, "qemu: the number of cpus is %d\n", vcpus);
280                 break;
281+            case QEMU_OPTION_acpi:
282+                acpi_enabled = 1;
283+                break;
284             }
285         }
286     }
287Index: ioemu/vl.h
288===================================================================
289--- ioemu.orig/vl.h     2007-05-03 15:06:42.000000000 +0100
290+++ ioemu/vl.h  2007-05-03 15:07:21.000000000 +0100
291@@ -168,6 +168,7 @@
292 extern int kqemu_allowed;
293 extern int win2k_install_hack;
294 extern int usb_enabled;
295+extern int acpi_enabled;
296 extern int smp_cpus;
297 
298 /* XXX: make it dynamic */
299@@ -924,6 +925,9 @@
300 void piix4_pm_init(PCIBus *bus, int devfn);
301 void acpi_bios_init(void);
302 
303+/* piix4acpi.c */
304+extern void pci_piix4_acpi_init(PCIBus *bus, int devfn);
305+
306 /* pc.c */
307 extern QEMUMachine pc_machine;
308 extern QEMUMachine isapc_machine;
309Index: ioemu/hw/piix_pci.c
310===================================================================
311--- ioemu.orig/hw/piix_pci.c    2007-05-03 15:06:42.000000000 +0100
312+++ ioemu/hw/piix_pci.c 2007-05-03 15:07:13.000000000 +0100
313@@ -241,7 +241,7 @@
314 static uint32_t pci_bios_io_addr;
315 static uint32_t pci_bios_mem_addr;
316 /* host irqs corresponding to PCI irqs A-D */
317-static uint8_t pci_irqs[4] = { 11, 9, 11, 9 };
318+static uint8_t pci_irqs[4] = { 10, 11, 10, 11 };
319 
320 static void pci_config_writel(PCIDevice *d, uint32_t addr, uint32_t val)
321 {
322@@ -336,6 +336,18 @@
323             pci_set_io_region_addr(d, 3, 0x374);
324         }
325         break;
326+    case 0x0680:
327+        if (vendor_id == 0x8086 && device_id == 0x7113) {
328+            /*
329+             * PIIX4 ACPI PM.
330+             * Special device with special PCI config space. No ordinary BARs.
331+             */
332+            pci_config_writew(d, 0x20, 0x0000); // No smb bus IO enable
333+            pci_config_writew(d, 0x22, 0x0000);
334+            pci_config_writew(d, 0x3c, 0x0009); // Hardcoded IRQ9
335+            pci_config_writew(d, 0x3d, 0x0001);
336+        }
337+        break;
338     case 0x0300:
339         if (vendor_id != 0x1234)
340             goto default_map;
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