1 | Index: ioemu/Makefile.target |
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2 | =================================================================== |
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3 | --- ioemu.orig/Makefile.target 2007-05-03 15:06:42.000000000 +0100 |
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4 | +++ ioemu/Makefile.target 2007-05-03 15:07:21.000000000 +0100 |
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5 | @@ -358,6 +358,7 @@ |
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6 | VL_OBJS+= fdc.o mc146818rtc.o serial.o pc.o |
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7 | VL_OBJS+= cirrus_vga.o mixeng.o parallel.o acpi.o piix_pci.o |
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8 | VL_OBJS+= usb-uhci.o |
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9 | +VL_OBJS+= piix4acpi.o |
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10 | DEFINES += -DHAS_AUDIO |
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11 | endif |
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12 | ifeq ($(TARGET_BASE_ARCH), ppc) |
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13 | Index: ioemu/hw/pc.c |
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14 | =================================================================== |
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15 | --- ioemu.orig/hw/pc.c 2007-05-03 15:06:42.000000000 +0100 |
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16 | +++ ioemu/hw/pc.c 2007-05-03 15:07:21.000000000 +0100 |
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17 | @@ -873,13 +873,19 @@ |
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18 | |
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19 | cmos_init(ram_size, boot_device, bs_table); |
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20 | |
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21 | + /* using PIIX4 acpi model */ |
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22 | + if (pci_enabled && acpi_enabled) |
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23 | + pci_piix4_acpi_init(pci_bus, piix3_devfn + 2); |
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24 | + |
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25 | if (pci_enabled && usb_enabled) { |
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26 | - usb_uhci_init(pci_bus, piix3_devfn + 2); |
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27 | + usb_uhci_init(pci_bus, piix3_devfn + (acpi_enabled ? 3 : 2)); |
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28 | } |
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29 | |
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30 | +#ifndef CONFIG_DM |
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31 | if (pci_enabled && acpi_enabled) { |
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32 | piix4_pm_init(pci_bus, piix3_devfn + 3); |
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33 | } |
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34 | +#endif /* !CONFIG_DM */ |
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35 | |
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36 | #if 0 |
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37 | /* ??? Need to figure out some way for the user to |
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38 | @@ -902,8 +908,10 @@ |
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39 | /* XXX: should be done in the Bochs BIOS */ |
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40 | if (pci_enabled) { |
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41 | pci_bios_init(); |
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42 | +#ifndef CONFIG_DM |
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43 | if (acpi_enabled) |
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44 | acpi_bios_init(); |
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45 | +#endif /* !CONFIG_DM */ |
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46 | } |
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47 | } |
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48 | |
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49 | Index: ioemu/hw/piix4acpi.c |
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50 | =================================================================== |
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51 | --- /dev/null 1970-01-01 00:00:00.000000000 +0000 |
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52 | +++ ioemu/hw/piix4acpi.c 2007-05-03 15:07:31.000000000 +0100 |
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53 | @@ -0,0 +1,186 @@ |
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54 | +/* |
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55 | + * PIIX4 ACPI controller emulation |
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56 | + * |
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57 | + * Winston liwen Wang, winston.l.wang@intel.com |
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58 | + * Copyright (c) 2006 , Intel Corporation. |
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59 | + * |
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60 | + * Permission is hereby granted, free of charge, to any person obtaining a copy |
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61 | + * of this software and associated documentation files (the "Software"), to deal |
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62 | + * in the Software without restriction, including without limitation the rights |
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63 | + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
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64 | + * copies of the Software, and to permit persons to whom the Software is |
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65 | + * furnished to do so, subject to the following conditions: |
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66 | + * |
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67 | + * The above copyright notice and this permission notice shall be included in |
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68 | + * all copies or substantial portions of the Software. |
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69 | + * |
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70 | + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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71 | + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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72 | + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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73 | + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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74 | + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
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75 | + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
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76 | + * THE SOFTWARE. |
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77 | + */ |
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78 | + |
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79 | +#include "vl.h" |
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80 | +#define FREQUENCE_PMTIMER 3753425 |
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81 | +/* acpi register bit define here */ |
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82 | + |
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83 | +/* PM1_STS */ |
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84 | +#define TMROF_STS (1 << 0) |
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85 | +#define BM_STS (1 << 4) |
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86 | +#define GBL_STS (1 << 5) |
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87 | +#define PWRBTN_STS (1 << 8) |
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88 | +#define RTC_STS (1 << 10) |
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89 | +#define PRBTNOR_STS (1 << 11) |
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90 | +#define WAK_STS (1 << 15) |
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91 | +/* PM1_EN */ |
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92 | +#define TMROF_EN (1 << 0) |
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93 | +#define GBL_EN (1 << 5) |
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94 | +#define PWRBTN_EN (1 << 8) |
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95 | +#define RTC_EN (1 << 10) |
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96 | +/* PM1_CNT */ |
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97 | +#define SCI_EN (1 << 0) |
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98 | +#define GBL_RLS (1 << 2) |
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99 | +#define SLP_EN (1 << 13) |
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100 | + |
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101 | +typedef struct AcpiDeviceState AcpiDeviceState; |
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102 | +AcpiDeviceState *acpi_device_table; |
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103 | + |
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104 | +typedef struct PCIAcpiState { |
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105 | + PCIDevice dev; |
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106 | + uint16_t pm1_control; /* pm1a_ECNT_BLK */ |
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107 | +} PCIAcpiState; |
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108 | + |
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109 | +static inline void acpi_set_irq(PCIAcpiState *s) |
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110 | +{ |
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111 | +/* no real SCI event need for now, so comment the following line out */ |
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112 | +/* pic_set_irq(s->irq, 1); */ |
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113 | + printf("acpi_set_irq: s->irq %x \n",s->irq); |
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114 | +} |
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115 | + |
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116 | +static void acpiPm1Control_writeb(void *opaque, uint32_t addr, uint32_t val) |
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117 | +{ |
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118 | + PCIAcpiState *s = opaque; |
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119 | + |
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120 | + s->pm1_control = (s->pm1_control & 0xff00) | (val & 0xff); |
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121 | +/* printf("acpiPm1Control_writeb \n addr %x val:%x\n", addr, val); */ |
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122 | + |
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123 | +} |
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124 | + |
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125 | +static uint32_t acpiPm1Control_readb(void *opaque, uint32_t addr) |
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126 | +{ |
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127 | + PCIAcpiState *s = opaque; |
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128 | + uint32_t val; |
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129 | + |
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130 | + /* Mask out the write-only bits */ |
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131 | + val = s->pm1_control & ~(GBL_RLS|SLP_EN) & 0xff; |
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132 | +/* printf("acpiPm1Control_readb \n addr %x val:%x\n", addr, val); */ |
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133 | + |
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134 | + return val; |
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135 | +} |
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136 | + |
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137 | +static void acpiPm1ControlP1_writeb(void *opaque, uint32_t addr, uint32_t val) |
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138 | +{ |
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139 | + PCIAcpiState *s = opaque; |
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140 | + |
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141 | + s->pm1_control = (s->pm1_control & 0xff) | (val << 8); |
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142 | +/* printf("acpiPm1ControlP1_writeb \n addr %x val:%x\n", addr, val); */ |
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143 | + |
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144 | +} |
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145 | + |
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146 | +static uint32_t acpiPm1ControlP1_readb(void *opaque, uint32_t addr) |
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147 | +{ |
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148 | + PCIAcpiState *s = opaque; |
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149 | + uint32_t val; |
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150 | + |
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151 | + /* Mask out the write-only bits */ |
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152 | + val = (s->pm1_control & ~(GBL_RLS|SLP_EN)) >> 8; |
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153 | +/* printf("acpiPm1ControlP1_readb \n addr %x val:%x\n", addr, val); */ |
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154 | + |
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155 | + return val; |
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156 | +} |
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157 | + |
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158 | + |
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159 | +/* word access */ |
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160 | + |
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161 | +static void acpiPm1Control_writew(void *opaque, uint32_t addr, uint32_t val) |
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162 | +{ |
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163 | + PCIAcpiState *s = opaque; |
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164 | + |
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165 | + s->pm1_control = val; |
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166 | +/* printf("acpiPm1Control_writew \n addr %x val:%x\n", addr, val); */ |
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167 | + |
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168 | +} |
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169 | + |
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170 | +static uint32_t acpiPm1Control_readw(void *opaque, uint32_t addr) |
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171 | +{ |
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172 | + PCIAcpiState *s = opaque; |
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173 | + uint32_t val; |
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174 | + |
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175 | + /* Mask out the write-only bits */ |
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176 | + val = s->pm1_control & ~(GBL_RLS|SLP_EN); |
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177 | +/* printf("acpiPm1Control_readw \n addr %x val:%x\n", addr, val); */ |
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178 | + |
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179 | + return val; |
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180 | +} |
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181 | + |
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182 | + |
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183 | +static void acpi_map(PCIDevice *pci_dev, int region_num, |
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184 | + uint32_t addr, uint32_t size, int type) |
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185 | +{ |
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186 | + PCIAcpiState *d = (PCIAcpiState *)pci_dev; |
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187 | + |
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188 | + printf("register acpi io \n"); |
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189 | + |
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190 | + /* Byte access */ |
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191 | + register_ioport_write(addr + 4, 1, 1, acpiPm1Control_writeb, d); |
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192 | + register_ioport_read(addr + 4, 1, 1, acpiPm1Control_readb, d); |
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193 | + register_ioport_write(addr + 4 + 1, 1, 1, acpiPm1ControlP1_writeb, d); |
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194 | + register_ioport_read(addr + 4 +1, 1, 1, acpiPm1ControlP1_readb, d); |
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195 | + |
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196 | + /* Word access */ |
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197 | + register_ioport_write(addr + 4, 2, 2, acpiPm1Control_writew, d); |
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198 | + register_ioport_read(addr + 4, 2, 2, acpiPm1Control_readw, d); |
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199 | +} |
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200 | + |
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201 | +/* PIIX4 acpi pci configuration space, func 2 */ |
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202 | +void pci_piix4_acpi_init(PCIBus *bus, int devfn) |
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203 | +{ |
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204 | + PCIAcpiState *d; |
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205 | + uint8_t *pci_conf; |
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206 | + |
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207 | + /* register a function 2 of PIIX4 */ |
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208 | + d = (PCIAcpiState *)pci_register_device( |
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209 | + bus, "PIIX4 ACPI", sizeof(PCIAcpiState), |
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210 | + devfn, NULL, NULL); |
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211 | + |
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212 | + pci_conf = d->dev.config; |
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213 | + pci_conf[0x00] = 0x86; /* Intel */ |
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214 | + pci_conf[0x01] = 0x80; |
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215 | + pci_conf[0x02] = 0x13; |
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216 | + pci_conf[0x03] = 0x71; |
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217 | + pci_conf[0x08] = 0x01; /* B0 stepping */ |
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218 | + pci_conf[0x09] = 0x00; /* base class */ |
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219 | + pci_conf[0x0a] = 0x80; /* Sub class */ |
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220 | + pci_conf[0x0b] = 0x06; |
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221 | + pci_conf[0x0e] = 0x00; |
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222 | + pci_conf[0x3d] = 0x01; /* Hardwired to PIRQA is used */ |
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223 | + |
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224 | + |
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225 | + /* PMBA POWER MANAGEMENT BASE ADDRESS, hardcoded to 0x1f40 |
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226 | + * to make shutdown work for IPF, due to IPF Guest Firmware |
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227 | + * will enumerate pci devices. |
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228 | + * |
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229 | + * TODO: if Guest Firmware or Guest OS will change this PMBA, |
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230 | + * More logic will be added. |
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231 | + */ |
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232 | + pci_conf[0x40] = 0x41; /* Special device-specific BAR at 0x40 */ |
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233 | + pci_conf[0x41] = 0x1f; |
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234 | + pci_conf[0x42] = 0x00; |
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235 | + pci_conf[0x43] = 0x00; |
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236 | + d->pm1_control = SCI_EN; |
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237 | + |
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238 | + acpi_map(d, 0, 0x1f40, 0x10, PCI_ADDRESS_SPACE_IO); |
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239 | +} |
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240 | Index: ioemu/vl.c |
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241 | =================================================================== |
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242 | --- ioemu.orig/vl.c 2007-05-03 15:06:42.000000000 +0100 |
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243 | +++ ioemu/vl.c 2007-05-03 15:07:21.000000000 +0100 |
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244 | @@ -157,7 +157,7 @@ |
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245 | #else |
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246 | #define MAX_CPUS 1 |
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247 | #endif |
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248 | -int acpi_enabled = 1; |
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249 | +int acpi_enabled = 0; |
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250 | int fd_bootchk = 1; |
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251 | |
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252 | extern int vcpus; |
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253 | @@ -5415,6 +5415,7 @@ |
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254 | #endif |
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255 | "-loadvm file start right away with a saved state (loadvm in monitor)\n" |
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256 | "-vnc display start a VNC server on display\n" |
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257 | + "-acpi disable or enable ACPI of HVM domain \n" |
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258 | "\n" |
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259 | "During emulation, the following keys are useful:\n" |
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260 | "ctrl-alt-f toggle full screen\n" |
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261 | @@ -5499,6 +5500,7 @@ |
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262 | |
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263 | QEMU_OPTION_d, |
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264 | QEMU_OPTION_vcpus, |
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265 | + QEMU_OPTION_acpi, |
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266 | }; |
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267 | |
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268 | typedef struct QEMUOption { |
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269 | @@ -5581,6 +5583,7 @@ |
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270 | |
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271 | { "d", HAS_ARG, QEMU_OPTION_d }, |
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272 | { "vcpus", 1, QEMU_OPTION_vcpus }, |
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273 | + { "acpi", 0, QEMU_OPTION_acpi }, |
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274 | { NULL }, |
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275 | }; |
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276 | |
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277 | @@ -6322,6 +6325,9 @@ |
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278 | vcpus = atoi(optarg); |
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279 | fprintf(logfile, "qemu: the number of cpus is %d\n", vcpus); |
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280 | break; |
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281 | + case QEMU_OPTION_acpi: |
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282 | + acpi_enabled = 1; |
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283 | + break; |
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284 | } |
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285 | } |
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286 | } |
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287 | Index: ioemu/vl.h |
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288 | =================================================================== |
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289 | --- ioemu.orig/vl.h 2007-05-03 15:06:42.000000000 +0100 |
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290 | +++ ioemu/vl.h 2007-05-03 15:07:21.000000000 +0100 |
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291 | @@ -168,6 +168,7 @@ |
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292 | extern int kqemu_allowed; |
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293 | extern int win2k_install_hack; |
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294 | extern int usb_enabled; |
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295 | +extern int acpi_enabled; |
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296 | extern int smp_cpus; |
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297 | |
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298 | /* XXX: make it dynamic */ |
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299 | @@ -924,6 +925,9 @@ |
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300 | void piix4_pm_init(PCIBus *bus, int devfn); |
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301 | void acpi_bios_init(void); |
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302 | |
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303 | +/* piix4acpi.c */ |
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304 | +extern void pci_piix4_acpi_init(PCIBus *bus, int devfn); |
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305 | + |
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306 | /* pc.c */ |
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307 | extern QEMUMachine pc_machine; |
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308 | extern QEMUMachine isapc_machine; |
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309 | Index: ioemu/hw/piix_pci.c |
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310 | =================================================================== |
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311 | --- ioemu.orig/hw/piix_pci.c 2007-05-03 15:06:42.000000000 +0100 |
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312 | +++ ioemu/hw/piix_pci.c 2007-05-03 15:07:13.000000000 +0100 |
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313 | @@ -241,7 +241,7 @@ |
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314 | static uint32_t pci_bios_io_addr; |
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315 | static uint32_t pci_bios_mem_addr; |
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316 | /* host irqs corresponding to PCI irqs A-D */ |
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317 | -static uint8_t pci_irqs[4] = { 11, 9, 11, 9 }; |
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318 | +static uint8_t pci_irqs[4] = { 10, 11, 10, 11 }; |
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319 | |
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320 | static void pci_config_writel(PCIDevice *d, uint32_t addr, uint32_t val) |
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321 | { |
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322 | @@ -336,6 +336,18 @@ |
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323 | pci_set_io_region_addr(d, 3, 0x374); |
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324 | } |
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325 | break; |
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326 | + case 0x0680: |
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327 | + if (vendor_id == 0x8086 && device_id == 0x7113) { |
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328 | + /* |
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329 | + * PIIX4 ACPI PM. |
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330 | + * Special device with special PCI config space. No ordinary BARs. |
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331 | + */ |
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332 | + pci_config_writew(d, 0x20, 0x0000); // No smb bus IO enable |
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333 | + pci_config_writew(d, 0x22, 0x0000); |
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334 | + pci_config_writew(d, 0x3c, 0x0009); // Hardcoded IRQ9 |
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335 | + pci_config_writew(d, 0x3d, 0x0001); |
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336 | + } |
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337 | + break; |
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338 | case 0x0300: |
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339 | if (vendor_id != 0x1234) |
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340 | goto default_map; |
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