1 | /* |
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2 | * QEMU Uninorth PCI host (for all Mac99 and newer machines) |
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3 | * |
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4 | * Copyright (c) 2006 Fabrice Bellard |
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5 | * |
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6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
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7 | * of this software and associated documentation files (the "Software"), to deal |
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8 | * in the Software without restriction, including without limitation the rights |
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9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
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10 | * copies of the Software, and to permit persons to whom the Software is |
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11 | * furnished to do so, subject to the following conditions: |
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12 | * |
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13 | * The above copyright notice and this permission notice shall be included in |
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14 | * all copies or substantial portions of the Software. |
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15 | * |
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16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
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21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
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22 | * THE SOFTWARE. |
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23 | */ |
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24 | #include "vl.h" |
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25 | typedef target_phys_addr_t pci_addr_t; |
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26 | #include "pci_host.h" |
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27 | |
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28 | typedef PCIHostState UNINState; |
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29 | |
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30 | static void pci_unin_main_config_writel (void *opaque, target_phys_addr_t addr, |
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31 | uint32_t val) |
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32 | { |
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33 | UNINState *s = opaque; |
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34 | int i; |
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35 | |
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36 | #ifdef TARGET_WORDS_BIGENDIAN |
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37 | val = bswap32(val); |
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38 | #endif |
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39 | |
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40 | for (i = 11; i < 32; i++) { |
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41 | if ((val & (1 << i)) != 0) |
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42 | break; |
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43 | } |
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44 | #if 0 |
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45 | s->config_reg = 0x80000000 | (1 << 16) | (val & 0x7FC) | (i << 11); |
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46 | #else |
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47 | s->config_reg = 0x80000000 | (0 << 16) | (val & 0x7FC) | (i << 11); |
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48 | #endif |
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49 | } |
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50 | |
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51 | static uint32_t pci_unin_main_config_readl (void *opaque, |
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52 | target_phys_addr_t addr) |
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53 | { |
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54 | UNINState *s = opaque; |
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55 | uint32_t val; |
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56 | int devfn; |
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57 | |
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58 | devfn = (s->config_reg >> 8) & 0xFF; |
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59 | val = (1 << (devfn >> 3)) | ((devfn & 0x07) << 8) | (s->config_reg & 0xFC); |
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60 | #ifdef TARGET_WORDS_BIGENDIAN |
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61 | val = bswap32(val); |
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62 | #endif |
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63 | |
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64 | return val; |
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65 | } |
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66 | |
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67 | static CPUWriteMemoryFunc *pci_unin_main_config_write[] = { |
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68 | &pci_unin_main_config_writel, |
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69 | &pci_unin_main_config_writel, |
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70 | &pci_unin_main_config_writel, |
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71 | }; |
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72 | |
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73 | static CPUReadMemoryFunc *pci_unin_main_config_read[] = { |
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74 | &pci_unin_main_config_readl, |
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75 | &pci_unin_main_config_readl, |
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76 | &pci_unin_main_config_readl, |
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77 | }; |
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78 | |
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79 | static CPUWriteMemoryFunc *pci_unin_main_write[] = { |
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80 | &pci_host_data_writeb, |
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81 | &pci_host_data_writew, |
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82 | &pci_host_data_writel, |
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83 | }; |
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84 | |
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85 | static CPUReadMemoryFunc *pci_unin_main_read[] = { |
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86 | &pci_host_data_readb, |
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87 | &pci_host_data_readw, |
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88 | &pci_host_data_readl, |
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89 | }; |
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90 | |
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91 | #if 0 |
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92 | |
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93 | static void pci_unin_config_writel (void *opaque, target_phys_addr_t addr, |
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94 | uint32_t val) |
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95 | { |
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96 | UNINState *s = opaque; |
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97 | |
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98 | #ifdef TARGET_WORDS_BIGENDIAN |
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99 | val = bswap32(val); |
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100 | #endif |
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101 | s->config_reg = 0x80000000 | (val & ~0x00000001); |
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102 | } |
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103 | |
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104 | static uint32_t pci_unin_config_readl (void *opaque, |
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105 | target_phys_addr_t addr) |
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106 | { |
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107 | UNINState *s = opaque; |
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108 | uint32_t val; |
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109 | |
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110 | val = (s->config_reg | 0x00000001) & ~0x80000000; |
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111 | #ifdef TARGET_WORDS_BIGENDIAN |
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112 | val = bswap32(val); |
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113 | #endif |
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114 | |
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115 | return val; |
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116 | } |
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117 | |
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118 | static CPUWriteMemoryFunc *pci_unin_config_write[] = { |
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119 | &pci_unin_config_writel, |
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120 | &pci_unin_config_writel, |
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121 | &pci_unin_config_writel, |
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122 | }; |
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123 | |
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124 | static CPUReadMemoryFunc *pci_unin_config_read[] = { |
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125 | &pci_unin_config_readl, |
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126 | &pci_unin_config_readl, |
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127 | &pci_unin_config_readl, |
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128 | }; |
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129 | |
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130 | static CPUWriteMemoryFunc *pci_unin_write[] = { |
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131 | &pci_host_pci_writeb, |
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132 | &pci_host_pci_writew, |
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133 | &pci_host_pci_writel, |
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134 | }; |
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135 | |
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136 | static CPUReadMemoryFunc *pci_unin_read[] = { |
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137 | &pci_host_pci_readb, |
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138 | &pci_host_pci_readw, |
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139 | &pci_host_pci_readl, |
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140 | }; |
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141 | #endif |
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142 | |
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143 | static void pci_unin_set_irq(PCIDevice *d, void *pic, int irq_num, int level) |
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144 | { |
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145 | openpic_set_irq(pic, d->config[PCI_INTERRUPT_LINE], level); |
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146 | } |
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147 | |
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148 | PCIBus *pci_pmac_init(void *pic) |
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149 | { |
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150 | UNINState *s; |
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151 | PCIDevice *d; |
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152 | int pci_mem_config, pci_mem_data; |
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153 | |
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154 | /* Use values found on a real PowerMac */ |
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155 | /* Uninorth main bus */ |
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156 | s = qemu_mallocz(sizeof(UNINState)); |
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157 | s->bus = pci_register_bus(pci_unin_set_irq, NULL, 11 << 3); |
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158 | |
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159 | pci_mem_config = cpu_register_io_memory(0, pci_unin_main_config_read, |
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160 | pci_unin_main_config_write, s); |
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161 | pci_mem_data = cpu_register_io_memory(0, pci_unin_main_read, |
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162 | pci_unin_main_write, s); |
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163 | cpu_register_physical_memory(0xf2800000, 0x1000, pci_mem_config); |
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164 | cpu_register_physical_memory(0xf2c00000, 0x1000, pci_mem_data); |
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165 | d = pci_register_device(s->bus, "Uni-north main", sizeof(PCIDevice), |
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166 | 11 << 3, NULL, NULL); |
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167 | d->config[0x00] = 0x6b; // vendor_id : Apple |
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168 | d->config[0x01] = 0x10; |
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169 | d->config[0x02] = 0x1F; // device_id |
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170 | d->config[0x03] = 0x00; |
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171 | d->config[0x08] = 0x00; // revision |
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172 | d->config[0x0A] = 0x00; // class_sub = pci host |
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173 | d->config[0x0B] = 0x06; // class_base = PCI_bridge |
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174 | d->config[0x0C] = 0x08; // cache_line_size |
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175 | d->config[0x0D] = 0x10; // latency_timer |
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176 | d->config[0x0E] = 0x00; // header_type |
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177 | d->config[0x34] = 0x00; // capabilities_pointer |
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178 | |
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179 | #if 0 // XXX: not activated as PPC BIOS doesn't handle mutiple buses properly |
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180 | /* pci-to-pci bridge */ |
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181 | d = pci_register_device("Uni-north bridge", sizeof(PCIDevice), 0, 13 << 3, |
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182 | NULL, NULL); |
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183 | d->config[0x00] = 0x11; // vendor_id : TI |
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184 | d->config[0x01] = 0x10; |
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185 | d->config[0x02] = 0x26; // device_id |
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186 | d->config[0x03] = 0x00; |
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187 | d->config[0x08] = 0x05; // revision |
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188 | d->config[0x0A] = 0x04; // class_sub = pci2pci |
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189 | d->config[0x0B] = 0x06; // class_base = PCI_bridge |
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190 | d->config[0x0C] = 0x08; // cache_line_size |
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191 | d->config[0x0D] = 0x20; // latency_timer |
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192 | d->config[0x0E] = 0x01; // header_type |
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193 | |
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194 | d->config[0x18] = 0x01; // primary_bus |
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195 | d->config[0x19] = 0x02; // secondary_bus |
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196 | d->config[0x1A] = 0x02; // subordinate_bus |
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197 | d->config[0x1B] = 0x20; // secondary_latency_timer |
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198 | d->config[0x1C] = 0x11; // io_base |
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199 | d->config[0x1D] = 0x01; // io_limit |
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200 | d->config[0x20] = 0x00; // memory_base |
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201 | d->config[0x21] = 0x80; |
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202 | d->config[0x22] = 0x00; // memory_limit |
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203 | d->config[0x23] = 0x80; |
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204 | d->config[0x24] = 0x01; // prefetchable_memory_base |
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205 | d->config[0x25] = 0x80; |
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206 | d->config[0x26] = 0xF1; // prefectchable_memory_limit |
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207 | d->config[0x27] = 0x7F; |
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208 | // d->config[0x34] = 0xdc // capabilities_pointer |
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209 | #endif |
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210 | #if 0 // XXX: not needed for now |
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211 | /* Uninorth AGP bus */ |
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212 | s = &pci_bridge[1]; |
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213 | pci_mem_config = cpu_register_io_memory(0, pci_unin_config_read, |
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214 | pci_unin_config_write, s); |
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215 | pci_mem_data = cpu_register_io_memory(0, pci_unin_read, |
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216 | pci_unin_write, s); |
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217 | cpu_register_physical_memory(0xf0800000, 0x1000, pci_mem_config); |
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218 | cpu_register_physical_memory(0xf0c00000, 0x1000, pci_mem_data); |
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219 | |
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220 | d = pci_register_device("Uni-north AGP", sizeof(PCIDevice), 0, 11 << 3, |
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221 | NULL, NULL); |
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222 | d->config[0x00] = 0x6b; // vendor_id : Apple |
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223 | d->config[0x01] = 0x10; |
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224 | d->config[0x02] = 0x20; // device_id |
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225 | d->config[0x03] = 0x00; |
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226 | d->config[0x08] = 0x00; // revision |
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227 | d->config[0x0A] = 0x00; // class_sub = pci host |
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228 | d->config[0x0B] = 0x06; // class_base = PCI_bridge |
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229 | d->config[0x0C] = 0x08; // cache_line_size |
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230 | d->config[0x0D] = 0x10; // latency_timer |
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231 | d->config[0x0E] = 0x00; // header_type |
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232 | // d->config[0x34] = 0x80; // capabilities_pointer |
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233 | #endif |
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234 | |
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235 | #if 0 // XXX: not needed for now |
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236 | /* Uninorth internal bus */ |
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237 | s = &pci_bridge[2]; |
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238 | pci_mem_config = cpu_register_io_memory(0, pci_unin_config_read, |
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239 | pci_unin_config_write, s); |
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240 | pci_mem_data = cpu_register_io_memory(0, pci_unin_read, |
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241 | pci_unin_write, s); |
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242 | cpu_register_physical_memory(0xf4800000, 0x1000, pci_mem_config); |
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243 | cpu_register_physical_memory(0xf4c00000, 0x1000, pci_mem_data); |
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244 | |
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245 | d = pci_register_device("Uni-north internal", sizeof(PCIDevice), |
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246 | 3, 11 << 3, NULL, NULL); |
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247 | d->config[0x00] = 0x6b; // vendor_id : Apple |
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248 | d->config[0x01] = 0x10; |
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249 | d->config[0x02] = 0x1E; // device_id |
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250 | d->config[0x03] = 0x00; |
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251 | d->config[0x08] = 0x00; // revision |
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252 | d->config[0x0A] = 0x00; // class_sub = pci host |
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253 | d->config[0x0B] = 0x06; // class_base = PCI_bridge |
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254 | d->config[0x0C] = 0x08; // cache_line_size |
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255 | d->config[0x0D] = 0x10; // latency_timer |
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256 | d->config[0x0E] = 0x00; // header_type |
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257 | d->config[0x34] = 0x00; // capabilities_pointer |
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258 | #endif |
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259 | return s->bus; |
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260 | } |
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261 | |
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