1 | /* |
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2 | * SH7750 device |
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3 | * |
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4 | * Copyright (c) 2005 Samuel Tardieu |
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5 | * |
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6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
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7 | * of this software and associated documentation files (the "Software"), to deal |
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8 | * in the Software without restriction, including without limitation the rights |
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9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
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10 | * copies of the Software, and to permit persons to whom the Software is |
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11 | * furnished to do so, subject to the following conditions: |
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12 | * |
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13 | * The above copyright notice and this permission notice shall be included in |
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14 | * all copies or substantial portions of the Software. |
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15 | * |
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16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
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21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
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22 | * THE SOFTWARE. |
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23 | */ |
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24 | #include <stdio.h> |
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25 | #include <assert.h> |
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26 | #include "vl.h" |
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27 | #include "sh7750_regs.h" |
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28 | #include "sh7750_regnames.h" |
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29 | |
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30 | typedef struct { |
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31 | uint8_t data[16]; |
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32 | uint8_t length; /* Number of characters in the FIFO */ |
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33 | uint8_t write_idx; /* Index of first character to write */ |
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34 | uint8_t read_idx; /* Index of first character to read */ |
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35 | } fifo; |
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36 | |
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37 | #define NB_DEVICES 4 |
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38 | |
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39 | typedef struct SH7750State { |
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40 | /* CPU */ |
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41 | CPUSH4State *cpu; |
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42 | /* Peripheral frequency in Hz */ |
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43 | uint32_t periph_freq; |
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44 | /* SDRAM controller */ |
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45 | uint16_t rfcr; |
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46 | /* First serial port */ |
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47 | CharDriverState *serial1; |
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48 | uint8_t scscr1; |
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49 | uint8_t scsmr1; |
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50 | uint8_t scbrr1; |
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51 | uint8_t scssr1; |
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52 | uint8_t scssr1_read; |
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53 | uint8_t sctsr1; |
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54 | uint8_t sctsr1_loaded; |
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55 | uint8_t sctdr1; |
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56 | uint8_t scrdr1; |
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57 | /* Second serial port */ |
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58 | CharDriverState *serial2; |
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59 | uint16_t sclsr2; |
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60 | uint16_t scscr2; |
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61 | uint16_t scfcr2; |
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62 | uint16_t scfsr2; |
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63 | uint16_t scsmr2; |
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64 | uint8_t scbrr2; |
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65 | fifo serial2_receive_fifo; |
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66 | fifo serial2_transmit_fifo; |
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67 | /* Timers */ |
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68 | uint8_t tstr; |
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69 | /* Timer 0 */ |
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70 | QEMUTimer *timer0; |
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71 | uint16_t tcr0; |
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72 | uint32_t tcor0; |
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73 | uint32_t tcnt0; |
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74 | /* IO ports */ |
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75 | uint16_t gpioic; |
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76 | uint32_t pctra; |
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77 | uint32_t pctrb; |
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78 | uint16_t portdira; /* Cached */ |
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79 | uint16_t portpullupa; /* Cached */ |
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80 | uint16_t portdirb; /* Cached */ |
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81 | uint16_t portpullupb; /* Cached */ |
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82 | uint16_t pdtra; |
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83 | uint16_t pdtrb; |
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84 | uint16_t periph_pdtra; /* Imposed by the peripherals */ |
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85 | uint16_t periph_portdira; /* Direction seen from the peripherals */ |
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86 | uint16_t periph_pdtrb; /* Imposed by the peripherals */ |
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87 | uint16_t periph_portdirb; /* Direction seen from the peripherals */ |
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88 | sh7750_io_device *devices[NB_DEVICES]; /* External peripherals */ |
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89 | /* Cache */ |
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90 | uint32_t ccr; |
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91 | } SH7750State; |
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92 | |
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93 | /********************************************************************** |
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94 | Timers |
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95 | **********************************************************************/ |
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96 | |
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97 | /* XXXXX At this time, timer0 works in underflow only mode, that is |
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98 | the value of tcnt0 is read at alarm computation time and cannot |
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99 | be read back by the guest OS */ |
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100 | |
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101 | static void start_timer0(SH7750State * s) |
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102 | { |
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103 | uint64_t now, next, prescaler; |
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104 | |
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105 | if ((s->tcr0 & 6) == 6) { |
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106 | fprintf(stderr, "rtc clock for timer 0 not supported\n"); |
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107 | assert(0); |
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108 | } |
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109 | |
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110 | if ((s->tcr0 & 7) == 5) { |
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111 | fprintf(stderr, "timer 0 configuration not supported\n"); |
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112 | assert(0); |
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113 | } |
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114 | |
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115 | if ((s->tcr0 & 4) == 4) |
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116 | prescaler = 1024; |
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117 | else |
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118 | prescaler = 4 << (s->tcr0 & 3); |
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119 | |
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120 | now = qemu_get_clock(vm_clock); |
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121 | /* XXXXX */ |
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122 | next = |
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123 | now + muldiv64(prescaler * s->tcnt0, ticks_per_sec, |
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124 | s->periph_freq); |
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125 | if (next == now) |
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126 | next = now + 1; |
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127 | fprintf(stderr, "now=%016" PRIx64 ", next=%016" PRIx64 "\n", now, next); |
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128 | fprintf(stderr, "timer will underflow in %f seconds\n", |
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129 | (float) (next - now) / (float) ticks_per_sec); |
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130 | |
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131 | qemu_mod_timer(s->timer0, next); |
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132 | } |
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133 | |
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134 | static void timer_start_changed(SH7750State * s) |
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135 | { |
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136 | if (s->tstr & SH7750_TSTR_STR0) { |
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137 | start_timer0(s); |
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138 | } else { |
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139 | fprintf(stderr, "timer 0 is stopped\n"); |
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140 | qemu_del_timer(s->timer0); |
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141 | } |
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142 | } |
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143 | |
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144 | static void timer0_cb(void *opaque) |
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145 | { |
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146 | SH7750State *s = opaque; |
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147 | |
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148 | s->tcnt0 = (uint32_t) 0; /* XXXXX */ |
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149 | if (--s->tcnt0 == (uint32_t) - 1) { |
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150 | fprintf(stderr, "timer 0 underflow\n"); |
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151 | s->tcnt0 = s->tcor0; |
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152 | s->tcr0 |= SH7750_TCR_UNF; |
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153 | if (s->tcr0 & SH7750_TCR_UNIE) { |
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154 | fprintf(stderr, |
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155 | "interrupt generation for timer 0 not supported\n"); |
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156 | assert(0); |
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157 | } |
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158 | } |
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159 | start_timer0(s); |
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160 | } |
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161 | |
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162 | static void init_timers(SH7750State * s) |
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163 | { |
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164 | s->tcor0 = 0xffffffff; |
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165 | s->tcnt0 = 0xffffffff; |
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166 | s->timer0 = qemu_new_timer(vm_clock, &timer0_cb, s); |
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167 | } |
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168 | |
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169 | /********************************************************************** |
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170 | First serial port |
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171 | **********************************************************************/ |
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172 | |
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173 | static int serial1_can_receive(void *opaque) |
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174 | { |
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175 | SH7750State *s = opaque; |
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176 | |
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177 | return s->scscr1 & SH7750_SCSCR_RE; |
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178 | } |
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179 | |
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180 | static void serial1_receive_char(SH7750State * s, uint8_t c) |
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181 | { |
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182 | if (s->scssr1 & SH7750_SCSSR1_RDRF) { |
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183 | s->scssr1 |= SH7750_SCSSR1_ORER; |
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184 | return; |
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185 | } |
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186 | |
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187 | s->scrdr1 = c; |
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188 | s->scssr1 |= SH7750_SCSSR1_RDRF; |
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189 | } |
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190 | |
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191 | static void serial1_receive(void *opaque, const uint8_t * buf, int size) |
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192 | { |
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193 | SH7750State *s = opaque; |
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194 | int i; |
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195 | |
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196 | for (i = 0; i < size; i++) { |
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197 | serial1_receive_char(s, buf[i]); |
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198 | } |
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199 | } |
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200 | |
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201 | static void serial1_event(void *opaque, int event) |
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202 | { |
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203 | assert(0); |
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204 | } |
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205 | |
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206 | static void serial1_maybe_send(SH7750State * s) |
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207 | { |
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208 | uint8_t c; |
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209 | |
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210 | if (s->scssr1 & SH7750_SCSSR1_TDRE) |
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211 | return; |
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212 | c = s->sctdr1; |
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213 | s->scssr1 |= SH7750_SCSSR1_TDRE | SH7750_SCSSR1_TEND; |
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214 | if (s->scscr1 & SH7750_SCSCR_TIE) { |
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215 | fprintf(stderr, "interrupts for serial port 1 not implemented\n"); |
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216 | assert(0); |
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217 | } |
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218 | /* XXXXX Check for errors in write */ |
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219 | qemu_chr_write(s->serial1, &c, 1); |
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220 | } |
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221 | |
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222 | static void serial1_change_scssr1(SH7750State * s, uint8_t mem_value) |
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223 | { |
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224 | uint8_t new_flags; |
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225 | |
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226 | /* If transmit disable, TDRE and TEND stays up */ |
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227 | if ((s->scscr1 & SH7750_SCSCR_TE) == 0) { |
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228 | mem_value |= SH7750_SCSSR1_TDRE | SH7750_SCSSR1_TEND; |
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229 | } |
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230 | |
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231 | /* Only clear bits which have been read before and do not set any bit |
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232 | in the flags */ |
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233 | new_flags = s->scssr1 & ~s->scssr1_read; /* Preserve unread flags */ |
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234 | new_flags &= mem_value | ~s->scssr1_read; /* Clear read flags */ |
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235 | |
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236 | s->scssr1 = (new_flags & 0xf8) | (mem_value & 1); |
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237 | s->scssr1_read &= mem_value; |
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238 | |
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239 | /* If TDRE has been cleared, TEND will also be cleared */ |
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240 | if ((s->scssr1 & SH7750_SCSSR1_TDRE) == 0) { |
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241 | s->scssr1 &= ~SH7750_SCSSR1_TEND; |
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242 | } |
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243 | |
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244 | /* Check for transmission to start */ |
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245 | serial1_maybe_send(s); |
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246 | } |
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247 | |
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248 | static void serial1_update_parameters(SH7750State * s) |
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249 | { |
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250 | QEMUSerialSetParams ssp; |
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251 | |
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252 | if (s->scsmr1 & SH7750_SCSMR_CHR_7) |
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253 | ssp.data_bits = 7; |
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254 | else |
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255 | ssp.data_bits = 8; |
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256 | if (s->scsmr1 & SH7750_SCSMR_PE) { |
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257 | if (s->scsmr1 & SH7750_SCSMR_PM_ODD) |
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258 | ssp.parity = 'O'; |
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259 | else |
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260 | ssp.parity = 'E'; |
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261 | } else |
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262 | ssp.parity = 'N'; |
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263 | if (s->scsmr1 & SH7750_SCSMR_STOP_2) |
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264 | ssp.stop_bits = 2; |
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265 | else |
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266 | ssp.stop_bits = 1; |
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267 | fprintf(stderr, "SCSMR1=%04x SCBRR1=%02x\n", s->scsmr1, s->scbrr1); |
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268 | ssp.speed = s->periph_freq / |
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269 | (32 * s->scbrr1 * (1 << (2 * (s->scsmr1 & 3)))) - 1; |
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270 | fprintf(stderr, "data bits=%d, stop bits=%d, parity=%c, speed=%d\n", |
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271 | ssp.data_bits, ssp.stop_bits, ssp.parity, ssp.speed); |
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272 | qemu_chr_ioctl(s->serial1, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp); |
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273 | } |
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274 | |
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275 | static void scscr1_changed(SH7750State * s) |
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276 | { |
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277 | if (s->scscr1 & (SH7750_SCSCR_TE | SH7750_SCSCR_RE)) { |
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278 | if (!s->serial1) { |
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279 | fprintf(stderr, "serial port 1 not bound to anything\n"); |
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280 | assert(0); |
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281 | } |
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282 | serial1_update_parameters(s); |
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283 | } |
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284 | if ((s->scscr1 & SH7750_SCSCR_RE) == 0) { |
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285 | s->scssr1 |= SH7750_SCSSR1_TDRE; |
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286 | } |
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287 | } |
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288 | |
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289 | static void init_serial1(SH7750State * s, int serial_nb) |
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290 | { |
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291 | CharDriverState *chr; |
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292 | |
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293 | s->scssr1 = 0x84; |
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294 | chr = serial_hds[serial_nb]; |
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295 | if (!chr) { |
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296 | fprintf(stderr, |
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297 | "no serial port associated to SH7750 first serial port\n"); |
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298 | return; |
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299 | } |
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300 | |
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301 | s->serial1 = chr; |
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302 | qemu_chr_add_read_handler(chr, serial1_can_receive, |
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303 | serial1_receive, s); |
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304 | qemu_chr_add_event_handler(chr, serial1_event); |
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305 | } |
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306 | |
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307 | /********************************************************************** |
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308 | Second serial port |
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309 | **********************************************************************/ |
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310 | |
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311 | static int serial2_can_receive(void *opaque) |
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312 | { |
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313 | SH7750State *s = opaque; |
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314 | static uint8_t max_fifo_size[] = { 15, 1, 4, 6, 8, 10, 12, 14 }; |
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315 | |
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316 | return s->serial2_receive_fifo.length < |
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317 | max_fifo_size[(s->scfcr2 >> 9) & 7]; |
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318 | } |
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319 | |
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320 | static void serial2_adjust_receive_flags(SH7750State * s) |
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321 | { |
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322 | static uint8_t max_fifo_size[] = { 1, 4, 8, 14 }; |
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323 | |
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324 | /* XXXXX Add interrupt generation */ |
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325 | if (s->serial2_receive_fifo.length >= |
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326 | max_fifo_size[(s->scfcr2 >> 7) & 3]) { |
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327 | s->scfsr2 |= SH7750_SCFSR2_RDF; |
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328 | s->scfsr2 &= ~SH7750_SCFSR2_DR; |
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329 | } else { |
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330 | s->scfsr2 &= ~SH7750_SCFSR2_RDF; |
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331 | if (s->serial2_receive_fifo.length > 0) |
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332 | s->scfsr2 |= SH7750_SCFSR2_DR; |
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333 | else |
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334 | s->scfsr2 &= ~SH7750_SCFSR2_DR; |
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335 | } |
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336 | } |
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337 | |
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338 | static void serial2_append_char(SH7750State * s, uint8_t c) |
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339 | { |
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340 | if (s->serial2_receive_fifo.length == 16) { |
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341 | /* Overflow */ |
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342 | s->sclsr2 |= SH7750_SCLSR2_ORER; |
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343 | return; |
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344 | } |
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345 | |
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346 | s->serial2_receive_fifo.data[s->serial2_receive_fifo.write_idx++] = c; |
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347 | s->serial2_receive_fifo.length++; |
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348 | serial2_adjust_receive_flags(s); |
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349 | } |
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350 | |
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351 | static void serial2_receive(void *opaque, const uint8_t * buf, int size) |
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352 | { |
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353 | SH7750State *s = opaque; |
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354 | int i; |
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355 | |
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356 | for (i = 0; i < size; i++) |
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357 | serial2_append_char(s, buf[i]); |
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358 | } |
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359 | |
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360 | static void serial2_event(void *opaque, int event) |
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361 | { |
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362 | /* XXXXX */ |
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363 | assert(0); |
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364 | } |
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365 | |
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366 | static void serial2_update_parameters(SH7750State * s) |
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367 | { |
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368 | QEMUSerialSetParams ssp; |
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369 | |
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370 | if (s->scsmr2 & SH7750_SCSMR_CHR_7) |
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371 | ssp.data_bits = 7; |
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372 | else |
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373 | ssp.data_bits = 8; |
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374 | if (s->scsmr2 & SH7750_SCSMR_PE) { |
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375 | if (s->scsmr2 & SH7750_SCSMR_PM_ODD) |
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376 | ssp.parity = 'O'; |
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377 | else |
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378 | ssp.parity = 'E'; |
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379 | } else |
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380 | ssp.parity = 'N'; |
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381 | if (s->scsmr2 & SH7750_SCSMR_STOP_2) |
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382 | ssp.stop_bits = 2; |
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383 | else |
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384 | ssp.stop_bits = 1; |
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385 | fprintf(stderr, "SCSMR2=%04x SCBRR2=%02x\n", s->scsmr2, s->scbrr2); |
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386 | ssp.speed = s->periph_freq / |
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387 | (32 * s->scbrr2 * (1 << (2 * (s->scsmr2 & 3)))) - 1; |
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388 | fprintf(stderr, "data bits=%d, stop bits=%d, parity=%c, speed=%d\n", |
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389 | ssp.data_bits, ssp.stop_bits, ssp.parity, ssp.speed); |
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390 | qemu_chr_ioctl(s->serial2, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp); |
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391 | } |
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392 | |
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393 | static void scscr2_changed(SH7750State * s) |
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394 | { |
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395 | if (s->scscr2 & (SH7750_SCSCR_TE | SH7750_SCSCR_RE)) { |
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396 | if (!s->serial2) { |
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397 | fprintf(stderr, "serial port 2 not bound to anything\n"); |
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398 | assert(0); |
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399 | } |
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400 | serial2_update_parameters(s); |
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401 | } |
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402 | } |
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403 | |
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404 | static void init_serial2(SH7750State * s, int serial_nb) |
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405 | { |
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406 | CharDriverState *chr; |
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407 | |
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408 | s->scfsr2 = 0x0060; |
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409 | |
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410 | chr = serial_hds[serial_nb]; |
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411 | if (!chr) { |
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412 | fprintf(stderr, |
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413 | "no serial port associated to SH7750 second serial port\n"); |
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414 | return; |
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415 | } |
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416 | |
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417 | s->serial2 = chr; |
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418 | qemu_chr_add_read_handler(chr, serial2_can_receive, |
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419 | serial2_receive, s); |
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420 | qemu_chr_add_event_handler(chr, serial2_event); |
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421 | } |
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422 | |
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423 | static void init_serial_ports(SH7750State * s) |
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424 | { |
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425 | init_serial1(s, 0); |
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426 | init_serial2(s, 1); |
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427 | } |
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428 | |
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429 | /********************************************************************** |
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430 | I/O ports |
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431 | **********************************************************************/ |
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432 | |
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433 | int sh7750_register_io_device(SH7750State * s, sh7750_io_device * device) |
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434 | { |
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435 | int i; |
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436 | |
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437 | for (i = 0; i < NB_DEVICES; i++) { |
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438 | if (s->devices[i] == NULL) { |
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439 | s->devices[i] = device; |
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440 | return 0; |
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441 | } |
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442 | } |
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443 | return -1; |
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444 | } |
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445 | |
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446 | static uint16_t portdir(uint32_t v) |
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447 | { |
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448 | #define EVENPORTMASK(n) ((v & (1<<((n)<<1))) >> (n)) |
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449 | return |
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450 | EVENPORTMASK(15) | EVENPORTMASK(14) | EVENPORTMASK(13) | |
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451 | EVENPORTMASK(12) | EVENPORTMASK(11) | EVENPORTMASK(10) | |
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452 | EVENPORTMASK(9) | EVENPORTMASK(8) | EVENPORTMASK(7) | |
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453 | EVENPORTMASK(6) | EVENPORTMASK(5) | EVENPORTMASK(4) | |
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454 | EVENPORTMASK(3) | EVENPORTMASK(2) | EVENPORTMASK(1) | |
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455 | EVENPORTMASK(0); |
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456 | } |
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457 | |
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458 | static uint16_t portpullup(uint32_t v) |
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459 | { |
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460 | #define ODDPORTMASK(n) ((v & (1<<(((n)<<1)+1))) >> (n)) |
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461 | return |
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462 | ODDPORTMASK(15) | ODDPORTMASK(14) | ODDPORTMASK(13) | |
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463 | ODDPORTMASK(12) | ODDPORTMASK(11) | ODDPORTMASK(10) | |
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464 | ODDPORTMASK(9) | ODDPORTMASK(8) | ODDPORTMASK(7) | ODDPORTMASK(6) | |
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465 | ODDPORTMASK(5) | ODDPORTMASK(4) | ODDPORTMASK(3) | ODDPORTMASK(2) | |
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466 | ODDPORTMASK(1) | ODDPORTMASK(0); |
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467 | } |
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468 | |
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469 | static uint16_t porta_lines(SH7750State * s) |
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470 | { |
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471 | return (s->portdira & s->pdtra) | /* CPU */ |
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472 | (s->periph_portdira & s->periph_pdtra) | /* Peripherals */ |
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473 | (~(s->portdira | s->periph_portdira) & s->portpullupa); /* Pullups */ |
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474 | } |
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475 | |
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476 | static uint16_t portb_lines(SH7750State * s) |
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477 | { |
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478 | return (s->portdirb & s->pdtrb) | /* CPU */ |
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479 | (s->periph_portdirb & s->periph_pdtrb) | /* Peripherals */ |
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480 | (~(s->portdirb | s->periph_portdirb) & s->portpullupb); /* Pullups */ |
---|
481 | } |
---|
482 | |
---|
483 | static void gen_port_interrupts(SH7750State * s) |
---|
484 | { |
---|
485 | /* XXXXX interrupts not generated */ |
---|
486 | } |
---|
487 | |
---|
488 | static void porta_changed(SH7750State * s, uint16_t prev) |
---|
489 | { |
---|
490 | uint16_t currenta, changes; |
---|
491 | int i, r = 0; |
---|
492 | |
---|
493 | #if 0 |
---|
494 | fprintf(stderr, "porta changed from 0x%04x to 0x%04x\n", |
---|
495 | prev, porta_lines(s)); |
---|
496 | fprintf(stderr, "pdtra=0x%04x, pctra=0x%08x\n", s->pdtra, s->pctra); |
---|
497 | #endif |
---|
498 | currenta = porta_lines(s); |
---|
499 | if (currenta == prev) |
---|
500 | return; |
---|
501 | changes = currenta ^ prev; |
---|
502 | |
---|
503 | for (i = 0; i < NB_DEVICES; i++) { |
---|
504 | if (s->devices[i] && (s->devices[i]->portamask_trigger & changes)) { |
---|
505 | r |= s->devices[i]->port_change_cb(currenta, portb_lines(s), |
---|
506 | &s->periph_pdtra, |
---|
507 | &s->periph_portdira, |
---|
508 | &s->periph_pdtrb, |
---|
509 | &s->periph_portdirb); |
---|
510 | } |
---|
511 | } |
---|
512 | |
---|
513 | if (r) |
---|
514 | gen_port_interrupts(s); |
---|
515 | } |
---|
516 | |
---|
517 | static void portb_changed(SH7750State * s, uint16_t prev) |
---|
518 | { |
---|
519 | uint16_t currentb, changes; |
---|
520 | int i, r = 0; |
---|
521 | |
---|
522 | currentb = portb_lines(s); |
---|
523 | if (currentb == prev) |
---|
524 | return; |
---|
525 | changes = currentb ^ prev; |
---|
526 | |
---|
527 | for (i = 0; i < NB_DEVICES; i++) { |
---|
528 | if (s->devices[i] && (s->devices[i]->portbmask_trigger & changes)) { |
---|
529 | r |= s->devices[i]->port_change_cb(portb_lines(s), currentb, |
---|
530 | &s->periph_pdtra, |
---|
531 | &s->periph_portdira, |
---|
532 | &s->periph_pdtrb, |
---|
533 | &s->periph_portdirb); |
---|
534 | } |
---|
535 | } |
---|
536 | |
---|
537 | if (r) |
---|
538 | gen_port_interrupts(s); |
---|
539 | } |
---|
540 | |
---|
541 | /********************************************************************** |
---|
542 | Memory |
---|
543 | **********************************************************************/ |
---|
544 | |
---|
545 | static void error_access(const char *kind, target_phys_addr_t addr) |
---|
546 | { |
---|
547 | fprintf(stderr, "%s to %s (0x%08x) not supported\n", |
---|
548 | kind, regname(addr), addr); |
---|
549 | } |
---|
550 | |
---|
551 | static void ignore_access(const char *kind, target_phys_addr_t addr) |
---|
552 | { |
---|
553 | fprintf(stderr, "%s to %s (0x%08x) ignored\n", |
---|
554 | kind, regname(addr), addr); |
---|
555 | } |
---|
556 | |
---|
557 | static uint32_t sh7750_mem_readb(void *opaque, target_phys_addr_t addr) |
---|
558 | { |
---|
559 | SH7750State *s = opaque; |
---|
560 | uint8_t r; |
---|
561 | |
---|
562 | switch (addr) { |
---|
563 | case SH7750_SCSSR1_A7: |
---|
564 | r = s->scssr1; |
---|
565 | s->scssr1_read |= r; |
---|
566 | return s->scssr1; |
---|
567 | case SH7750_SCRDR1_A7: |
---|
568 | s->scssr1 &= ~SH7750_SCSSR1_RDRF; |
---|
569 | return s->scrdr1; |
---|
570 | default: |
---|
571 | error_access("byte read", addr); |
---|
572 | assert(0); |
---|
573 | } |
---|
574 | } |
---|
575 | |
---|
576 | static uint32_t sh7750_mem_readw(void *opaque, target_phys_addr_t addr) |
---|
577 | { |
---|
578 | SH7750State *s = opaque; |
---|
579 | uint16_t r; |
---|
580 | |
---|
581 | switch (addr) { |
---|
582 | case SH7750_RFCR_A7: |
---|
583 | fprintf(stderr, |
---|
584 | "Read access to refresh count register, incrementing\n"); |
---|
585 | return s->rfcr++; |
---|
586 | case SH7750_TCR0_A7: |
---|
587 | return s->tcr0; |
---|
588 | case SH7750_SCLSR2_A7: |
---|
589 | /* Read and clear overflow bit */ |
---|
590 | r = s->sclsr2; |
---|
591 | s->sclsr2 = 0; |
---|
592 | return r; |
---|
593 | case SH7750_SCSFR2_A7: |
---|
594 | return s->scfsr2; |
---|
595 | case SH7750_PDTRA_A7: |
---|
596 | return porta_lines(s); |
---|
597 | case SH7750_PDTRB_A7: |
---|
598 | return portb_lines(s); |
---|
599 | default: |
---|
600 | error_access("word read", addr); |
---|
601 | assert(0); |
---|
602 | } |
---|
603 | } |
---|
604 | |
---|
605 | static uint32_t sh7750_mem_readl(void *opaque, target_phys_addr_t addr) |
---|
606 | { |
---|
607 | SH7750State *s = opaque; |
---|
608 | |
---|
609 | switch (addr) { |
---|
610 | case SH7750_MMUCR_A7: |
---|
611 | return s->cpu->mmucr; |
---|
612 | case SH7750_PTEH_A7: |
---|
613 | return s->cpu->pteh; |
---|
614 | case SH7750_PTEL_A7: |
---|
615 | return s->cpu->ptel; |
---|
616 | case SH7750_TTB_A7: |
---|
617 | return s->cpu->ttb; |
---|
618 | case SH7750_TEA_A7: |
---|
619 | return s->cpu->tea; |
---|
620 | case SH7750_TRA_A7: |
---|
621 | return s->cpu->tra; |
---|
622 | case SH7750_EXPEVT_A7: |
---|
623 | return s->cpu->expevt; |
---|
624 | case SH7750_INTEVT_A7: |
---|
625 | return s->cpu->intevt; |
---|
626 | case SH7750_CCR_A7: |
---|
627 | return s->ccr; |
---|
628 | case 0x1f000030: /* Processor version PVR */ |
---|
629 | return 0x00050000; /* SH7750R */ |
---|
630 | case 0x1f000040: /* Processor version CVR */ |
---|
631 | return 0x00110000; /* Minimum caches */ |
---|
632 | case 0x1f000044: /* Processor version PRR */ |
---|
633 | return 0x00000100; /* SH7750R */ |
---|
634 | default: |
---|
635 | error_access("long read", addr); |
---|
636 | assert(0); |
---|
637 | } |
---|
638 | } |
---|
639 | |
---|
640 | static void sh7750_mem_writeb(void *opaque, target_phys_addr_t addr, |
---|
641 | uint32_t mem_value) |
---|
642 | { |
---|
643 | SH7750State *s = opaque; |
---|
644 | |
---|
645 | switch (addr) { |
---|
646 | /* PRECHARGE ? XXXXX */ |
---|
647 | case SH7750_PRECHARGE0_A7: |
---|
648 | case SH7750_PRECHARGE1_A7: |
---|
649 | ignore_access("byte write", addr); |
---|
650 | return; |
---|
651 | case SH7750_SCBRR2_A7: |
---|
652 | s->scbrr2 = mem_value; |
---|
653 | return; |
---|
654 | case SH7750_TSTR_A7: |
---|
655 | s->tstr = mem_value; |
---|
656 | timer_start_changed(s); |
---|
657 | return; |
---|
658 | case SH7750_SCSCR1_A7: |
---|
659 | s->scscr1 = mem_value; |
---|
660 | scscr1_changed(s); |
---|
661 | return; |
---|
662 | case SH7750_SCSMR1_A7: |
---|
663 | s->scsmr1 = mem_value; |
---|
664 | return; |
---|
665 | case SH7750_SCBRR1_A7: |
---|
666 | s->scbrr1 = mem_value; |
---|
667 | return; |
---|
668 | case SH7750_SCTDR1_A7: |
---|
669 | s->scssr1 &= ~SH7750_SCSSR1_TEND; |
---|
670 | s->sctdr1 = mem_value; |
---|
671 | return; |
---|
672 | case SH7750_SCSSR1_A7: |
---|
673 | serial1_change_scssr1(s, mem_value); |
---|
674 | return; |
---|
675 | default: |
---|
676 | error_access("byte write", addr); |
---|
677 | assert(0); |
---|
678 | } |
---|
679 | } |
---|
680 | |
---|
681 | static void sh7750_mem_writew(void *opaque, target_phys_addr_t addr, |
---|
682 | uint32_t mem_value) |
---|
683 | { |
---|
684 | SH7750State *s = opaque; |
---|
685 | uint16_t temp; |
---|
686 | |
---|
687 | switch (addr) { |
---|
688 | /* SDRAM controller */ |
---|
689 | case SH7750_SCBRR1_A7: |
---|
690 | case SH7750_SCBRR2_A7: |
---|
691 | case SH7750_BCR2_A7: |
---|
692 | case SH7750_BCR3_A7: |
---|
693 | case SH7750_RTCOR_A7: |
---|
694 | case SH7750_RTCNT_A7: |
---|
695 | case SH7750_RTCSR_A7: |
---|
696 | ignore_access("word write", addr); |
---|
697 | return; |
---|
698 | /* IO ports */ |
---|
699 | case SH7750_PDTRA_A7: |
---|
700 | temp = porta_lines(s); |
---|
701 | s->pdtra = mem_value; |
---|
702 | porta_changed(s, temp); |
---|
703 | return; |
---|
704 | case SH7750_PDTRB_A7: |
---|
705 | temp = portb_lines(s); |
---|
706 | s->pdtrb = mem_value; |
---|
707 | portb_changed(s, temp); |
---|
708 | return; |
---|
709 | case SH7750_RFCR_A7: |
---|
710 | fprintf(stderr, "Write access to refresh count register\n"); |
---|
711 | s->rfcr = mem_value; |
---|
712 | return; |
---|
713 | case SH7750_SCLSR2_A7: |
---|
714 | s->sclsr2 = mem_value; |
---|
715 | return; |
---|
716 | case SH7750_SCSCR2_A7: |
---|
717 | s->scscr2 = mem_value; |
---|
718 | scscr2_changed(s); |
---|
719 | return; |
---|
720 | case SH7750_SCFCR2_A7: |
---|
721 | s->scfcr2 = mem_value; |
---|
722 | return; |
---|
723 | case SH7750_SCSMR2_A7: |
---|
724 | s->scsmr2 = mem_value; |
---|
725 | return; |
---|
726 | case SH7750_TCR0_A7: |
---|
727 | s->tcr0 = mem_value; |
---|
728 | return; |
---|
729 | case SH7750_GPIOIC_A7: |
---|
730 | s->gpioic = mem_value; |
---|
731 | if (mem_value != 0) { |
---|
732 | fprintf(stderr, "I/O interrupts not implemented\n"); |
---|
733 | assert(0); |
---|
734 | } |
---|
735 | return; |
---|
736 | default: |
---|
737 | error_access("word write", addr); |
---|
738 | assert(0); |
---|
739 | } |
---|
740 | } |
---|
741 | |
---|
742 | static void sh7750_mem_writel(void *opaque, target_phys_addr_t addr, |
---|
743 | uint32_t mem_value) |
---|
744 | { |
---|
745 | SH7750State *s = opaque; |
---|
746 | uint16_t temp; |
---|
747 | |
---|
748 | switch (addr) { |
---|
749 | /* SDRAM controller */ |
---|
750 | case SH7750_BCR1_A7: |
---|
751 | case SH7750_BCR4_A7: |
---|
752 | case SH7750_WCR1_A7: |
---|
753 | case SH7750_WCR2_A7: |
---|
754 | case SH7750_WCR3_A7: |
---|
755 | case SH7750_MCR_A7: |
---|
756 | ignore_access("long write", addr); |
---|
757 | return; |
---|
758 | /* IO ports */ |
---|
759 | case SH7750_PCTRA_A7: |
---|
760 | temp = porta_lines(s); |
---|
761 | s->pctra = mem_value; |
---|
762 | s->portdira = portdir(mem_value); |
---|
763 | s->portpullupa = portpullup(mem_value); |
---|
764 | porta_changed(s, temp); |
---|
765 | return; |
---|
766 | case SH7750_PCTRB_A7: |
---|
767 | temp = portb_lines(s); |
---|
768 | s->pctrb = mem_value; |
---|
769 | s->portdirb = portdir(mem_value); |
---|
770 | s->portpullupb = portpullup(mem_value); |
---|
771 | portb_changed(s, temp); |
---|
772 | return; |
---|
773 | case SH7750_TCNT0_A7: |
---|
774 | s->tcnt0 = mem_value & 0xf; |
---|
775 | return; |
---|
776 | case SH7750_MMUCR_A7: |
---|
777 | s->cpu->mmucr = mem_value; |
---|
778 | return; |
---|
779 | case SH7750_PTEH_A7: |
---|
780 | s->cpu->pteh = mem_value; |
---|
781 | return; |
---|
782 | case SH7750_PTEL_A7: |
---|
783 | s->cpu->ptel = mem_value; |
---|
784 | return; |
---|
785 | case SH7750_TTB_A7: |
---|
786 | s->cpu->ttb = mem_value; |
---|
787 | return; |
---|
788 | case SH7750_TEA_A7: |
---|
789 | s->cpu->tea = mem_value; |
---|
790 | return; |
---|
791 | case SH7750_TRA_A7: |
---|
792 | s->cpu->tra = mem_value & 0x000007ff; |
---|
793 | return; |
---|
794 | case SH7750_EXPEVT_A7: |
---|
795 | s->cpu->expevt = mem_value & 0x000007ff; |
---|
796 | return; |
---|
797 | case SH7750_INTEVT_A7: |
---|
798 | s->cpu->intevt = mem_value & 0x000007ff; |
---|
799 | return; |
---|
800 | case SH7750_CCR_A7: |
---|
801 | s->ccr = mem_value; |
---|
802 | return; |
---|
803 | default: |
---|
804 | error_access("long write", addr); |
---|
805 | assert(0); |
---|
806 | } |
---|
807 | } |
---|
808 | |
---|
809 | static CPUReadMemoryFunc *sh7750_mem_read[] = { |
---|
810 | sh7750_mem_readb, |
---|
811 | sh7750_mem_readw, |
---|
812 | sh7750_mem_readl |
---|
813 | }; |
---|
814 | |
---|
815 | static CPUWriteMemoryFunc *sh7750_mem_write[] = { |
---|
816 | sh7750_mem_writeb, |
---|
817 | sh7750_mem_writew, |
---|
818 | sh7750_mem_writel |
---|
819 | }; |
---|
820 | |
---|
821 | SH7750State *sh7750_init(CPUSH4State * cpu) |
---|
822 | { |
---|
823 | SH7750State *s; |
---|
824 | int sh7750_io_memory; |
---|
825 | |
---|
826 | s = qemu_mallocz(sizeof(SH7750State)); |
---|
827 | s->cpu = cpu; |
---|
828 | s->periph_freq = 60000000; /* 60MHz */ |
---|
829 | sh7750_io_memory = cpu_register_io_memory(0, |
---|
830 | sh7750_mem_read, |
---|
831 | sh7750_mem_write, s); |
---|
832 | cpu_register_physical_memory(0x1c000000, 0x04000000, sh7750_io_memory); |
---|
833 | init_timers(s); |
---|
834 | init_serial_ports(s); |
---|
835 | return s; |
---|
836 | } |
---|