1 | /* |
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2 | * QEMU 16450 UART emulation |
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3 | * |
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4 | * Copyright (c) 2003-2004 Fabrice Bellard |
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5 | * |
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6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
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7 | * of this software and associated documentation files (the "Software"), to deal |
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8 | * in the Software without restriction, including without limitation the rights |
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9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
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10 | * copies of the Software, and to permit persons to whom the Software is |
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11 | * furnished to do so, subject to the following conditions: |
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12 | * |
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13 | * The above copyright notice and this permission notice shall be included in |
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14 | * all copies or substantial portions of the Software. |
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15 | * |
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16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
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21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
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22 | * THE SOFTWARE. |
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23 | */ |
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24 | #include "vl.h" |
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25 | #include <sys/time.h> |
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26 | #include <time.h> |
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27 | #include <assert.h> |
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28 | |
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29 | //#define DEBUG_SERIAL |
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30 | |
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31 | #define UART_LCR_DLAB 0x80 /* Divisor latch access bit */ |
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32 | |
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33 | #define UART_IER_MSI 0x08 /* Enable Modem status interrupt */ |
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34 | #define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */ |
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35 | #define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */ |
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36 | #define UART_IER_RDI 0x01 /* Enable receiver data interrupt */ |
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37 | |
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38 | #define UART_IIR_NO_INT 0x01 /* No interrupts pending */ |
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39 | #define UART_IIR_ID 0x06 /* Mask for the interrupt ID */ |
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40 | |
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41 | #define UART_IIR_MSI 0x00 /* Modem status interrupt */ |
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42 | #define UART_IIR_THRI 0x02 /* Transmitter holding register empty */ |
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43 | #define UART_IIR_RDI 0x04 /* Receiver data interrupt */ |
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44 | #define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */ |
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45 | |
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46 | /* |
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47 | * These are the definitions for the Modem Control Register |
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48 | */ |
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49 | #define UART_MCR_LOOP 0x10 /* Enable loopback test mode */ |
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50 | #define UART_MCR_OUT2 0x08 /* Out2 complement */ |
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51 | #define UART_MCR_OUT1 0x04 /* Out1 complement */ |
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52 | #define UART_MCR_RTS 0x02 /* RTS complement */ |
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53 | #define UART_MCR_DTR 0x01 /* DTR complement */ |
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54 | |
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55 | /* |
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56 | * These are the definitions for the Modem Status Register |
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57 | */ |
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58 | #define UART_MSR_DCD 0x80 /* Data Carrier Detect */ |
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59 | #define UART_MSR_RI 0x40 /* Ring Indicator */ |
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60 | #define UART_MSR_DSR 0x20 /* Data Set Ready */ |
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61 | #define UART_MSR_CTS 0x10 /* Clear to Send */ |
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62 | #define UART_MSR_DDCD 0x08 /* Delta DCD */ |
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63 | #define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */ |
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64 | #define UART_MSR_DDSR 0x02 /* Delta DSR */ |
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65 | #define UART_MSR_DCTS 0x01 /* Delta CTS */ |
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66 | #define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */ |
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67 | |
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68 | #define UART_LSR_TEMT 0x40 /* Transmitter empty */ |
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69 | #define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */ |
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70 | #define UART_LSR_BI 0x10 /* Break interrupt indicator */ |
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71 | #define UART_LSR_FE 0x08 /* Frame error indicator */ |
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72 | #define UART_LSR_PE 0x04 /* Parity error indicator */ |
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73 | #define UART_LSR_OE 0x02 /* Overrun error indicator */ |
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74 | #define UART_LSR_DR 0x01 /* Receiver data ready */ |
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75 | |
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76 | /* Maximum retries for a single byte transmit. */ |
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77 | #define WRITE_MAX_SINGLE_RETRIES 3 |
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78 | /* Maximum retries for a sequence of back-to-back unsuccessful transmits. */ |
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79 | #define WRITE_MAX_TOTAL_RETRIES 10 |
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80 | |
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81 | struct SerialState { |
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82 | uint8_t divider; |
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83 | uint8_t rbr; /* receive register */ |
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84 | uint8_t ier; |
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85 | uint8_t iir; /* read only */ |
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86 | uint8_t lcr; |
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87 | uint8_t mcr; |
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88 | uint8_t lsr; /* read only */ |
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89 | uint8_t msr; /* read only */ |
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90 | uint8_t scr; |
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91 | /* NOTE: this hidden state is necessary for tx irq generation as |
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92 | it can be reset while reading iir */ |
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93 | int thr_ipending; |
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94 | SetIRQFunc *set_irq; |
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95 | void *irq_opaque; |
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96 | int irq; |
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97 | CharDriverState *chr; |
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98 | int last_break_enable; |
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99 | target_ulong base; |
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100 | int it_shift; |
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101 | |
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102 | /* |
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103 | * If a character transmitted via UART cannot be written to its |
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104 | * destination immediately we remember it here and retry a few times via |
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105 | * a polling timer. |
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106 | * - write_single_retries: Number of write retries for current byte. |
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107 | * - write_total_retries: Number of write retries for back-to-back |
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108 | * unsuccessful transmits. |
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109 | */ |
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110 | int write_single_retries; |
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111 | int write_total_retries; |
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112 | char write_chr; |
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113 | QEMUTimer *write_retry_timer; |
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114 | }; |
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115 | |
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116 | static void serial_update_irq(SerialState *s) |
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117 | { |
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118 | if ((s->lsr & UART_LSR_DR) && (s->ier & UART_IER_RDI)) { |
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119 | s->iir = UART_IIR_RDI; |
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120 | } else if (s->thr_ipending && (s->ier & UART_IER_THRI)) { |
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121 | s->iir = UART_IIR_THRI; |
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122 | } else { |
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123 | s->iir = UART_IIR_NO_INT; |
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124 | } |
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125 | if (s->iir != UART_IIR_NO_INT) { |
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126 | s->set_irq(s->irq_opaque, s->irq, 1); |
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127 | } else { |
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128 | s->set_irq(s->irq_opaque, s->irq, 0); |
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129 | } |
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130 | } |
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131 | |
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132 | static void serial_update_parameters(SerialState *s) |
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133 | { |
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134 | int speed, parity, data_bits, stop_bits; |
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135 | QEMUSerialSetParams ssp; |
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136 | |
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137 | if (s->lcr & 0x08) { |
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138 | if (s->lcr & 0x10) |
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139 | parity = 'E'; |
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140 | else |
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141 | parity = 'O'; |
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142 | } else { |
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143 | parity = 'N'; |
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144 | } |
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145 | if (s->lcr & 0x04) |
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146 | stop_bits = 2; |
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147 | else |
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148 | stop_bits = 1; |
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149 | data_bits = (s->lcr & 0x03) + 5; |
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150 | if (s->divider == 0) |
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151 | return; |
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152 | speed = 115200 / s->divider; |
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153 | ssp.speed = speed; |
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154 | ssp.parity = parity; |
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155 | ssp.data_bits = data_bits; |
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156 | ssp.stop_bits = stop_bits; |
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157 | qemu_chr_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp); |
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158 | #if 0 |
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159 | printf("speed=%d parity=%c data=%d stop=%d\n", |
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160 | speed, parity, data_bits, stop_bits); |
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161 | #endif |
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162 | } |
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163 | |
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164 | /* Rate limit serial requests so that e.g. grub on a serial console |
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165 | doesn't kill dom0. Simple token bucket. If we get some actual |
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166 | data from the user, instantly refil the bucket. */ |
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167 | |
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168 | /* How long it takes to generate a token, in microseconds. */ |
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169 | #define TOKEN_PERIOD 1000 |
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170 | /* Maximum and initial size of token bucket */ |
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171 | #define TOKENS_MAX 100000 |
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172 | |
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173 | static int tokens_avail; |
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174 | |
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175 | static void serial_get_token(void) |
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176 | { |
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177 | static struct timeval last_refil_time; |
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178 | static int started; |
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179 | |
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180 | assert(tokens_avail >= 0); |
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181 | if (!tokens_avail) { |
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182 | struct timeval delta, now; |
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183 | int generated; |
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184 | |
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185 | if (!started) { |
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186 | gettimeofday(&last_refil_time, NULL); |
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187 | tokens_avail = TOKENS_MAX; |
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188 | started = 1; |
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189 | return; |
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190 | } |
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191 | retry: |
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192 | gettimeofday(&now, NULL); |
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193 | delta.tv_sec = now.tv_sec - last_refil_time.tv_sec; |
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194 | delta.tv_usec = now.tv_usec - last_refil_time.tv_usec; |
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195 | if (delta.tv_usec < 0) { |
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196 | delta.tv_usec += 1000000; |
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197 | delta.tv_sec--; |
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198 | } |
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199 | assert(delta.tv_usec >= 0 && delta.tv_sec >= 0); |
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200 | if (delta.tv_usec < TOKEN_PERIOD) { |
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201 | struct timespec ts; |
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202 | /* Wait until at least one token is available. */ |
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203 | ts.tv_sec = TOKEN_PERIOD / 1000000; |
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204 | ts.tv_nsec = (TOKEN_PERIOD % 1000000) * 1000; |
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205 | while (nanosleep(&ts, &ts) < 0 && errno == EINTR) |
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206 | ; |
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207 | goto retry; |
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208 | } |
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209 | generated = (delta.tv_sec * 1000000) / TOKEN_PERIOD; |
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210 | generated += |
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211 | ((delta.tv_sec * 1000000) % TOKEN_PERIOD + delta.tv_usec) / TOKEN_PERIOD; |
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212 | assert(generated > 0); |
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213 | |
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214 | last_refil_time.tv_usec += (generated * TOKEN_PERIOD) % 1000000; |
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215 | last_refil_time.tv_sec += last_refil_time.tv_usec / 1000000; |
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216 | last_refil_time.tv_usec %= 1000000; |
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217 | last_refil_time.tv_sec += (generated * TOKEN_PERIOD) / 1000000; |
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218 | if (generated > TOKENS_MAX) |
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219 | generated = TOKENS_MAX; |
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220 | tokens_avail = generated; |
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221 | } |
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222 | tokens_avail--; |
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223 | } |
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224 | |
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225 | static void serial_chr_write(void *opaque) |
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226 | { |
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227 | SerialState *s = opaque; |
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228 | |
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229 | /* Cancel any outstanding retry if this is a new byte. */ |
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230 | qemu_del_timer(s->write_retry_timer); |
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231 | |
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232 | /* Retry every 100ms for 300ms total. */ |
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233 | if (qemu_chr_write(s->chr, &s->write_chr, 1) == -1) { |
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234 | s->write_total_retries++; |
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235 | if (s->write_single_retries++ >= WRITE_MAX_SINGLE_RETRIES) |
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236 | fprintf(stderr, "serial: write error\n"); |
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237 | else if (s->write_total_retries <= WRITE_MAX_TOTAL_RETRIES) { |
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238 | qemu_mod_timer(s->write_retry_timer, |
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239 | qemu_get_clock(vm_clock) + ticks_per_sec / 10); |
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240 | return; |
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241 | } |
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242 | } else { |
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243 | s->write_total_retries = 0; /* if successful then reset counter */ |
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244 | } |
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245 | |
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246 | /* Success: Notify guest that THR is empty. */ |
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247 | s->thr_ipending = 1; |
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248 | s->lsr |= UART_LSR_THRE; |
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249 | s->lsr |= UART_LSR_TEMT; |
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250 | serial_update_irq(s); |
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251 | } |
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252 | |
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253 | static void serial_ioport_write(void *opaque, uint32_t addr, uint32_t val) |
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254 | { |
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255 | SerialState *s = opaque; |
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256 | |
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257 | addr &= 7; |
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258 | #ifdef DEBUG_SERIAL |
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259 | printf("serial: write addr=0x%02x val=0x%02x\n", addr, val); |
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260 | #endif |
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261 | switch(addr) { |
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262 | default: |
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263 | case 0: |
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264 | if (s->lcr & UART_LCR_DLAB) { |
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265 | s->divider = (s->divider & 0xff00) | val; |
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266 | serial_update_parameters(s); |
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267 | } else { |
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268 | s->thr_ipending = 0; |
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269 | s->lsr &= ~UART_LSR_THRE; |
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270 | serial_update_irq(s); |
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271 | s->write_chr = val; |
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272 | s->write_single_retries = 0; |
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273 | serial_chr_write(s); |
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274 | } |
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275 | break; |
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276 | case 1: |
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277 | if (s->lcr & UART_LCR_DLAB) { |
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278 | s->divider = (s->divider & 0x00ff) | (val << 8); |
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279 | serial_update_parameters(s); |
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280 | } else { |
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281 | s->ier = val & 0x0f; |
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282 | if (s->lsr & UART_LSR_THRE) { |
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283 | s->thr_ipending = 1; |
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284 | } |
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285 | serial_update_irq(s); |
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286 | } |
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287 | break; |
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288 | case 2: |
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289 | break; |
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290 | case 3: |
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291 | { |
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292 | int break_enable; |
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293 | s->lcr = val; |
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294 | serial_update_parameters(s); |
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295 | break_enable = (val >> 6) & 1; |
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296 | if (break_enable != s->last_break_enable) { |
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297 | s->last_break_enable = break_enable; |
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298 | qemu_chr_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_BREAK, |
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299 | &break_enable); |
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300 | } |
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301 | } |
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302 | break; |
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303 | case 4: |
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304 | s->mcr = val & 0x1f; |
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305 | break; |
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306 | case 5: |
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307 | break; |
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308 | case 6: |
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309 | break; |
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310 | case 7: |
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311 | s->scr = val; |
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312 | break; |
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313 | } |
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314 | } |
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315 | |
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316 | static uint32_t serial_ioport_read(void *opaque, uint32_t addr) |
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317 | { |
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318 | SerialState *s = opaque; |
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319 | uint32_t ret; |
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320 | |
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321 | addr &= 7; |
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322 | switch(addr) { |
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323 | default: |
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324 | case 0: |
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325 | if (s->lcr & UART_LCR_DLAB) { |
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326 | ret = s->divider & 0xff; |
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327 | } else { |
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328 | ret = s->rbr; |
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329 | s->lsr &= ~(UART_LSR_DR | UART_LSR_BI); |
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330 | serial_update_irq(s); |
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331 | } |
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332 | break; |
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333 | case 1: |
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334 | if (s->lcr & UART_LCR_DLAB) { |
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335 | ret = (s->divider >> 8) & 0xff; |
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336 | } else { |
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337 | ret = s->ier; |
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338 | } |
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339 | break; |
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340 | case 2: |
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341 | ret = s->iir; |
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342 | /* reset THR pending bit */ |
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343 | if ((ret & 0x7) == UART_IIR_THRI) |
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344 | s->thr_ipending = 0; |
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345 | serial_update_irq(s); |
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346 | break; |
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347 | case 3: |
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348 | ret = s->lcr; |
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349 | break; |
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350 | case 4: |
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351 | ret = s->mcr; |
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352 | break; |
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353 | case 5: |
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354 | serial_get_token(); |
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355 | ret = s->lsr; |
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356 | break; |
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357 | case 6: |
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358 | serial_get_token(); |
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359 | if (s->mcr & UART_MCR_LOOP) { |
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360 | /* in loopback, the modem output pins are connected to the |
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361 | inputs */ |
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362 | ret = (s->mcr & 0x0c) << 4; |
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363 | ret |= (s->mcr & 0x02) << 3; |
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364 | ret |= (s->mcr & 0x01) << 5; |
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365 | } else { |
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366 | ret = s->msr; |
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367 | } |
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368 | break; |
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369 | case 7: |
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370 | ret = s->scr; |
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371 | break; |
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372 | } |
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373 | #ifdef DEBUG_SERIAL |
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374 | printf("serial: read addr=0x%02x val=0x%02x\n", addr, ret); |
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375 | #endif |
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376 | return ret; |
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377 | } |
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378 | |
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379 | static int serial_can_receive(SerialState *s) |
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380 | { |
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381 | return !(s->lsr & UART_LSR_DR); |
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382 | } |
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383 | |
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384 | static void serial_receive_byte(SerialState *s, int ch) |
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385 | { |
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386 | s->rbr = ch; |
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387 | s->lsr |= UART_LSR_DR; |
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388 | serial_update_irq(s); |
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389 | } |
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390 | |
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391 | static void serial_receive_break(SerialState *s) |
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392 | { |
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393 | s->rbr = 0; |
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394 | s->lsr |= UART_LSR_BI | UART_LSR_DR; |
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395 | serial_update_irq(s); |
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396 | } |
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397 | |
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398 | static int serial_can_receive1(void *opaque) |
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399 | { |
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400 | SerialState *s = opaque; |
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401 | return serial_can_receive(s); |
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402 | } |
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403 | |
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404 | static void serial_receive1(void *opaque, const uint8_t *buf, int size) |
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405 | { |
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406 | SerialState *s = opaque; |
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407 | tokens_avail = TOKENS_MAX; |
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408 | serial_receive_byte(s, buf[0]); |
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409 | } |
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410 | |
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411 | static void serial_event(void *opaque, int event) |
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412 | { |
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413 | SerialState *s = opaque; |
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414 | tokens_avail = TOKENS_MAX; |
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415 | if (event == CHR_EVENT_BREAK) |
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416 | serial_receive_break(s); |
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417 | } |
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418 | |
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419 | static void serial_save(QEMUFile *f, void *opaque) |
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420 | { |
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421 | SerialState *s = opaque; |
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422 | |
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423 | qemu_put_8s(f,&s->divider); |
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424 | qemu_put_8s(f,&s->rbr); |
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425 | qemu_put_8s(f,&s->ier); |
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426 | qemu_put_8s(f,&s->iir); |
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427 | qemu_put_8s(f,&s->lcr); |
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428 | qemu_put_8s(f,&s->mcr); |
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429 | qemu_put_8s(f,&s->lsr); |
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430 | qemu_put_8s(f,&s->msr); |
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431 | qemu_put_8s(f,&s->scr); |
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432 | } |
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433 | |
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434 | static int serial_load(QEMUFile *f, void *opaque, int version_id) |
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435 | { |
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436 | SerialState *s = opaque; |
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437 | |
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438 | if(version_id != 1) |
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439 | return -EINVAL; |
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440 | |
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441 | qemu_get_8s(f,&s->divider); |
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442 | qemu_get_8s(f,&s->rbr); |
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443 | qemu_get_8s(f,&s->ier); |
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444 | qemu_get_8s(f,&s->iir); |
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445 | qemu_get_8s(f,&s->lcr); |
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446 | qemu_get_8s(f,&s->mcr); |
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447 | qemu_get_8s(f,&s->lsr); |
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448 | qemu_get_8s(f,&s->msr); |
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449 | qemu_get_8s(f,&s->scr); |
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450 | |
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451 | return 0; |
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452 | } |
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453 | |
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454 | /* If fd is zero, it means that the serial device uses the console */ |
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455 | SerialState *serial_init(SetIRQFunc *set_irq, void *opaque, |
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456 | int base, int irq, CharDriverState *chr) |
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457 | { |
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458 | SerialState *s; |
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459 | |
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460 | s = qemu_mallocz(sizeof(SerialState)); |
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461 | if (!s) |
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462 | return NULL; |
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463 | s->set_irq = set_irq; |
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464 | s->irq_opaque = opaque; |
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465 | s->irq = irq; |
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466 | s->lsr = UART_LSR_TEMT | UART_LSR_THRE; |
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467 | s->iir = UART_IIR_NO_INT; |
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468 | s->msr = UART_MSR_DCD | UART_MSR_DSR | UART_MSR_CTS; |
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469 | s->write_retry_timer = qemu_new_timer(vm_clock, serial_chr_write, s); |
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470 | |
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471 | register_savevm("serial", base, 1, serial_save, serial_load, s); |
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472 | |
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473 | register_ioport_write(base, 8, 1, serial_ioport_write, s); |
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474 | register_ioport_read(base, 8, 1, serial_ioport_read, s); |
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475 | s->chr = chr; |
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476 | qemu_chr_add_read_handler(chr, serial_can_receive1, serial_receive1, s); |
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477 | qemu_chr_add_event_handler(chr, serial_event); |
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478 | return s; |
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479 | } |
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480 | |
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481 | /* Memory mapped interface */ |
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482 | static uint32_t serial_mm_readb (void *opaque, target_phys_addr_t addr) |
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483 | { |
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484 | SerialState *s = opaque; |
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485 | |
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486 | return serial_ioport_read(s, (addr - s->base) >> s->it_shift) & 0xFF; |
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487 | } |
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488 | |
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489 | static void serial_mm_writeb (void *opaque, |
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490 | target_phys_addr_t addr, uint32_t value) |
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491 | { |
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492 | SerialState *s = opaque; |
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493 | |
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494 | serial_ioport_write(s, (addr - s->base) >> s->it_shift, value & 0xFF); |
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495 | } |
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496 | |
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497 | static uint32_t serial_mm_readw (void *opaque, target_phys_addr_t addr) |
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498 | { |
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499 | SerialState *s = opaque; |
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500 | |
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501 | return serial_ioport_read(s, (addr - s->base) >> s->it_shift) & 0xFFFF; |
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502 | } |
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503 | |
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504 | static void serial_mm_writew (void *opaque, |
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505 | target_phys_addr_t addr, uint32_t value) |
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506 | { |
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507 | SerialState *s = opaque; |
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508 | |
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509 | serial_ioport_write(s, (addr - s->base) >> s->it_shift, value & 0xFFFF); |
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510 | } |
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511 | |
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512 | static uint32_t serial_mm_readl (void *opaque, target_phys_addr_t addr) |
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513 | { |
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514 | SerialState *s = opaque; |
---|
515 | |
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516 | return serial_ioport_read(s, (addr - s->base) >> s->it_shift); |
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517 | } |
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518 | |
---|
519 | static void serial_mm_writel (void *opaque, |
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520 | target_phys_addr_t addr, uint32_t value) |
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521 | { |
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522 | SerialState *s = opaque; |
---|
523 | |
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524 | serial_ioport_write(s, (addr - s->base) >> s->it_shift, value); |
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525 | } |
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526 | |
---|
527 | static CPUReadMemoryFunc *serial_mm_read[] = { |
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528 | &serial_mm_readb, |
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529 | &serial_mm_readw, |
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530 | &serial_mm_readl, |
---|
531 | }; |
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532 | |
---|
533 | static CPUWriteMemoryFunc *serial_mm_write[] = { |
---|
534 | &serial_mm_writeb, |
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535 | &serial_mm_writew, |
---|
536 | &serial_mm_writel, |
---|
537 | }; |
---|
538 | |
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539 | SerialState *serial_mm_init (SetIRQFunc *set_irq, void *opaque, |
---|
540 | target_ulong base, int it_shift, |
---|
541 | int irq, CharDriverState *chr) |
---|
542 | { |
---|
543 | SerialState *s; |
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544 | int s_io_memory; |
---|
545 | |
---|
546 | s = qemu_mallocz(sizeof(SerialState)); |
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547 | if (!s) |
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548 | return NULL; |
---|
549 | s->set_irq = set_irq; |
---|
550 | s->irq_opaque = opaque; |
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551 | s->irq = irq; |
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552 | s->lsr = UART_LSR_TEMT | UART_LSR_THRE; |
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553 | s->iir = UART_IIR_NO_INT; |
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554 | s->msr = UART_MSR_DCD | UART_MSR_DSR | UART_MSR_CTS; |
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555 | s->base = base; |
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556 | s->it_shift = it_shift; |
---|
557 | s->write_retry_timer = qemu_new_timer(vm_clock, serial_chr_write, s); |
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558 | |
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559 | register_savevm("serial", base, 1, serial_save, serial_load, s); |
---|
560 | |
---|
561 | s_io_memory = cpu_register_io_memory(0, serial_mm_read, |
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562 | serial_mm_write, s); |
---|
563 | cpu_register_physical_memory(base, 8 << it_shift, s_io_memory); |
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564 | s->chr = chr; |
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565 | qemu_chr_add_read_handler(chr, serial_can_receive1, serial_receive1, s); |
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566 | qemu_chr_add_event_handler(chr, serial_event); |
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567 | return s; |
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568 | } |
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