1 | /* |
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2 | * QEMU NE2000 emulation |
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3 | * |
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4 | * Copyright (c) 2003-2004 Fabrice Bellard |
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5 | * |
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6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
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7 | * of this software and associated documentation files (the "Software"), to deal |
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8 | * in the Software without restriction, including without limitation the rights |
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9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
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10 | * copies of the Software, and to permit persons to whom the Software is |
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11 | * furnished to do so, subject to the following conditions: |
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12 | * |
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13 | * The above copyright notice and this permission notice shall be included in |
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14 | * all copies or substantial portions of the Software. |
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15 | * |
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16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
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21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
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22 | * THE SOFTWARE. |
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23 | */ |
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24 | #include "vl.h" |
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25 | |
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26 | /* debug NE2000 card */ |
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27 | //#define DEBUG_NE2000 |
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28 | |
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29 | #define MAX_ETH_FRAME_SIZE 1514 |
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30 | |
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31 | #define E8390_CMD 0x00 /* The command register (for all pages) */ |
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32 | /* Page 0 register offsets. */ |
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33 | #define EN0_CLDALO 0x01 /* Low byte of current local dma addr RD */ |
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34 | #define EN0_STARTPG 0x01 /* Starting page of ring bfr WR */ |
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35 | #define EN0_CLDAHI 0x02 /* High byte of current local dma addr RD */ |
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36 | #define EN0_STOPPG 0x02 /* Ending page +1 of ring bfr WR */ |
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37 | #define EN0_BOUNDARY 0x03 /* Boundary page of ring bfr RD WR */ |
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38 | #define EN0_TSR 0x04 /* Transmit status reg RD */ |
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39 | #define EN0_TPSR 0x04 /* Transmit starting page WR */ |
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40 | #define EN0_NCR 0x05 /* Number of collision reg RD */ |
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41 | #define EN0_TCNTLO 0x05 /* Low byte of tx byte count WR */ |
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42 | #define EN0_FIFO 0x06 /* FIFO RD */ |
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43 | #define EN0_TCNTHI 0x06 /* High byte of tx byte count WR */ |
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44 | #define EN0_ISR 0x07 /* Interrupt status reg RD WR */ |
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45 | #define EN0_CRDALO 0x08 /* low byte of current remote dma address RD */ |
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46 | #define EN0_RSARLO 0x08 /* Remote start address reg 0 */ |
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47 | #define EN0_CRDAHI 0x09 /* high byte, current remote dma address RD */ |
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48 | #define EN0_RSARHI 0x09 /* Remote start address reg 1 */ |
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49 | #define EN0_RCNTLO 0x0a /* Remote byte count reg WR */ |
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50 | #define EN0_RTL8029ID0 0x0a /* Realtek ID byte #1 RD */ |
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51 | #define EN0_RCNTHI 0x0b /* Remote byte count reg WR */ |
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52 | #define EN0_RTL8029ID1 0x0b /* Realtek ID byte #2 RD */ |
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53 | #define EN0_RSR 0x0c /* rx status reg RD */ |
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54 | #define EN0_RXCR 0x0c /* RX configuration reg WR */ |
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55 | #define EN0_TXCR 0x0d /* TX configuration reg WR */ |
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56 | #define EN0_COUNTER0 0x0d /* Rcv alignment error counter RD */ |
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57 | #define EN0_DCFG 0x0e /* Data configuration reg WR */ |
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58 | #define EN0_COUNTER1 0x0e /* Rcv CRC error counter RD */ |
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59 | #define EN0_IMR 0x0f /* Interrupt mask reg WR */ |
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60 | #define EN0_COUNTER2 0x0f /* Rcv missed frame error counter RD */ |
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61 | |
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62 | #define EN1_PHYS 0x11 |
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63 | #define EN1_CURPAG 0x17 |
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64 | #define EN1_MULT 0x18 |
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65 | |
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66 | #define EN2_STARTPG 0x21 /* Starting page of ring bfr RD */ |
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67 | #define EN2_STOPPG 0x22 /* Ending page +1 of ring bfr RD */ |
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68 | |
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69 | #define EN3_CONFIG0 0x33 |
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70 | #define EN3_CONFIG1 0x34 |
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71 | #define EN3_CONFIG2 0x35 |
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72 | #define EN3_CONFIG3 0x36 |
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73 | |
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74 | /* Register accessed at EN_CMD, the 8390 base addr. */ |
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75 | #define E8390_STOP 0x01 /* Stop and reset the chip */ |
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76 | #define E8390_START 0x02 /* Start the chip, clear reset */ |
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77 | #define E8390_TRANS 0x04 /* Transmit a frame */ |
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78 | #define E8390_RREAD 0x08 /* Remote read */ |
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79 | #define E8390_RWRITE 0x10 /* Remote write */ |
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80 | #define E8390_NODMA 0x20 /* Remote DMA */ |
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81 | #define E8390_PAGE0 0x00 /* Select page chip registers */ |
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82 | #define E8390_PAGE1 0x40 /* using the two high-order bits */ |
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83 | #define E8390_PAGE2 0x80 /* Page 3 is invalid. */ |
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84 | |
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85 | /* Bits in EN0_ISR - Interrupt status register */ |
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86 | #define ENISR_RX 0x01 /* Receiver, no error */ |
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87 | #define ENISR_TX 0x02 /* Transmitter, no error */ |
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88 | #define ENISR_RX_ERR 0x04 /* Receiver, with error */ |
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89 | #define ENISR_TX_ERR 0x08 /* Transmitter, with error */ |
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90 | #define ENISR_OVER 0x10 /* Receiver overwrote the ring */ |
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91 | #define ENISR_COUNTERS 0x20 /* Counters need emptying */ |
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92 | #define ENISR_RDC 0x40 /* remote dma complete */ |
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93 | #define ENISR_RESET 0x80 /* Reset completed */ |
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94 | #define ENISR_ALL 0x3f /* Interrupts we will enable */ |
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95 | |
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96 | /* Bits in received packet status byte and EN0_RSR*/ |
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97 | #define ENRSR_RXOK 0x01 /* Received a good packet */ |
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98 | #define ENRSR_CRC 0x02 /* CRC error */ |
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99 | #define ENRSR_FAE 0x04 /* frame alignment error */ |
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100 | #define ENRSR_FO 0x08 /* FIFO overrun */ |
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101 | #define ENRSR_MPA 0x10 /* missed pkt */ |
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102 | #define ENRSR_PHY 0x20 /* physical/multicast address */ |
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103 | #define ENRSR_DIS 0x40 /* receiver disable. set in monitor mode */ |
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104 | #define ENRSR_DEF 0x80 /* deferring */ |
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105 | |
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106 | /* Transmitted packet status, EN0_TSR. */ |
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107 | #define ENTSR_PTX 0x01 /* Packet transmitted without error */ |
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108 | #define ENTSR_ND 0x02 /* The transmit wasn't deferred. */ |
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109 | #define ENTSR_COL 0x04 /* The transmit collided at least once. */ |
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110 | #define ENTSR_ABT 0x08 /* The transmit collided 16 times, and was deferred. */ |
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111 | #define ENTSR_CRS 0x10 /* The carrier sense was lost. */ |
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112 | #define ENTSR_FU 0x20 /* A "FIFO underrun" occurred during transmit. */ |
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113 | #define ENTSR_CDH 0x40 /* The collision detect "heartbeat" signal was lost. */ |
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114 | #define ENTSR_OWC 0x80 /* There was an out-of-window collision. */ |
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115 | |
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116 | #define NE2000_PMEM_SIZE (32*1024) |
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117 | #define NE2000_PMEM_START (16*1024) |
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118 | #define NE2000_PMEM_END (NE2000_PMEM_SIZE+NE2000_PMEM_START) |
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119 | #define NE2000_MEM_SIZE NE2000_PMEM_END |
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120 | |
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121 | typedef struct NE2000State { |
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122 | uint8_t cmd; |
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123 | uint32_t start; |
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124 | uint32_t stop; |
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125 | uint8_t boundary; |
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126 | uint8_t tsr; |
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127 | uint8_t tpsr; |
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128 | uint16_t tcnt; |
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129 | uint16_t rcnt; |
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130 | uint32_t rsar; |
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131 | uint8_t rsr; |
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132 | uint8_t rxcr; |
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133 | uint8_t isr; |
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134 | uint8_t dcfg; |
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135 | uint8_t imr; |
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136 | uint8_t phys[6]; /* mac address */ |
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137 | uint8_t curpag; |
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138 | uint8_t mult[8]; /* multicast mask array */ |
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139 | int irq; |
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140 | int tainted; |
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141 | PCIDevice *pci_dev; |
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142 | VLANClientState *vc; |
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143 | uint8_t macaddr[6]; |
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144 | uint8_t mem[NE2000_MEM_SIZE]; |
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145 | } NE2000State; |
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146 | |
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147 | static void ne2000_reset(NE2000State *s) |
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148 | { |
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149 | int i; |
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150 | |
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151 | s->isr = ENISR_RESET; |
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152 | memcpy(s->mem, s->macaddr, 6); |
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153 | s->mem[14] = 0x57; |
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154 | s->mem[15] = 0x57; |
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155 | |
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156 | /* duplicate prom data */ |
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157 | for(i = 15;i >= 0; i--) { |
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158 | s->mem[2 * i] = s->mem[i]; |
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159 | s->mem[2 * i + 1] = s->mem[i]; |
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160 | } |
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161 | } |
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162 | |
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163 | static void ne2000_update_irq(NE2000State *s) |
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164 | { |
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165 | int isr; |
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166 | isr = (s->isr & s->imr) & 0x7f; |
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167 | #if defined(DEBUG_NE2000) |
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168 | printf("NE2000: Set IRQ line %d to %d (%02x %02x)\n", |
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169 | s->irq, isr ? 1 : 0, s->isr, s->imr); |
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170 | #endif |
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171 | if (s->irq == 16) { |
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172 | /* PCI irq */ |
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173 | pci_set_irq(s->pci_dev, 0, (isr != 0)); |
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174 | } else { |
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175 | /* ISA irq */ |
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176 | pic_set_irq(s->irq, (isr != 0)); |
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177 | } |
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178 | } |
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179 | |
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180 | #define POLYNOMIAL 0x04c11db6 |
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181 | |
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182 | /* From FreeBSD */ |
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183 | /* XXX: optimize */ |
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184 | static int compute_mcast_idx(const uint8_t *ep) |
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185 | { |
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186 | uint32_t crc; |
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187 | int carry, i, j; |
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188 | uint8_t b; |
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189 | |
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190 | crc = 0xffffffff; |
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191 | for (i = 0; i < 6; i++) { |
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192 | b = *ep++; |
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193 | for (j = 0; j < 8; j++) { |
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194 | carry = ((crc & 0x80000000L) ? 1 : 0) ^ (b & 0x01); |
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195 | crc <<= 1; |
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196 | b >>= 1; |
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197 | if (carry) |
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198 | crc = ((crc ^ POLYNOMIAL) | carry); |
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199 | } |
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200 | } |
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201 | return (crc >> 26); |
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202 | } |
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203 | |
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204 | static int ne2000_buffer_full(NE2000State *s) |
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205 | { |
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206 | int avail, index, boundary; |
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207 | |
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208 | index = s->curpag << 8; |
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209 | boundary = s->boundary << 8; |
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210 | if (index <= boundary) |
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211 | avail = boundary - index; |
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212 | else |
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213 | avail = (s->stop - s->start) - (index - boundary); |
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214 | if (avail < (MAX_ETH_FRAME_SIZE + 4)) |
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215 | return 1; |
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216 | return 0; |
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217 | } |
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218 | |
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219 | static int ne2000_can_receive(void *opaque) |
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220 | { |
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221 | NE2000State *s = opaque; |
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222 | |
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223 | if (s->cmd & E8390_STOP) |
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224 | return 1; |
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225 | return !ne2000_buffer_full(s); |
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226 | } |
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227 | |
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228 | #define MIN_BUF_SIZE 60 |
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229 | |
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230 | static inline int ne2000_valid_ring_addr(NE2000State *s, unsigned int addr) |
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231 | { |
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232 | addr <<= 8; |
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233 | return addr < s->stop && addr >= s->start; |
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234 | } |
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235 | |
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236 | static inline int ne2000_check_state(NE2000State *s) |
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237 | { |
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238 | if (!s->tainted) |
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239 | return 0; |
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240 | |
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241 | if (s->start >= s->stop || s->stop > NE2000_MEM_SIZE) |
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242 | return -EINVAL; |
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243 | |
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244 | if (!ne2000_valid_ring_addr(s, s->curpag)) |
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245 | return -EINVAL; |
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246 | |
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247 | s->tainted = 0; |
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248 | return 0; |
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249 | } |
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250 | |
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251 | static void ne2000_receive(void *opaque, const uint8_t *buf, int size) |
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252 | { |
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253 | NE2000State *s = opaque; |
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254 | uint8_t *p; |
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255 | int total_len, next, avail, len, index, mcast_idx; |
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256 | uint8_t buf1[60]; |
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257 | static const uint8_t broadcast_macaddr[6] = |
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258 | { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; |
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259 | |
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260 | #if defined(DEBUG_NE2000) |
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261 | printf("NE2000: received len=%d\n", size); |
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262 | #endif |
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263 | |
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264 | if (ne2000_check_state(s)) |
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265 | return; |
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266 | |
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267 | if (!ne2000_valid_ring_addr(s, s->boundary)) |
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268 | return; |
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269 | |
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270 | if (s->cmd & E8390_STOP || ne2000_buffer_full(s)) |
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271 | return; |
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272 | |
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273 | /* XXX: check this */ |
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274 | if (s->rxcr & 0x10) { |
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275 | /* promiscuous: receive all */ |
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276 | } else { |
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277 | if (!memcmp(buf, broadcast_macaddr, 6)) { |
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278 | /* broadcast address */ |
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279 | if (!(s->rxcr & 0x04)) |
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280 | return; |
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281 | } else if (buf[0] & 0x01) { |
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282 | /* multicast */ |
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283 | if (!(s->rxcr & 0x08)) |
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284 | return; |
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285 | mcast_idx = compute_mcast_idx(buf); |
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286 | if (!(s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7)))) |
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287 | return; |
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288 | } else if (s->mem[0] == buf[0] && |
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289 | s->mem[2] == buf[1] && |
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290 | s->mem[4] == buf[2] && |
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291 | s->mem[6] == buf[3] && |
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292 | s->mem[8] == buf[4] && |
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293 | s->mem[10] == buf[5]) { |
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294 | /* match */ |
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295 | } else { |
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296 | return; |
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297 | } |
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298 | } |
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299 | |
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300 | |
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301 | /* if too small buffer, then expand it */ |
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302 | if (size < MIN_BUF_SIZE) { |
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303 | memcpy(buf1, buf, size); |
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304 | memset(buf1 + size, 0, MIN_BUF_SIZE - size); |
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305 | buf = buf1; |
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306 | size = MIN_BUF_SIZE; |
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307 | } |
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308 | |
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309 | index = s->curpag << 8; |
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310 | /* 4 bytes for header */ |
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311 | total_len = size + 4; |
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312 | /* address for next packet (4 bytes for CRC) */ |
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313 | next = index + ((total_len + 4 + 255) & ~0xff); |
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314 | if (next >= s->stop) |
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315 | next -= (s->stop - s->start); |
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316 | /* prepare packet header */ |
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317 | p = s->mem + index; |
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318 | s->rsr = ENRSR_RXOK; /* receive status */ |
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319 | /* XXX: check this */ |
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320 | if (buf[0] & 0x01) |
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321 | s->rsr |= ENRSR_PHY; |
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322 | p[0] = s->rsr; |
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323 | p[1] = next >> 8; |
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324 | p[2] = total_len; |
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325 | p[3] = total_len >> 8; |
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326 | index += 4; |
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327 | |
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328 | /* write packet data */ |
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329 | while (size > 0) { |
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330 | avail = s->stop - index; |
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331 | len = size; |
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332 | if (len > avail) |
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333 | len = avail; |
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334 | memcpy(s->mem + index, buf, len); |
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335 | buf += len; |
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336 | index += len; |
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337 | if (index == s->stop) |
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338 | index = s->start; |
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339 | size -= len; |
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340 | } |
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341 | s->curpag = next >> 8; |
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342 | |
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343 | /* now we can signal we have receive something */ |
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344 | s->isr |= ENISR_RX; |
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345 | ne2000_update_irq(s); |
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346 | } |
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347 | |
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348 | static void ne2000_ioport_write(void *opaque, uint32_t addr, uint32_t val) |
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349 | { |
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350 | NE2000State *s = opaque; |
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351 | int offset, page, index; |
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352 | |
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353 | addr &= 0xf; |
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354 | #ifdef DEBUG_NE2000 |
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355 | printf("NE2000: write addr=0x%x val=0x%02x\n", addr, val); |
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356 | #endif |
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357 | if (addr == E8390_CMD) { |
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358 | /* control register */ |
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359 | s->cmd = val; |
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360 | if (!(val & E8390_STOP)) { /* START bit makes no sense on RTL8029... */ |
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361 | s->isr &= ~ENISR_RESET; |
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362 | /* test specific case: zero length transfert */ |
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363 | if ((val & (E8390_RREAD | E8390_RWRITE)) && |
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364 | s->rcnt == 0) { |
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365 | s->isr |= ENISR_RDC; |
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366 | ne2000_update_irq(s); |
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367 | } |
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368 | if (val & E8390_TRANS) { |
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369 | index = (s->tpsr << 8); |
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370 | /* XXX: next 2 lines are a hack to make netware 3.11 work */ |
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371 | if (index >= NE2000_PMEM_END) |
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372 | index -= NE2000_PMEM_SIZE; |
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373 | /* fail safe: check range on the transmitted length */ |
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374 | if (index + s->tcnt <= NE2000_PMEM_END) { |
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375 | qemu_send_packet(s->vc, s->mem + index, s->tcnt); |
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376 | } |
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377 | /* signal end of transfert */ |
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378 | s->tsr = ENTSR_PTX; |
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379 | s->isr |= ENISR_TX; |
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380 | s->cmd &= ~E8390_TRANS; |
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381 | ne2000_update_irq(s); |
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382 | } |
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383 | } |
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384 | } else { |
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385 | page = s->cmd >> 6; |
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386 | offset = addr | (page << 4); |
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387 | switch(offset) { |
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388 | case EN0_STARTPG: |
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389 | s->start = val << 8; |
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390 | s->tainted = 1; |
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391 | break; |
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392 | case EN0_STOPPG: |
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393 | s->stop = val << 8; |
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394 | s->tainted = 1; |
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395 | break; |
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396 | case EN0_BOUNDARY: |
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397 | s->boundary = val; |
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398 | break; |
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399 | case EN0_IMR: |
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400 | s->imr = val; |
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401 | ne2000_update_irq(s); |
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402 | break; |
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403 | case EN0_TPSR: |
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404 | s->tpsr = val; |
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405 | break; |
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406 | case EN0_TCNTLO: |
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407 | s->tcnt = (s->tcnt & 0xff00) | val; |
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408 | break; |
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409 | case EN0_TCNTHI: |
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410 | s->tcnt = (s->tcnt & 0x00ff) | (val << 8); |
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411 | break; |
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412 | case EN0_RSARLO: |
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413 | s->rsar = (s->rsar & 0xff00) | val; |
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414 | break; |
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415 | case EN0_RSARHI: |
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416 | s->rsar = (s->rsar & 0x00ff) | (val << 8); |
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417 | break; |
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418 | case EN0_RCNTLO: |
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419 | s->rcnt = (s->rcnt & 0xff00) | val; |
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420 | break; |
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421 | case EN0_RCNTHI: |
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422 | s->rcnt = (s->rcnt & 0x00ff) | (val << 8); |
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423 | break; |
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424 | case EN0_RXCR: |
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425 | s->rxcr = val; |
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426 | break; |
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427 | case EN0_DCFG: |
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428 | s->dcfg = val; |
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429 | break; |
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430 | case EN0_ISR: |
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431 | s->isr &= ~(val & 0x7f); |
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432 | ne2000_update_irq(s); |
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433 | break; |
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434 | case EN1_PHYS ... EN1_PHYS + 5: |
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435 | s->phys[offset - EN1_PHYS] = val; |
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436 | break; |
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437 | case EN1_CURPAG: |
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438 | s->curpag = val; |
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439 | s->tainted = 1; |
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440 | break; |
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441 | case EN1_MULT ... EN1_MULT + 7: |
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442 | s->mult[offset - EN1_MULT] = val; |
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443 | break; |
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444 | } |
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445 | } |
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446 | } |
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447 | |
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448 | static uint32_t ne2000_ioport_read(void *opaque, uint32_t addr) |
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449 | { |
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450 | NE2000State *s = opaque; |
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451 | int offset, page, ret; |
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452 | |
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453 | addr &= 0xf; |
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454 | if (addr == E8390_CMD) { |
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455 | ret = s->cmd; |
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456 | } else { |
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457 | page = s->cmd >> 6; |
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458 | offset = addr | (page << 4); |
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459 | switch(offset) { |
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460 | case EN0_TSR: |
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461 | ret = s->tsr; |
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462 | break; |
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463 | case EN0_BOUNDARY: |
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464 | ret = s->boundary; |
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465 | break; |
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466 | case EN0_ISR: |
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467 | ret = s->isr; |
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468 | break; |
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469 | case EN0_RSARLO: |
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470 | ret = s->rsar & 0x00ff; |
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471 | break; |
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472 | case EN0_RSARHI: |
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473 | ret = s->rsar >> 8; |
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474 | break; |
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475 | case EN1_PHYS ... EN1_PHYS + 5: |
---|
476 | ret = s->phys[offset - EN1_PHYS]; |
---|
477 | break; |
---|
478 | case EN1_CURPAG: |
---|
479 | ret = s->curpag; |
---|
480 | break; |
---|
481 | case EN1_MULT ... EN1_MULT + 7: |
---|
482 | ret = s->mult[offset - EN1_MULT]; |
---|
483 | break; |
---|
484 | case EN0_RSR: |
---|
485 | ret = s->rsr; |
---|
486 | break; |
---|
487 | case EN2_STARTPG: |
---|
488 | ret = s->start >> 8; |
---|
489 | break; |
---|
490 | case EN2_STOPPG: |
---|
491 | ret = s->stop >> 8; |
---|
492 | break; |
---|
493 | case EN0_RTL8029ID0: |
---|
494 | ret = 0x50; |
---|
495 | break; |
---|
496 | case EN0_RTL8029ID1: |
---|
497 | ret = 0x43; |
---|
498 | break; |
---|
499 | case EN3_CONFIG0: |
---|
500 | ret = 0; /* 10baseT media */ |
---|
501 | break; |
---|
502 | case EN3_CONFIG2: |
---|
503 | ret = 0x40; /* 10baseT active */ |
---|
504 | break; |
---|
505 | case EN3_CONFIG3: |
---|
506 | ret = 0x40; /* Full duplex */ |
---|
507 | break; |
---|
508 | default: |
---|
509 | ret = 0x00; |
---|
510 | break; |
---|
511 | } |
---|
512 | } |
---|
513 | #ifdef DEBUG_NE2000 |
---|
514 | printf("NE2000: read addr=0x%x val=%02x\n", addr, ret); |
---|
515 | #endif |
---|
516 | return ret; |
---|
517 | } |
---|
518 | |
---|
519 | static inline void ne2000_mem_writeb(NE2000State *s, uint32_t addr, |
---|
520 | uint32_t val) |
---|
521 | { |
---|
522 | if (addr < 32 || |
---|
523 | (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) { |
---|
524 | s->mem[addr] = val; |
---|
525 | } |
---|
526 | } |
---|
527 | |
---|
528 | static inline void ne2000_mem_writew(NE2000State *s, uint32_t addr, |
---|
529 | uint32_t val) |
---|
530 | { |
---|
531 | addr &= ~1; /* XXX: check exact behaviour if not even */ |
---|
532 | if (addr < 32 || |
---|
533 | (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) { |
---|
534 | *(uint16_t *)(s->mem + addr) = cpu_to_le16(val); |
---|
535 | } |
---|
536 | } |
---|
537 | |
---|
538 | static inline void ne2000_mem_writel(NE2000State *s, uint32_t addr, |
---|
539 | uint32_t val) |
---|
540 | { |
---|
541 | addr &= ~1; /* XXX: check exact behaviour if not even */ |
---|
542 | if (addr < 32 || |
---|
543 | (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE - 2)) { |
---|
544 | cpu_to_le32wu((uint32_t *)(s->mem + addr), val); |
---|
545 | } |
---|
546 | } |
---|
547 | |
---|
548 | static inline uint32_t ne2000_mem_readb(NE2000State *s, uint32_t addr) |
---|
549 | { |
---|
550 | if (addr < 32 || |
---|
551 | (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) { |
---|
552 | return s->mem[addr]; |
---|
553 | } else { |
---|
554 | return 0xff; |
---|
555 | } |
---|
556 | } |
---|
557 | |
---|
558 | static inline uint32_t ne2000_mem_readw(NE2000State *s, uint32_t addr) |
---|
559 | { |
---|
560 | addr &= ~1; /* XXX: check exact behaviour if not even */ |
---|
561 | if (addr < 32 || |
---|
562 | (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) { |
---|
563 | return le16_to_cpu(*(uint16_t *)(s->mem + addr)); |
---|
564 | } else { |
---|
565 | return 0xffff; |
---|
566 | } |
---|
567 | } |
---|
568 | |
---|
569 | static inline uint32_t ne2000_mem_readl(NE2000State *s, uint32_t addr) |
---|
570 | { |
---|
571 | addr &= ~1; /* XXX: check exact behaviour if not even */ |
---|
572 | if (addr < 32 || |
---|
573 | (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE - 2)) { |
---|
574 | return le32_to_cpupu((uint32_t *)(s->mem + addr)); |
---|
575 | } else { |
---|
576 | return 0xffffffff; |
---|
577 | } |
---|
578 | } |
---|
579 | |
---|
580 | static inline void ne2000_dma_update(NE2000State *s, int len) |
---|
581 | { |
---|
582 | s->rsar += len; |
---|
583 | /* wrap */ |
---|
584 | /* XXX: check what to do if rsar > stop */ |
---|
585 | if (s->rsar == s->stop) |
---|
586 | s->rsar = s->start; |
---|
587 | |
---|
588 | if (s->rcnt <= len) { |
---|
589 | s->rcnt = 0; |
---|
590 | /* signal end of transfert */ |
---|
591 | s->isr |= ENISR_RDC; |
---|
592 | ne2000_update_irq(s); |
---|
593 | } else { |
---|
594 | s->rcnt -= len; |
---|
595 | } |
---|
596 | } |
---|
597 | |
---|
598 | static void ne2000_asic_ioport_write(void *opaque, uint32_t addr, uint32_t val) |
---|
599 | { |
---|
600 | NE2000State *s = opaque; |
---|
601 | |
---|
602 | #ifdef DEBUG_NE2000 |
---|
603 | printf("NE2000: asic write val=0x%04x\n", val); |
---|
604 | #endif |
---|
605 | if (s->rcnt == 0) |
---|
606 | return; |
---|
607 | if (s->dcfg & 0x01) { |
---|
608 | /* 16 bit access */ |
---|
609 | ne2000_mem_writew(s, s->rsar, val); |
---|
610 | ne2000_dma_update(s, 2); |
---|
611 | } else { |
---|
612 | /* 8 bit access */ |
---|
613 | ne2000_mem_writeb(s, s->rsar, val); |
---|
614 | ne2000_dma_update(s, 1); |
---|
615 | } |
---|
616 | } |
---|
617 | |
---|
618 | static uint32_t ne2000_asic_ioport_read(void *opaque, uint32_t addr) |
---|
619 | { |
---|
620 | NE2000State *s = opaque; |
---|
621 | int ret; |
---|
622 | |
---|
623 | if (s->dcfg & 0x01) { |
---|
624 | /* 16 bit access */ |
---|
625 | ret = ne2000_mem_readw(s, s->rsar); |
---|
626 | ne2000_dma_update(s, 2); |
---|
627 | } else { |
---|
628 | /* 8 bit access */ |
---|
629 | ret = ne2000_mem_readb(s, s->rsar); |
---|
630 | ne2000_dma_update(s, 1); |
---|
631 | } |
---|
632 | #ifdef DEBUG_NE2000 |
---|
633 | printf("NE2000: asic read val=0x%04x\n", ret); |
---|
634 | #endif |
---|
635 | return ret; |
---|
636 | } |
---|
637 | |
---|
638 | static void ne2000_asic_ioport_writel(void *opaque, uint32_t addr, uint32_t val) |
---|
639 | { |
---|
640 | NE2000State *s = opaque; |
---|
641 | |
---|
642 | #ifdef DEBUG_NE2000 |
---|
643 | printf("NE2000: asic writel val=0x%04x\n", val); |
---|
644 | #endif |
---|
645 | if (s->rcnt == 0) |
---|
646 | return; |
---|
647 | /* 32 bit access */ |
---|
648 | ne2000_mem_writel(s, s->rsar, val); |
---|
649 | ne2000_dma_update(s, 4); |
---|
650 | } |
---|
651 | |
---|
652 | static uint32_t ne2000_asic_ioport_readl(void *opaque, uint32_t addr) |
---|
653 | { |
---|
654 | NE2000State *s = opaque; |
---|
655 | int ret; |
---|
656 | |
---|
657 | /* 32 bit access */ |
---|
658 | ret = ne2000_mem_readl(s, s->rsar); |
---|
659 | ne2000_dma_update(s, 4); |
---|
660 | #ifdef DEBUG_NE2000 |
---|
661 | printf("NE2000: asic readl val=0x%04x\n", ret); |
---|
662 | #endif |
---|
663 | return ret; |
---|
664 | } |
---|
665 | |
---|
666 | static void ne2000_reset_ioport_write(void *opaque, uint32_t addr, uint32_t val) |
---|
667 | { |
---|
668 | /* nothing to do (end of reset pulse) */ |
---|
669 | } |
---|
670 | |
---|
671 | static uint32_t ne2000_reset_ioport_read(void *opaque, uint32_t addr) |
---|
672 | { |
---|
673 | NE2000State *s = opaque; |
---|
674 | ne2000_reset(s); |
---|
675 | return 0; |
---|
676 | } |
---|
677 | |
---|
678 | static void ne2000_save(QEMUFile* f,void* opaque) |
---|
679 | { |
---|
680 | NE2000State* s=(NE2000State*)opaque; |
---|
681 | |
---|
682 | qemu_put_8s(f, &s->rxcr); |
---|
683 | |
---|
684 | qemu_put_8s(f, &s->cmd); |
---|
685 | qemu_put_be32s(f, &s->start); |
---|
686 | qemu_put_be32s(f, &s->stop); |
---|
687 | qemu_put_8s(f, &s->boundary); |
---|
688 | qemu_put_8s(f, &s->tsr); |
---|
689 | qemu_put_8s(f, &s->tpsr); |
---|
690 | qemu_put_be16s(f, &s->tcnt); |
---|
691 | qemu_put_be16s(f, &s->rcnt); |
---|
692 | qemu_put_be32s(f, &s->rsar); |
---|
693 | qemu_put_8s(f, &s->rsr); |
---|
694 | qemu_put_8s(f, &s->isr); |
---|
695 | qemu_put_8s(f, &s->dcfg); |
---|
696 | qemu_put_8s(f, &s->imr); |
---|
697 | qemu_put_buffer(f, s->phys, 6); |
---|
698 | qemu_put_8s(f, &s->curpag); |
---|
699 | qemu_put_buffer(f, s->mult, 8); |
---|
700 | qemu_put_be32s(f, &s->irq); |
---|
701 | qemu_put_buffer(f, s->mem, NE2000_MEM_SIZE); |
---|
702 | } |
---|
703 | |
---|
704 | static int ne2000_load(QEMUFile* f,void* opaque,int version_id) |
---|
705 | { |
---|
706 | NE2000State* s=(NE2000State*)opaque; |
---|
707 | |
---|
708 | if (version_id == 2) { |
---|
709 | qemu_get_8s(f, &s->rxcr); |
---|
710 | } else if (version_id == 1) { |
---|
711 | s->rxcr = 0x0c; |
---|
712 | } else { |
---|
713 | return -EINVAL; |
---|
714 | } |
---|
715 | |
---|
716 | qemu_get_8s(f, &s->cmd); |
---|
717 | qemu_get_be32s(f, &s->start); |
---|
718 | qemu_get_be32s(f, &s->stop); |
---|
719 | qemu_get_8s(f, &s->boundary); |
---|
720 | qemu_get_8s(f, &s->tsr); |
---|
721 | qemu_get_8s(f, &s->tpsr); |
---|
722 | qemu_get_be16s(f, &s->tcnt); |
---|
723 | qemu_get_be16s(f, &s->rcnt); |
---|
724 | qemu_get_be32s(f, &s->rsar); |
---|
725 | qemu_get_8s(f, &s->rsr); |
---|
726 | qemu_get_8s(f, &s->isr); |
---|
727 | qemu_get_8s(f, &s->dcfg); |
---|
728 | qemu_get_8s(f, &s->imr); |
---|
729 | qemu_get_buffer(f, s->phys, 6); |
---|
730 | qemu_get_8s(f, &s->curpag); |
---|
731 | qemu_get_buffer(f, s->mult, 8); |
---|
732 | qemu_get_be32s(f, &s->irq); |
---|
733 | qemu_get_buffer(f, s->mem, NE2000_MEM_SIZE); |
---|
734 | |
---|
735 | return 0; |
---|
736 | } |
---|
737 | |
---|
738 | void isa_ne2000_init(int base, int irq, NICInfo *nd) |
---|
739 | { |
---|
740 | NE2000State *s; |
---|
741 | |
---|
742 | s = qemu_mallocz(sizeof(NE2000State)); |
---|
743 | if (!s) |
---|
744 | return; |
---|
745 | |
---|
746 | register_ioport_write(base, 16, 1, ne2000_ioport_write, s); |
---|
747 | register_ioport_read(base, 16, 1, ne2000_ioport_read, s); |
---|
748 | |
---|
749 | register_ioport_write(base + 0x10, 1, 1, ne2000_asic_ioport_write, s); |
---|
750 | register_ioport_read(base + 0x10, 1, 1, ne2000_asic_ioport_read, s); |
---|
751 | register_ioport_write(base + 0x10, 2, 2, ne2000_asic_ioport_write, s); |
---|
752 | register_ioport_read(base + 0x10, 2, 2, ne2000_asic_ioport_read, s); |
---|
753 | |
---|
754 | register_ioport_write(base + 0x1f, 1, 1, ne2000_reset_ioport_write, s); |
---|
755 | register_ioport_read(base + 0x1f, 1, 1, ne2000_reset_ioport_read, s); |
---|
756 | s->irq = irq; |
---|
757 | memcpy(s->macaddr, nd->macaddr, 6); |
---|
758 | |
---|
759 | ne2000_reset(s); |
---|
760 | |
---|
761 | s->vc = qemu_new_vlan_client(nd->vlan, ne2000_receive, |
---|
762 | ne2000_can_receive, s); |
---|
763 | |
---|
764 | snprintf(s->vc->info_str, sizeof(s->vc->info_str), |
---|
765 | "ne2000 macaddr=%02x:%02x:%02x:%02x:%02x:%02x", |
---|
766 | s->macaddr[0], |
---|
767 | s->macaddr[1], |
---|
768 | s->macaddr[2], |
---|
769 | s->macaddr[3], |
---|
770 | s->macaddr[4], |
---|
771 | s->macaddr[5]); |
---|
772 | |
---|
773 | register_savevm("ne2000", base, 2, ne2000_save, ne2000_load, s); |
---|
774 | } |
---|
775 | |
---|
776 | /***********************************************************/ |
---|
777 | /* PCI NE2000 definitions */ |
---|
778 | |
---|
779 | typedef struct PCINE2000State { |
---|
780 | PCIDevice dev; |
---|
781 | NE2000State ne2000; |
---|
782 | } PCINE2000State; |
---|
783 | |
---|
784 | static void ne2000_map(PCIDevice *pci_dev, int region_num, |
---|
785 | uint32_t addr, uint32_t size, int type) |
---|
786 | { |
---|
787 | PCINE2000State *d = (PCINE2000State *)pci_dev; |
---|
788 | NE2000State *s = &d->ne2000; |
---|
789 | |
---|
790 | register_ioport_write(addr, 16, 1, ne2000_ioport_write, s); |
---|
791 | register_ioport_read(addr, 16, 1, ne2000_ioport_read, s); |
---|
792 | |
---|
793 | register_ioport_write(addr + 0x10, 1, 1, ne2000_asic_ioport_write, s); |
---|
794 | register_ioport_read(addr + 0x10, 1, 1, ne2000_asic_ioport_read, s); |
---|
795 | register_ioport_write(addr + 0x10, 2, 2, ne2000_asic_ioport_write, s); |
---|
796 | register_ioport_read(addr + 0x10, 2, 2, ne2000_asic_ioport_read, s); |
---|
797 | register_ioport_write(addr + 0x10, 4, 4, ne2000_asic_ioport_writel, s); |
---|
798 | register_ioport_read(addr + 0x10, 4, 4, ne2000_asic_ioport_readl, s); |
---|
799 | |
---|
800 | register_ioport_write(addr + 0x1f, 1, 1, ne2000_reset_ioport_write, s); |
---|
801 | register_ioport_read(addr + 0x1f, 1, 1, ne2000_reset_ioport_read, s); |
---|
802 | } |
---|
803 | |
---|
804 | void pci_ne2000_init(PCIBus *bus, NICInfo *nd) |
---|
805 | { |
---|
806 | PCINE2000State *d; |
---|
807 | NE2000State *s; |
---|
808 | uint8_t *pci_conf; |
---|
809 | int instance; |
---|
810 | |
---|
811 | d = (PCINE2000State *)pci_register_device(bus, |
---|
812 | "NE2000", sizeof(PCINE2000State), |
---|
813 | -1, |
---|
814 | NULL, NULL); |
---|
815 | pci_conf = d->dev.config; |
---|
816 | pci_conf[0x00] = 0xec; // Realtek 8029 |
---|
817 | pci_conf[0x01] = 0x10; |
---|
818 | pci_conf[0x02] = 0x29; |
---|
819 | pci_conf[0x03] = 0x80; |
---|
820 | pci_conf[0x0a] = 0x00; // ethernet network controller |
---|
821 | pci_conf[0x0b] = 0x02; |
---|
822 | pci_conf[0x0e] = 0x00; // header_type |
---|
823 | pci_conf[0x3d] = 1; // interrupt pin 0 |
---|
824 | |
---|
825 | pci_register_io_region(&d->dev, 0, 0x100, |
---|
826 | PCI_ADDRESS_SPACE_IO, ne2000_map); |
---|
827 | s = &d->ne2000; |
---|
828 | s->irq = 16; // PCI interrupt |
---|
829 | s->pci_dev = (PCIDevice *)d; |
---|
830 | memcpy(s->macaddr, nd->macaddr, 6); |
---|
831 | ne2000_reset(s); |
---|
832 | s->vc = qemu_new_vlan_client(nd->vlan, ne2000_receive, |
---|
833 | ne2000_can_receive, s); |
---|
834 | |
---|
835 | snprintf(s->vc->info_str, sizeof(s->vc->info_str), |
---|
836 | "ne2000 pci macaddr=%02x:%02x:%02x:%02x:%02x:%02x", |
---|
837 | s->macaddr[0], |
---|
838 | s->macaddr[1], |
---|
839 | s->macaddr[2], |
---|
840 | s->macaddr[3], |
---|
841 | s->macaddr[4], |
---|
842 | s->macaddr[5]); |
---|
843 | |
---|
844 | instance = pci_bus_num(bus) << 8 | s->pci_dev->devfn; |
---|
845 | register_savevm("ne2000", instance, 2, ne2000_save, ne2000_load, s); |
---|
846 | register_savevm("ne2000_pci", instance, 1, generic_pci_save, |
---|
847 | generic_pci_load, &d->dev); |
---|
848 | } |
---|