1 | #include "vl.h" |
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2 | |
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3 | #define BIOS_FILENAME "mips_bios.bin" |
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4 | //#define BIOS_FILENAME "system.bin" |
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5 | #define KERNEL_LOAD_ADDR 0x80010000 |
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6 | #define INITRD_LOAD_ADDR 0x80800000 |
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7 | |
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8 | #define VIRT_TO_PHYS_ADDEND (-0x80000000LL) |
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9 | |
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10 | extern FILE *logfile; |
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11 | |
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12 | static PITState *pit; |
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13 | |
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14 | static void pic_irq_request(void *opaque, int level) |
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15 | { |
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16 | CPUState *env = first_cpu; |
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17 | if (level) { |
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18 | env->CP0_Cause |= 0x00000400; |
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19 | cpu_interrupt(env, CPU_INTERRUPT_HARD); |
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20 | } else { |
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21 | env->CP0_Cause &= ~0x00000400; |
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22 | cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); |
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23 | } |
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24 | } |
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25 | |
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26 | void cpu_mips_irqctrl_init (void) |
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27 | { |
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28 | } |
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29 | |
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30 | /* XXX: do not use a global */ |
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31 | uint32_t cpu_mips_get_random (CPUState *env) |
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32 | { |
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33 | static uint32_t seed = 0; |
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34 | uint32_t idx; |
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35 | seed = seed * 314159 + 1; |
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36 | idx = (seed >> 16) % (MIPS_TLB_NB - env->CP0_Wired) + env->CP0_Wired; |
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37 | return idx; |
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38 | } |
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39 | |
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40 | /* MIPS R4K timer */ |
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41 | uint32_t cpu_mips_get_count (CPUState *env) |
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42 | { |
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43 | return env->CP0_Count + |
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44 | (uint32_t)muldiv64(qemu_get_clock(vm_clock), |
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45 | 100 * 1000 * 1000, ticks_per_sec); |
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46 | } |
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47 | |
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48 | static void cpu_mips_update_count (CPUState *env, uint32_t count, |
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49 | uint32_t compare) |
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50 | { |
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51 | uint64_t now, next; |
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52 | uint32_t tmp; |
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53 | |
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54 | tmp = count; |
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55 | if (count == compare) |
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56 | tmp++; |
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57 | now = qemu_get_clock(vm_clock); |
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58 | next = now + muldiv64(compare - tmp, ticks_per_sec, 100 * 1000 * 1000); |
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59 | if (next == now) |
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60 | next++; |
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61 | #if 0 |
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62 | if (logfile) { |
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63 | fprintf(logfile, "%s: 0x%08" PRIx64 " %08x %08x => 0x%08" PRIx64 "\n", |
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64 | __func__, now, count, compare, next - now); |
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65 | } |
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66 | #endif |
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67 | /* Store new count and compare registers */ |
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68 | env->CP0_Compare = compare; |
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69 | env->CP0_Count = |
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70 | count - (uint32_t)muldiv64(now, 100 * 1000 * 1000, ticks_per_sec); |
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71 | /* Adjust timer */ |
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72 | qemu_mod_timer(env->timer, next); |
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73 | } |
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74 | |
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75 | void cpu_mips_store_count (CPUState *env, uint32_t value) |
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76 | { |
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77 | cpu_mips_update_count(env, value, env->CP0_Compare); |
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78 | } |
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79 | |
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80 | void cpu_mips_store_compare (CPUState *env, uint32_t value) |
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81 | { |
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82 | cpu_mips_update_count(env, cpu_mips_get_count(env), value); |
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83 | env->CP0_Cause &= ~0x00008000; |
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84 | cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); |
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85 | } |
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86 | |
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87 | static void mips_timer_cb (void *opaque) |
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88 | { |
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89 | CPUState *env; |
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90 | |
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91 | env = opaque; |
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92 | #if 0 |
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93 | if (logfile) { |
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94 | fprintf(logfile, "%s\n", __func__); |
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95 | } |
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96 | #endif |
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97 | cpu_mips_update_count(env, cpu_mips_get_count(env), env->CP0_Compare); |
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98 | env->CP0_Cause |= 0x00008000; |
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99 | cpu_interrupt(env, CPU_INTERRUPT_HARD); |
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100 | } |
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101 | |
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102 | void cpu_mips_clock_init (CPUState *env) |
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103 | { |
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104 | env->timer = qemu_new_timer(vm_clock, &mips_timer_cb, env); |
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105 | env->CP0_Compare = 0; |
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106 | cpu_mips_update_count(env, 1, 0); |
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107 | } |
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108 | |
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109 | |
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110 | static void io_writeb (void *opaque, target_phys_addr_t addr, uint32_t value) |
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111 | { |
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112 | #if 0 |
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113 | if (logfile) |
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114 | fprintf(logfile, "%s: addr %08x val %08x\n", __func__, addr, value); |
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115 | #endif |
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116 | cpu_outb(NULL, addr & 0xffff, value); |
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117 | } |
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118 | |
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119 | static uint32_t io_readb (void *opaque, target_phys_addr_t addr) |
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120 | { |
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121 | uint32_t ret = cpu_inb(NULL, addr & 0xffff); |
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122 | #if 0 |
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123 | if (logfile) |
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124 | fprintf(logfile, "%s: addr %08x val %08x\n", __func__, addr, ret); |
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125 | #endif |
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126 | return ret; |
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127 | } |
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128 | |
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129 | static void io_writew (void *opaque, target_phys_addr_t addr, uint32_t value) |
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130 | { |
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131 | #if 0 |
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132 | if (logfile) |
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133 | fprintf(logfile, "%s: addr %08x val %08x\n", __func__, addr, value); |
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134 | #endif |
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135 | #ifdef TARGET_WORDS_BIGENDIAN |
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136 | value = bswap16(value); |
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137 | #endif |
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138 | cpu_outw(NULL, addr & 0xffff, value); |
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139 | } |
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140 | |
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141 | static uint32_t io_readw (void *opaque, target_phys_addr_t addr) |
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142 | { |
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143 | uint32_t ret = cpu_inw(NULL, addr & 0xffff); |
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144 | #ifdef TARGET_WORDS_BIGENDIAN |
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145 | ret = bswap16(ret); |
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146 | #endif |
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147 | #if 0 |
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148 | if (logfile) |
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149 | fprintf(logfile, "%s: addr %08x val %08x\n", __func__, addr, ret); |
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150 | #endif |
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151 | return ret; |
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152 | } |
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153 | |
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154 | static void io_writel (void *opaque, target_phys_addr_t addr, uint32_t value) |
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155 | { |
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156 | #if 0 |
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157 | if (logfile) |
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158 | fprintf(logfile, "%s: addr %08x val %08x\n", __func__, addr, value); |
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159 | #endif |
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160 | #ifdef TARGET_WORDS_BIGENDIAN |
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161 | value = bswap32(value); |
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162 | #endif |
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163 | cpu_outl(NULL, addr & 0xffff, value); |
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164 | } |
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165 | |
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166 | static uint32_t io_readl (void *opaque, target_phys_addr_t addr) |
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167 | { |
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168 | uint32_t ret = cpu_inl(NULL, addr & 0xffff); |
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169 | |
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170 | #ifdef TARGET_WORDS_BIGENDIAN |
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171 | ret = bswap32(ret); |
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172 | #endif |
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173 | #if 0 |
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174 | if (logfile) |
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175 | fprintf(logfile, "%s: addr %08x val %08x\n", __func__, addr, ret); |
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176 | #endif |
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177 | return ret; |
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178 | } |
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179 | |
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180 | CPUWriteMemoryFunc *io_write[] = { |
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181 | &io_writeb, |
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182 | &io_writew, |
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183 | &io_writel, |
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184 | }; |
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185 | |
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186 | CPUReadMemoryFunc *io_read[] = { |
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187 | &io_readb, |
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188 | &io_readw, |
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189 | &io_readl, |
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190 | }; |
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191 | |
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192 | void mips_r4k_init (int ram_size, int vga_ram_size, int boot_device, |
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193 | DisplayState *ds, const char **fd_filename, int snapshot, |
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194 | const char *kernel_filename, const char *kernel_cmdline, |
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195 | const char *initrd_filename) |
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196 | { |
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197 | char buf[1024]; |
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198 | int64_t entry = 0; |
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199 | unsigned long bios_offset; |
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200 | int io_memory; |
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201 | int ret; |
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202 | CPUState *env; |
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203 | long kernel_size; |
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204 | |
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205 | env = cpu_init(); |
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206 | register_savevm("cpu", 0, 3, cpu_save, cpu_load, env); |
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207 | |
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208 | /* allocate RAM */ |
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209 | cpu_register_physical_memory(0, ram_size, IO_MEM_RAM); |
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210 | |
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211 | /* Try to load a BIOS image. If this fails, we continue regardless, |
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212 | but initialize the hardware ourselves. When a kernel gets |
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213 | preloaded we also initialize the hardware, since the BIOS wasn't |
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214 | run. */ |
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215 | bios_offset = ram_size + vga_ram_size; |
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216 | snprintf(buf, sizeof(buf), "%s/%s", bios_dir, BIOS_FILENAME); |
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217 | ret = load_image(buf, phys_ram_base + bios_offset); |
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218 | if (ret == BIOS_SIZE) { |
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219 | cpu_register_physical_memory((uint32_t)(0x1fc00000), |
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220 | BIOS_SIZE, bios_offset | IO_MEM_ROM); |
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221 | } else { |
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222 | /* not fatal */ |
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223 | fprintf(stderr, "qemu: Warning, could not load MIPS bios '%s'\n", |
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224 | buf); |
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225 | } |
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226 | |
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227 | kernel_size = 0; |
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228 | if (kernel_filename) { |
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229 | kernel_size = load_elf(kernel_filename, VIRT_TO_PHYS_ADDEND, &entry); |
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230 | if (kernel_size >= 0) |
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231 | env->PC = entry; |
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232 | else { |
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233 | kernel_size = load_image(kernel_filename, |
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234 | phys_ram_base + KERNEL_LOAD_ADDR + VIRT_TO_PHYS_ADDEND); |
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235 | if (kernel_size < 0) { |
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236 | fprintf(stderr, "qemu: could not load kernel '%s'\n", |
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237 | kernel_filename); |
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238 | exit(1); |
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239 | } |
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240 | env->PC = KERNEL_LOAD_ADDR; |
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241 | } |
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242 | |
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243 | /* load initrd */ |
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244 | if (initrd_filename) { |
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245 | if (load_image(initrd_filename, |
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246 | phys_ram_base + INITRD_LOAD_ADDR + VIRT_TO_PHYS_ADDEND) |
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247 | == (target_ulong) -1) { |
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248 | fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", |
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249 | initrd_filename); |
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250 | exit(1); |
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251 | } |
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252 | } |
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253 | |
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254 | /* Store command line. */ |
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255 | strcpy (phys_ram_base + (16 << 20) - 256, kernel_cmdline); |
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256 | /* FIXME: little endian support */ |
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257 | *(int *)(phys_ram_base + (16 << 20) - 260) = tswap32 (0x12345678); |
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258 | *(int *)(phys_ram_base + (16 << 20) - 264) = tswap32 (ram_size); |
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259 | } |
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260 | |
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261 | /* Init internal devices */ |
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262 | cpu_mips_clock_init(env); |
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263 | cpu_mips_irqctrl_init(); |
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264 | |
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265 | /* Register 64 KB of ISA IO space at 0x14000000 */ |
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266 | io_memory = cpu_register_io_memory(0, io_read, io_write, NULL); |
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267 | cpu_register_physical_memory(0x14000000, 0x00010000, io_memory); |
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268 | isa_mem_base = 0x10000000; |
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269 | |
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270 | isa_pic = pic_init(pic_irq_request, env); |
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271 | pit = pit_init(0x40, 0); |
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272 | serial_init(&pic_set_irq_new, isa_pic, 0x3f8, 4, serial_hds[0]); |
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273 | vga_initialize(NULL, ds, phys_ram_base + ram_size, ram_size, |
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274 | vga_ram_size, 0, 0); |
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275 | |
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276 | if (nd_table[0].vlan) { |
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277 | if (nd_table[0].model == NULL |
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278 | || strcmp(nd_table[0].model, "ne2k_isa") == 0) { |
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279 | isa_ne2000_init(0x300, 9, &nd_table[0]); |
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280 | } else { |
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281 | fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model); |
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282 | exit (1); |
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283 | } |
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284 | } |
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285 | } |
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286 | |
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287 | QEMUMachine mips_machine = { |
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288 | "mips", |
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289 | "mips r4k platform", |
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290 | mips_r4k_init, |
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291 | }; |
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