1 | /* |
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2 | * QEMU MC146818 RTC emulation |
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3 | * |
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4 | * Copyright (c) 2003-2004 Fabrice Bellard |
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5 | * |
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6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
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7 | * of this software and associated documentation files (the "Software"), to deal |
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8 | * in the Software without restriction, including without limitation the rights |
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9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
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10 | * copies of the Software, and to permit persons to whom the Software is |
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11 | * furnished to do so, subject to the following conditions: |
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12 | * |
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13 | * The above copyright notice and this permission notice shall be included in |
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14 | * all copies or substantial portions of the Software. |
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15 | * |
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16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
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21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
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22 | * THE SOFTWARE. |
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23 | */ |
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24 | #include "vl.h" |
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25 | |
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26 | //#define DEBUG_CMOS |
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27 | |
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28 | #define RTC_SECONDS 0 |
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29 | #define RTC_SECONDS_ALARM 1 |
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30 | #define RTC_MINUTES 2 |
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31 | #define RTC_MINUTES_ALARM 3 |
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32 | #define RTC_HOURS 4 |
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33 | #define RTC_HOURS_ALARM 5 |
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34 | #define RTC_ALARM_DONT_CARE 0xC0 |
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35 | |
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36 | #define RTC_DAY_OF_WEEK 6 |
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37 | #define RTC_DAY_OF_MONTH 7 |
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38 | #define RTC_MONTH 8 |
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39 | #define RTC_YEAR 9 |
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40 | |
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41 | #define RTC_REG_A 10 |
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42 | #define RTC_REG_B 11 |
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43 | #define RTC_REG_C 12 |
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44 | #define RTC_REG_D 13 |
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45 | |
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46 | #define REG_A_UIP 0x80 |
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47 | |
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48 | #define REG_B_SET 0x80 |
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49 | #define REG_B_PIE 0x40 |
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50 | #define REG_B_AIE 0x20 |
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51 | #define REG_B_UIE 0x10 |
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52 | |
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53 | struct RTCState { |
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54 | uint8_t cmos_data[128]; |
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55 | uint8_t cmos_index; |
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56 | struct tm current_tm; |
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57 | int irq; |
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58 | /* periodic timer */ |
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59 | QEMUTimer *periodic_timer; |
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60 | int64_t next_periodic_time; |
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61 | /* second update */ |
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62 | int64_t next_second_time; |
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63 | QEMUTimer *second_timer; |
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64 | QEMUTimer *second_timer2; |
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65 | }; |
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66 | |
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67 | static void rtc_set_time(RTCState *s); |
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68 | static void rtc_copy_date(RTCState *s); |
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69 | |
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70 | static void rtc_timer_update(RTCState *s, int64_t current_time) |
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71 | { |
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72 | int period_code, period; |
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73 | int64_t cur_clock, next_irq_clock; |
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74 | |
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75 | period_code = s->cmos_data[RTC_REG_A] & 0x0f; |
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76 | if (period_code != 0 && |
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77 | (s->cmos_data[RTC_REG_B] & REG_B_PIE)) { |
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78 | if (period_code <= 2) |
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79 | period_code += 7; |
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80 | /* period in 32 Khz cycles */ |
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81 | period = 1 << (period_code - 1); |
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82 | /* compute 32 khz clock */ |
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83 | cur_clock = muldiv64(current_time, 32768, ticks_per_sec); |
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84 | next_irq_clock = (cur_clock & ~(period - 1)) + period; |
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85 | s->next_periodic_time = muldiv64(next_irq_clock, ticks_per_sec, 32768) + 1; |
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86 | qemu_mod_timer(s->periodic_timer, s->next_periodic_time); |
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87 | } else { |
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88 | qemu_del_timer(s->periodic_timer); |
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89 | } |
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90 | } |
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91 | |
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92 | static void rtc_periodic_timer(void *opaque) |
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93 | { |
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94 | RTCState *s = opaque; |
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95 | |
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96 | rtc_timer_update(s, s->next_periodic_time); |
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97 | s->cmos_data[RTC_REG_C] |= 0xc0; |
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98 | pic_set_irq(s->irq, 1); |
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99 | } |
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100 | |
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101 | static void cmos_ioport_write(void *opaque, uint32_t addr, uint32_t data) |
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102 | { |
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103 | RTCState *s = opaque; |
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104 | |
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105 | if ((addr & 1) == 0) { |
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106 | s->cmos_index = data & 0x7f; |
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107 | } else { |
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108 | #ifdef DEBUG_CMOS |
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109 | printf("cmos: write index=0x%02x val=0x%02x\n", |
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110 | s->cmos_index, data); |
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111 | #endif |
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112 | switch(s->cmos_index) { |
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113 | case RTC_SECONDS_ALARM: |
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114 | case RTC_MINUTES_ALARM: |
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115 | case RTC_HOURS_ALARM: |
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116 | /* XXX: not supported */ |
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117 | s->cmos_data[s->cmos_index] = data; |
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118 | break; |
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119 | case RTC_SECONDS: |
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120 | case RTC_MINUTES: |
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121 | case RTC_HOURS: |
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122 | case RTC_DAY_OF_WEEK: |
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123 | case RTC_DAY_OF_MONTH: |
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124 | case RTC_MONTH: |
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125 | case RTC_YEAR: |
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126 | s->cmos_data[s->cmos_index] = data; |
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127 | /* if in set mode, do not update the time */ |
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128 | if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) { |
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129 | rtc_set_time(s); |
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130 | } |
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131 | break; |
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132 | case RTC_REG_A: |
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133 | /* UIP bit is read only */ |
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134 | s->cmos_data[RTC_REG_A] = (data & ~REG_A_UIP) | |
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135 | (s->cmos_data[RTC_REG_A] & REG_A_UIP); |
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136 | rtc_timer_update(s, qemu_get_clock(vm_clock)); |
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137 | break; |
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138 | case RTC_REG_B: |
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139 | if (data & REG_B_SET) { |
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140 | /* set mode: reset UIP mode */ |
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141 | s->cmos_data[RTC_REG_A] &= ~REG_A_UIP; |
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142 | data &= ~REG_B_UIE; |
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143 | } else { |
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144 | /* if disabling set mode, update the time */ |
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145 | if (s->cmos_data[RTC_REG_B] & REG_B_SET) { |
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146 | rtc_set_time(s); |
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147 | } |
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148 | } |
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149 | s->cmos_data[RTC_REG_B] = data; |
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150 | rtc_timer_update(s, qemu_get_clock(vm_clock)); |
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151 | break; |
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152 | case RTC_REG_C: |
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153 | case RTC_REG_D: |
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154 | /* cannot write to them */ |
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155 | break; |
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156 | default: |
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157 | s->cmos_data[s->cmos_index] = data; |
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158 | break; |
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159 | } |
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160 | } |
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161 | } |
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162 | |
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163 | static inline int to_bcd(RTCState *s, int a) |
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164 | { |
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165 | if (s->cmos_data[RTC_REG_B] & 0x04) { |
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166 | return a; |
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167 | } else { |
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168 | return ((a / 10) << 4) | (a % 10); |
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169 | } |
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170 | } |
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171 | |
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172 | static inline int from_bcd(RTCState *s, int a) |
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173 | { |
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174 | if (s->cmos_data[RTC_REG_B] & 0x04) { |
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175 | return a; |
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176 | } else { |
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177 | return ((a >> 4) * 10) + (a & 0x0f); |
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178 | } |
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179 | } |
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180 | |
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181 | static void send_timeoffset_msg(time_t delta) |
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182 | { |
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183 | |
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184 | /* This routine is used to inform another entity that the |
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185 | base time offset has changed. For instance, if you |
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186 | were using xenstore, you might want to write to the store |
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187 | at this point. Or, you might use some other method. |
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188 | Whatever you might choose, here's a hook point to implement it. |
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189 | |
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190 | One item of note is that this delta is in addition to |
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191 | any existing offset you might be already using. */ |
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192 | |
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193 | return; |
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194 | } |
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195 | |
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196 | static void rtc_set_time(RTCState *s) |
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197 | { |
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198 | struct tm *tm = &s->current_tm; |
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199 | time_t before, after; |
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200 | |
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201 | before = mktime(tm); |
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202 | tm->tm_sec = from_bcd(s, s->cmos_data[RTC_SECONDS]); |
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203 | tm->tm_min = from_bcd(s, s->cmos_data[RTC_MINUTES]); |
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204 | tm->tm_hour = from_bcd(s, s->cmos_data[RTC_HOURS] & 0x7f); |
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205 | if (!(s->cmos_data[RTC_REG_B] & 0x02) && |
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206 | (s->cmos_data[RTC_HOURS] & 0x80)) { |
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207 | tm->tm_hour += 12; |
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208 | } |
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209 | tm->tm_wday = from_bcd(s, s->cmos_data[RTC_DAY_OF_WEEK]); |
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210 | tm->tm_mday = from_bcd(s, s->cmos_data[RTC_DAY_OF_MONTH]); |
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211 | tm->tm_mon = from_bcd(s, s->cmos_data[RTC_MONTH]) - 1; |
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212 | tm->tm_year = from_bcd(s, s->cmos_data[RTC_YEAR]) + 100; |
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213 | |
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214 | /* Compute, and send, the additional time delta |
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215 | We could compute the total time delta, but this is |
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216 | sufficient, and simple. */ |
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217 | after = mktime(tm); |
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218 | send_timeoffset_msg(after-before); |
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219 | } |
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220 | |
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221 | static void rtc_copy_date(RTCState *s) |
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222 | { |
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223 | const struct tm *tm = &s->current_tm; |
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224 | |
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225 | s->cmos_data[RTC_SECONDS] = to_bcd(s, tm->tm_sec); |
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226 | s->cmos_data[RTC_MINUTES] = to_bcd(s, tm->tm_min); |
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227 | if (s->cmos_data[RTC_REG_B] & 0x02) { |
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228 | /* 24 hour format */ |
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229 | s->cmos_data[RTC_HOURS] = to_bcd(s, tm->tm_hour); |
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230 | } else { |
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231 | /* 12 hour format */ |
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232 | s->cmos_data[RTC_HOURS] = to_bcd(s, tm->tm_hour % 12); |
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233 | if (tm->tm_hour >= 12) |
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234 | s->cmos_data[RTC_HOURS] |= 0x80; |
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235 | } |
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236 | s->cmos_data[RTC_DAY_OF_WEEK] = to_bcd(s, tm->tm_wday); |
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237 | s->cmos_data[RTC_DAY_OF_MONTH] = to_bcd(s, tm->tm_mday); |
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238 | s->cmos_data[RTC_MONTH] = to_bcd(s, tm->tm_mon + 1); |
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239 | s->cmos_data[RTC_YEAR] = to_bcd(s, tm->tm_year % 100); |
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240 | } |
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241 | |
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242 | /* month is between 0 and 11. */ |
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243 | static int get_days_in_month(int month, int year) |
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244 | { |
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245 | static const int days_tab[12] = { |
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246 | 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31 |
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247 | }; |
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248 | int d; |
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249 | if ((unsigned )month >= 12) |
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250 | return 31; |
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251 | d = days_tab[month]; |
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252 | if (month == 1) { |
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253 | if ((year % 4) == 0 && ((year % 100) != 0 || (year % 400) == 0)) |
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254 | d++; |
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255 | } |
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256 | return d; |
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257 | } |
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258 | |
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259 | /* update 'tm' to the next second */ |
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260 | static void rtc_next_second(struct tm *tm) |
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261 | { |
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262 | int days_in_month; |
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263 | |
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264 | tm->tm_sec++; |
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265 | if ((unsigned)tm->tm_sec >= 60) { |
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266 | tm->tm_sec = 0; |
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267 | tm->tm_min++; |
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268 | if ((unsigned)tm->tm_min >= 60) { |
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269 | tm->tm_min = 0; |
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270 | tm->tm_hour++; |
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271 | if ((unsigned)tm->tm_hour >= 24) { |
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272 | tm->tm_hour = 0; |
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273 | /* next day */ |
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274 | tm->tm_wday++; |
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275 | if ((unsigned)tm->tm_wday >= 7) |
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276 | tm->tm_wday = 0; |
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277 | days_in_month = get_days_in_month(tm->tm_mon, |
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278 | tm->tm_year + 1900); |
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279 | tm->tm_mday++; |
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280 | if (tm->tm_mday < 1) { |
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281 | tm->tm_mday = 1; |
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282 | } else if (tm->tm_mday > days_in_month) { |
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283 | tm->tm_mday = 1; |
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284 | tm->tm_mon++; |
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285 | if (tm->tm_mon >= 12) { |
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286 | tm->tm_mon = 0; |
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287 | tm->tm_year++; |
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288 | } |
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289 | } |
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290 | } |
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291 | } |
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292 | } |
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293 | } |
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294 | |
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295 | |
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296 | static void rtc_update_second(void *opaque) |
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297 | { |
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298 | RTCState *s = opaque; |
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299 | int64_t delay; |
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300 | |
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301 | /* if the oscillator is not in normal operation, we do not update */ |
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302 | if ((s->cmos_data[RTC_REG_A] & 0x70) != 0x20) { |
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303 | s->next_second_time += ticks_per_sec; |
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304 | qemu_mod_timer(s->second_timer, s->next_second_time); |
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305 | } else { |
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306 | rtc_next_second(&s->current_tm); |
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307 | |
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308 | if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) { |
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309 | /* update in progress bit */ |
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310 | s->cmos_data[RTC_REG_A] |= REG_A_UIP; |
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311 | } |
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312 | /* should be 244 us = 8 / 32768 seconds, but currently the |
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313 | timers do not have the necessary resolution. */ |
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314 | delay = (ticks_per_sec * 1) / 100; |
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315 | if (delay < 1) |
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316 | delay = 1; |
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317 | qemu_mod_timer(s->second_timer2, |
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318 | s->next_second_time + delay); |
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319 | } |
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320 | } |
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321 | |
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322 | static void rtc_update_second2(void *opaque) |
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323 | { |
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324 | RTCState *s = opaque; |
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325 | |
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326 | if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) { |
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327 | rtc_copy_date(s); |
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328 | } |
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329 | |
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330 | /* check alarm */ |
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331 | if (s->cmos_data[RTC_REG_B] & REG_B_AIE) { |
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332 | if (((s->cmos_data[RTC_SECONDS_ALARM] & 0xc0) == 0xc0 || |
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333 | s->cmos_data[RTC_SECONDS_ALARM] == s->current_tm.tm_sec) && |
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334 | ((s->cmos_data[RTC_MINUTES_ALARM] & 0xc0) == 0xc0 || |
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335 | s->cmos_data[RTC_MINUTES_ALARM] == s->current_tm.tm_mon) && |
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336 | ((s->cmos_data[RTC_HOURS_ALARM] & 0xc0) == 0xc0 || |
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337 | s->cmos_data[RTC_HOURS_ALARM] == s->current_tm.tm_hour)) { |
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338 | |
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339 | s->cmos_data[RTC_REG_C] |= 0xa0; |
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340 | pic_set_irq(s->irq, 1); |
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341 | } |
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342 | } |
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343 | |
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344 | /* update ended interrupt */ |
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345 | if (s->cmos_data[RTC_REG_B] & REG_B_UIE) { |
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346 | s->cmos_data[RTC_REG_C] |= 0x90; |
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347 | pic_set_irq(s->irq, 1); |
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348 | } |
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349 | |
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350 | /* clear update in progress bit */ |
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351 | s->cmos_data[RTC_REG_A] &= ~REG_A_UIP; |
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352 | |
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353 | s->next_second_time += ticks_per_sec; |
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354 | qemu_mod_timer(s->second_timer, s->next_second_time); |
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355 | } |
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356 | |
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357 | static uint32_t cmos_ioport_read(void *opaque, uint32_t addr) |
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358 | { |
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359 | RTCState *s = opaque; |
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360 | int ret; |
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361 | if ((addr & 1) == 0) { |
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362 | return 0xff; |
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363 | } else { |
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364 | switch(s->cmos_index) { |
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365 | case RTC_SECONDS: |
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366 | case RTC_MINUTES: |
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367 | case RTC_HOURS: |
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368 | case RTC_DAY_OF_WEEK: |
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369 | case RTC_DAY_OF_MONTH: |
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370 | case RTC_MONTH: |
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371 | case RTC_YEAR: |
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372 | ret = s->cmos_data[s->cmos_index]; |
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373 | break; |
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374 | case RTC_REG_A: |
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375 | ret = s->cmos_data[s->cmos_index]; |
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376 | break; |
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377 | case RTC_REG_C: |
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378 | ret = s->cmos_data[s->cmos_index]; |
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379 | pic_set_irq(s->irq, 0); |
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380 | s->cmos_data[RTC_REG_C] = 0x00; |
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381 | break; |
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382 | default: |
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383 | ret = s->cmos_data[s->cmos_index]; |
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384 | break; |
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385 | } |
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386 | #ifdef DEBUG_CMOS |
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387 | printf("cmos: read index=0x%02x val=0x%02x\n", |
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388 | s->cmos_index, ret); |
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389 | #endif |
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390 | return ret; |
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391 | } |
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392 | } |
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393 | |
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394 | void rtc_set_memory(RTCState *s, int addr, int val) |
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395 | { |
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396 | if (addr >= 0 && addr <= 127) |
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397 | s->cmos_data[addr] = val; |
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398 | } |
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399 | |
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400 | void rtc_set_date(RTCState *s, const struct tm *tm) |
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401 | { |
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402 | s->current_tm = *tm; |
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403 | rtc_copy_date(s); |
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404 | } |
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405 | |
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406 | static void rtc_save(QEMUFile *f, void *opaque) |
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407 | { |
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408 | RTCState *s = opaque; |
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409 | |
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410 | qemu_put_buffer(f, s->cmos_data, 128); |
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411 | qemu_put_8s(f, &s->cmos_index); |
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412 | |
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413 | qemu_put_be32s(f, &s->current_tm.tm_sec); |
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414 | qemu_put_be32s(f, &s->current_tm.tm_min); |
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415 | qemu_put_be32s(f, &s->current_tm.tm_hour); |
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416 | qemu_put_be32s(f, &s->current_tm.tm_wday); |
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417 | qemu_put_be32s(f, &s->current_tm.tm_mday); |
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418 | qemu_put_be32s(f, &s->current_tm.tm_mon); |
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419 | qemu_put_be32s(f, &s->current_tm.tm_year); |
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420 | |
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421 | qemu_put_timer(f, s->periodic_timer); |
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422 | qemu_put_be64s(f, &s->next_periodic_time); |
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423 | |
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424 | qemu_put_be64s(f, &s->next_second_time); |
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425 | qemu_put_timer(f, s->second_timer); |
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426 | qemu_put_timer(f, s->second_timer2); |
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427 | } |
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428 | |
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429 | static int rtc_load(QEMUFile *f, void *opaque, int version_id) |
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430 | { |
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431 | RTCState *s = opaque; |
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432 | |
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433 | if (version_id != 1) |
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434 | return -EINVAL; |
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435 | |
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436 | qemu_get_buffer(f, s->cmos_data, 128); |
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437 | qemu_get_8s(f, &s->cmos_index); |
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438 | |
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439 | qemu_get_be32s(f, &s->current_tm.tm_sec); |
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440 | qemu_get_be32s(f, &s->current_tm.tm_min); |
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441 | qemu_get_be32s(f, &s->current_tm.tm_hour); |
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442 | qemu_get_be32s(f, &s->current_tm.tm_wday); |
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443 | qemu_get_be32s(f, &s->current_tm.tm_mday); |
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444 | qemu_get_be32s(f, &s->current_tm.tm_mon); |
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445 | qemu_get_be32s(f, &s->current_tm.tm_year); |
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446 | |
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447 | qemu_get_timer(f, s->periodic_timer); |
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448 | qemu_get_be64s(f, &s->next_periodic_time); |
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449 | |
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450 | qemu_get_be64s(f, &s->next_second_time); |
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451 | qemu_get_timer(f, s->second_timer); |
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452 | qemu_get_timer(f, s->second_timer2); |
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453 | return 0; |
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454 | } |
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455 | |
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456 | RTCState *rtc_init(int base, int irq) |
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457 | { |
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458 | RTCState *s; |
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459 | |
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460 | s = qemu_mallocz(sizeof(RTCState)); |
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461 | if (!s) |
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462 | return NULL; |
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463 | |
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464 | s->irq = irq; |
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465 | s->cmos_data[RTC_REG_A] = 0x26; |
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466 | s->cmos_data[RTC_REG_B] = 0x02; |
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467 | s->cmos_data[RTC_REG_C] = 0x00; |
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468 | s->cmos_data[RTC_REG_D] = 0x80; |
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469 | |
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470 | s->periodic_timer = qemu_new_timer(vm_clock, |
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471 | rtc_periodic_timer, s); |
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472 | s->second_timer = qemu_new_timer(vm_clock, |
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473 | rtc_update_second, s); |
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474 | s->second_timer2 = qemu_new_timer(vm_clock, |
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475 | rtc_update_second2, s); |
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476 | |
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477 | s->next_second_time = qemu_get_clock(vm_clock) + (ticks_per_sec * 99) / 100; |
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478 | qemu_mod_timer(s->second_timer2, s->next_second_time); |
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479 | |
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480 | register_ioport_write(base, 2, 1, cmos_ioport_write, s); |
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481 | register_ioport_read(base, 2, 1, cmos_ioport_read, s); |
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482 | |
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483 | register_savevm("mc146818rtc", base, 1, rtc_save, rtc_load, s); |
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484 | return s; |
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485 | } |
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486 | |
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