1 | /* |
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2 | * QEMU 8253/8254 interval timer emulation |
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3 | * |
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4 | * Copyright (c) 2003-2004 Fabrice Bellard |
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5 | * |
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6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
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7 | * of this software and associated documentation files (the "Software"), to deal |
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8 | * in the Software without restriction, including without limitation the rights |
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9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
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10 | * copies of the Software, and to permit persons to whom the Software is |
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11 | * furnished to do so, subject to the following conditions: |
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12 | * |
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13 | * The above copyright notice and this permission notice shall be included in |
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14 | * all copies or substantial portions of the Software. |
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15 | * |
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16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
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21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
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22 | * THE SOFTWARE. |
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23 | */ |
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24 | #include "vl.h" |
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25 | |
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26 | //#define DEBUG_PIT |
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27 | |
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28 | #define RW_STATE_LSB 1 |
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29 | #define RW_STATE_MSB 2 |
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30 | #define RW_STATE_WORD0 3 |
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31 | #define RW_STATE_WORD1 4 |
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32 | |
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33 | typedef struct PITChannelState { |
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34 | int count; /* can be 65536 */ |
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35 | uint16_t latched_count; |
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36 | uint8_t count_latched; |
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37 | uint8_t status_latched; |
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38 | uint8_t status; |
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39 | uint8_t read_state; |
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40 | uint8_t write_state; |
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41 | uint8_t write_latch; |
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42 | uint8_t rw_mode; |
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43 | uint8_t mode; |
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44 | uint8_t bcd; /* not supported */ |
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45 | uint8_t gate; /* timer start */ |
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46 | int64_t count_load_time; |
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47 | /* irq handling */ |
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48 | int64_t next_transition_time; |
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49 | QEMUTimer *irq_timer; |
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50 | int irq; |
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51 | } PITChannelState; |
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52 | |
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53 | struct PITState { |
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54 | PITChannelState channels[3]; |
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55 | }; |
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56 | |
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57 | static PITState pit_state; |
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58 | |
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59 | static void pit_irq_timer_update(PITChannelState *s, int64_t current_time); |
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60 | |
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61 | static int pit_get_count(PITChannelState *s) |
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62 | { |
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63 | uint64_t d; |
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64 | int counter; |
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65 | |
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66 | d = muldiv64(qemu_get_clock(vm_clock) - s->count_load_time, PIT_FREQ, ticks_per_sec); |
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67 | switch(s->mode) { |
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68 | case 0: |
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69 | case 1: |
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70 | case 4: |
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71 | case 5: |
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72 | counter = (s->count - d) & 0xffff; |
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73 | break; |
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74 | case 3: |
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75 | /* XXX: may be incorrect for odd counts */ |
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76 | counter = s->count - ((2 * d) % s->count); |
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77 | break; |
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78 | default: |
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79 | counter = s->count - (d % s->count); |
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80 | break; |
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81 | } |
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82 | return counter; |
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83 | } |
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84 | |
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85 | /* get pit output bit */ |
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86 | static int pit_get_out1(PITChannelState *s, int64_t current_time) |
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87 | { |
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88 | uint64_t d; |
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89 | int out; |
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90 | |
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91 | d = muldiv64(current_time - s->count_load_time, PIT_FREQ, ticks_per_sec); |
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92 | switch(s->mode) { |
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93 | default: |
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94 | case 0: |
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95 | out = (d >= s->count); |
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96 | break; |
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97 | case 1: |
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98 | out = (d < s->count); |
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99 | break; |
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100 | case 2: |
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101 | if ((d % s->count) == 0 && d != 0) |
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102 | out = 1; |
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103 | else |
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104 | out = 0; |
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105 | break; |
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106 | case 3: |
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107 | out = (d % s->count) < ((s->count + 1) >> 1); |
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108 | break; |
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109 | case 4: |
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110 | case 5: |
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111 | out = (d == s->count); |
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112 | break; |
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113 | } |
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114 | return out; |
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115 | } |
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116 | |
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117 | int pit_get_out(PITState *pit, int channel, int64_t current_time) |
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118 | { |
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119 | PITChannelState *s = &pit->channels[channel]; |
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120 | return pit_get_out1(s, current_time); |
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121 | } |
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122 | |
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123 | /* return -1 if no transition will occur. */ |
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124 | static int64_t pit_get_next_transition_time(PITChannelState *s, |
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125 | int64_t current_time) |
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126 | { |
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127 | uint64_t d, next_time, base; |
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128 | int period2; |
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129 | |
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130 | d = muldiv64(current_time - s->count_load_time, PIT_FREQ, ticks_per_sec); |
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131 | switch(s->mode) { |
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132 | default: |
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133 | case 0: |
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134 | case 1: |
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135 | if (d < s->count) |
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136 | next_time = s->count; |
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137 | else |
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138 | return -1; |
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139 | break; |
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140 | case 2: |
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141 | base = (d / s->count) * s->count; |
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142 | if ((d - base) == 0 && d != 0) |
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143 | next_time = base + s->count; |
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144 | else |
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145 | next_time = base + s->count + 1; |
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146 | break; |
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147 | case 3: |
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148 | base = (d / s->count) * s->count; |
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149 | period2 = ((s->count + 1) >> 1); |
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150 | if ((d - base) < period2) |
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151 | next_time = base + period2; |
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152 | else |
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153 | next_time = base + s->count; |
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154 | break; |
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155 | case 4: |
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156 | case 5: |
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157 | if (d < s->count) |
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158 | next_time = s->count; |
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159 | else if (d == s->count) |
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160 | next_time = s->count + 1; |
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161 | else |
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162 | return -1; |
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163 | break; |
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164 | } |
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165 | /* convert to timer units */ |
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166 | next_time = s->count_load_time + muldiv64(next_time, ticks_per_sec, PIT_FREQ); |
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167 | /* fix potential rounding problems */ |
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168 | /* XXX: better solution: use a clock at PIT_FREQ Hz */ |
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169 | if (next_time <= current_time) |
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170 | next_time = current_time + 1; |
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171 | return next_time; |
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172 | } |
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173 | |
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174 | /* val must be 0 or 1 */ |
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175 | void pit_set_gate(PITState *pit, int channel, int val) |
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176 | { |
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177 | PITChannelState *s = &pit->channels[channel]; |
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178 | |
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179 | switch(s->mode) { |
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180 | default: |
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181 | case 0: |
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182 | case 4: |
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183 | /* XXX: just disable/enable counting */ |
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184 | break; |
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185 | case 1: |
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186 | case 5: |
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187 | if (s->gate < val) { |
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188 | /* restart counting on rising edge */ |
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189 | s->count_load_time = qemu_get_clock(vm_clock); |
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190 | pit_irq_timer_update(s, s->count_load_time); |
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191 | } |
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192 | break; |
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193 | case 2: |
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194 | case 3: |
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195 | if (s->gate < val) { |
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196 | /* restart counting on rising edge */ |
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197 | s->count_load_time = qemu_get_clock(vm_clock); |
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198 | pit_irq_timer_update(s, s->count_load_time); |
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199 | } |
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200 | /* XXX: disable/enable counting */ |
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201 | break; |
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202 | } |
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203 | s->gate = val; |
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204 | } |
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205 | |
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206 | int pit_get_gate(PITState *pit, int channel) |
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207 | { |
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208 | PITChannelState *s = &pit->channels[channel]; |
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209 | return s->gate; |
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210 | } |
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211 | |
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212 | int pit_get_initial_count(PITState *pit, int channel) |
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213 | { |
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214 | PITChannelState *s = &pit->channels[channel]; |
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215 | return s->count; |
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216 | } |
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217 | |
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218 | int pit_get_mode(PITState *pit, int channel) |
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219 | { |
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220 | PITChannelState *s = &pit->channels[channel]; |
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221 | return s->mode; |
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222 | } |
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223 | |
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224 | static inline void pit_load_count(PITChannelState *s, int val) |
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225 | { |
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226 | if (val == 0) |
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227 | val = 0x10000; |
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228 | s->count_load_time = qemu_get_clock(vm_clock); |
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229 | s->count = val; |
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230 | pit_irq_timer_update(s, s->count_load_time); |
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231 | } |
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232 | |
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233 | /* if already latched, do not latch again */ |
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234 | static void pit_latch_count(PITChannelState *s) |
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235 | { |
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236 | if (!s->count_latched) { |
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237 | s->latched_count = pit_get_count(s); |
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238 | s->count_latched = s->rw_mode; |
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239 | } |
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240 | } |
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241 | |
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242 | static void pit_ioport_write(void *opaque, uint32_t addr, uint32_t val) |
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243 | { |
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244 | PITState *pit = opaque; |
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245 | int channel, access; |
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246 | PITChannelState *s; |
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247 | |
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248 | addr &= 3; |
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249 | if (addr == 3) { |
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250 | channel = val >> 6; |
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251 | if (channel == 3) { |
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252 | /* read back command */ |
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253 | for(channel = 0; channel < 3; channel++) { |
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254 | s = &pit->channels[channel]; |
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255 | if (val & (2 << channel)) { |
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256 | if (!(val & 0x20)) { |
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257 | pit_latch_count(s); |
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258 | } |
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259 | if (!(val & 0x10) && !s->status_latched) { |
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260 | /* status latch */ |
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261 | /* XXX: add BCD and null count */ |
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262 | s->status = (pit_get_out1(s, qemu_get_clock(vm_clock)) << 7) | |
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263 | (s->rw_mode << 4) | |
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264 | (s->mode << 1) | |
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265 | s->bcd; |
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266 | s->status_latched = 1; |
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267 | } |
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268 | } |
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269 | } |
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270 | } else { |
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271 | s = &pit->channels[channel]; |
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272 | access = (val >> 4) & 3; |
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273 | if (access == 0) { |
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274 | pit_latch_count(s); |
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275 | } else { |
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276 | s->rw_mode = access; |
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277 | s->read_state = access; |
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278 | s->write_state = access; |
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279 | |
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280 | s->mode = (val >> 1) & 7; |
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281 | s->bcd = val & 1; |
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282 | /* XXX: update irq timer ? */ |
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283 | } |
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284 | } |
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285 | } else { |
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286 | s = &pit->channels[addr]; |
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287 | switch(s->write_state) { |
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288 | default: |
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289 | case RW_STATE_LSB: |
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290 | pit_load_count(s, val); |
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291 | break; |
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292 | case RW_STATE_MSB: |
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293 | pit_load_count(s, val << 8); |
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294 | break; |
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295 | case RW_STATE_WORD0: |
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296 | s->write_latch = val; |
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297 | s->write_state = RW_STATE_WORD1; |
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298 | break; |
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299 | case RW_STATE_WORD1: |
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300 | pit_load_count(s, s->write_latch | (val << 8)); |
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301 | s->write_state = RW_STATE_WORD0; |
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302 | break; |
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303 | } |
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304 | } |
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305 | } |
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306 | |
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307 | static uint32_t pit_ioport_read(void *opaque, uint32_t addr) |
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308 | { |
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309 | PITState *pit = opaque; |
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310 | int ret, count; |
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311 | PITChannelState *s; |
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312 | |
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313 | addr &= 3; |
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314 | s = &pit->channels[addr]; |
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315 | if (s->status_latched) { |
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316 | s->status_latched = 0; |
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317 | ret = s->status; |
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318 | } else if (s->count_latched) { |
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319 | switch(s->count_latched) { |
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320 | default: |
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321 | case RW_STATE_LSB: |
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322 | ret = s->latched_count & 0xff; |
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323 | s->count_latched = 0; |
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324 | break; |
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325 | case RW_STATE_MSB: |
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326 | ret = s->latched_count >> 8; |
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327 | s->count_latched = 0; |
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328 | break; |
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329 | case RW_STATE_WORD0: |
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330 | ret = s->latched_count & 0xff; |
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331 | s->count_latched = RW_STATE_MSB; |
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332 | break; |
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333 | } |
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334 | } else { |
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335 | switch(s->read_state) { |
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336 | default: |
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337 | case RW_STATE_LSB: |
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338 | count = pit_get_count(s); |
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339 | ret = count & 0xff; |
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340 | break; |
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341 | case RW_STATE_MSB: |
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342 | count = pit_get_count(s); |
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343 | ret = (count >> 8) & 0xff; |
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344 | break; |
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345 | case RW_STATE_WORD0: |
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346 | count = pit_get_count(s); |
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347 | ret = count & 0xff; |
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348 | s->read_state = RW_STATE_WORD1; |
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349 | break; |
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350 | case RW_STATE_WORD1: |
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351 | count = pit_get_count(s); |
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352 | ret = (count >> 8) & 0xff; |
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353 | s->read_state = RW_STATE_WORD0; |
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354 | break; |
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355 | } |
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356 | } |
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357 | return ret; |
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358 | } |
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359 | |
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360 | static void pit_irq_timer_update(PITChannelState *s, int64_t current_time) |
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361 | { |
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362 | int64_t expire_time; |
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363 | int irq_level; |
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364 | |
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365 | if (!s->irq_timer) |
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366 | return; |
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367 | expire_time = pit_get_next_transition_time(s, current_time); |
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368 | irq_level = pit_get_out1(s, current_time); |
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369 | pic_set_irq(s->irq, irq_level); |
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370 | #ifdef DEBUG_PIT |
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371 | printf("irq_level=%d next_delay=%f\n", |
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372 | irq_level, |
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373 | (double)(expire_time - current_time) / ticks_per_sec); |
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374 | #endif |
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375 | s->next_transition_time = expire_time; |
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376 | if (expire_time != -1) |
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377 | qemu_mod_timer(s->irq_timer, expire_time); |
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378 | else |
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379 | qemu_del_timer(s->irq_timer); |
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380 | } |
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381 | |
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382 | static void pit_irq_timer(void *opaque) |
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383 | { |
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384 | PITChannelState *s = opaque; |
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385 | |
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386 | pit_irq_timer_update(s, s->next_transition_time); |
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387 | } |
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388 | |
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389 | static void pit_save(QEMUFile *f, void *opaque) |
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390 | { |
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391 | PITState *pit = opaque; |
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392 | PITChannelState *s; |
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393 | int i; |
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394 | |
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395 | for(i = 0; i < 3; i++) { |
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396 | s = &pit->channels[i]; |
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397 | qemu_put_be32s(f, &s->count); |
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398 | qemu_put_be16s(f, &s->latched_count); |
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399 | qemu_put_8s(f, &s->count_latched); |
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400 | qemu_put_8s(f, &s->status_latched); |
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401 | qemu_put_8s(f, &s->status); |
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402 | qemu_put_8s(f, &s->read_state); |
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403 | qemu_put_8s(f, &s->write_state); |
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404 | qemu_put_8s(f, &s->write_latch); |
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405 | qemu_put_8s(f, &s->rw_mode); |
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406 | qemu_put_8s(f, &s->mode); |
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407 | qemu_put_8s(f, &s->bcd); |
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408 | qemu_put_8s(f, &s->gate); |
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409 | qemu_put_be64s(f, &s->count_load_time); |
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410 | if (s->irq_timer) { |
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411 | qemu_put_be64s(f, &s->next_transition_time); |
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412 | qemu_put_timer(f, s->irq_timer); |
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413 | } |
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414 | } |
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415 | } |
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416 | |
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417 | static int pit_load(QEMUFile *f, void *opaque, int version_id) |
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418 | { |
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419 | PITState *pit = opaque; |
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420 | PITChannelState *s; |
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421 | int i; |
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422 | |
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423 | if (version_id != 1) |
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424 | return -EINVAL; |
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425 | |
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426 | for(i = 0; i < 3; i++) { |
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427 | s = &pit->channels[i]; |
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428 | qemu_get_be32s(f, &s->count); |
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429 | qemu_get_be16s(f, &s->latched_count); |
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430 | qemu_get_8s(f, &s->count_latched); |
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431 | qemu_get_8s(f, &s->status_latched); |
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432 | qemu_get_8s(f, &s->status); |
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433 | qemu_get_8s(f, &s->read_state); |
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434 | qemu_get_8s(f, &s->write_state); |
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435 | qemu_get_8s(f, &s->write_latch); |
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436 | qemu_get_8s(f, &s->rw_mode); |
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437 | qemu_get_8s(f, &s->mode); |
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438 | qemu_get_8s(f, &s->bcd); |
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439 | qemu_get_8s(f, &s->gate); |
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440 | qemu_get_be64s(f, &s->count_load_time); |
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441 | if (s->irq_timer) { |
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442 | qemu_get_be64s(f, &s->next_transition_time); |
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443 | qemu_get_timer(f, s->irq_timer); |
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444 | } |
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445 | } |
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446 | return 0; |
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447 | } |
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448 | |
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449 | static void pit_reset(void *opaque) |
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450 | { |
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451 | PITState *pit = opaque; |
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452 | PITChannelState *s; |
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453 | int i; |
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454 | |
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455 | for(i = 0;i < 3; i++) { |
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456 | s = &pit->channels[i]; |
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457 | s->mode = 3; |
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458 | s->gate = (i != 2); |
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459 | pit_load_count(s, 0); |
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460 | } |
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461 | } |
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462 | |
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463 | PITState *pit_init(int base, int irq) |
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464 | { |
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465 | PITState *pit = &pit_state; |
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466 | PITChannelState *s; |
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467 | |
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468 | s = &pit->channels[0]; |
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469 | /* the timer 0 is connected to an IRQ */ |
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470 | s->irq_timer = qemu_new_timer(vm_clock, pit_irq_timer, s); |
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471 | s->irq = irq; |
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472 | |
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473 | register_savevm("i8254", base, 1, pit_save, pit_load, pit); |
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474 | |
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475 | qemu_register_reset(pit_reset, pit); |
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476 | register_ioport_write(base, 4, 1, pit_ioport_write, pit); |
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477 | register_ioport_read(base, 3, 1, pit_ioport_read, pit); |
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478 | |
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479 | pit_reset(pit); |
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480 | |
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481 | return pit; |
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482 | } |
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