1 | /* |
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2 | * QEMU DMA emulation |
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3 | * |
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4 | * Copyright (c) 2003-2004 Vassili Karpov (malc) |
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5 | * |
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6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
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7 | * of this software and associated documentation files (the "Software"), to deal |
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8 | * in the Software without restriction, including without limitation the rights |
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9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
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10 | * copies of the Software, and to permit persons to whom the Software is |
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11 | * furnished to do so, subject to the following conditions: |
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12 | * |
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13 | * The above copyright notice and this permission notice shall be included in |
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14 | * all copies or substantial portions of the Software. |
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15 | * |
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16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
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21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
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22 | * THE SOFTWARE. |
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23 | */ |
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24 | #include "vl.h" |
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25 | |
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26 | /* #define DEBUG_DMA */ |
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27 | |
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28 | #define dolog(...) fprintf (stderr, "dma: " __VA_ARGS__) |
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29 | #ifdef DEBUG_DMA |
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30 | #define lwarn(...) fprintf (stderr, "dma: " __VA_ARGS__) |
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31 | #define linfo(...) fprintf (stderr, "dma: " __VA_ARGS__) |
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32 | #define ldebug(...) fprintf (stderr, "dma: " __VA_ARGS__) |
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33 | #else |
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34 | #define lwarn(...) |
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35 | #define linfo(...) |
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36 | #define ldebug(...) |
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37 | #endif |
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38 | |
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39 | #define LENOFA(a) ((int) (sizeof(a)/sizeof(a[0]))) |
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40 | |
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41 | struct dma_regs { |
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42 | int now[2]; |
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43 | uint16_t base[2]; |
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44 | uint8_t mode; |
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45 | uint8_t page; |
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46 | uint8_t pageh; |
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47 | uint8_t dack; |
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48 | uint8_t eop; |
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49 | DMA_transfer_handler transfer_handler; |
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50 | void *opaque; |
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51 | }; |
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52 | |
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53 | #define ADDR 0 |
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54 | #define COUNT 1 |
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55 | |
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56 | static struct dma_cont { |
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57 | uint8_t status; |
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58 | uint8_t command; |
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59 | uint8_t mask; |
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60 | uint8_t flip_flop; |
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61 | int dshift; |
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62 | struct dma_regs regs[4]; |
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63 | } dma_controllers[2]; |
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64 | |
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65 | enum { |
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66 | CMD_MEMORY_TO_MEMORY = 0x01, |
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67 | CMD_FIXED_ADDRESS = 0x02, |
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68 | CMD_BLOCK_CONTROLLER = 0x04, |
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69 | CMD_COMPRESSED_TIME = 0x08, |
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70 | CMD_CYCLIC_PRIORITY = 0x10, |
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71 | CMD_EXTENDED_WRITE = 0x20, |
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72 | CMD_LOW_DREQ = 0x40, |
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73 | CMD_LOW_DACK = 0x80, |
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74 | CMD_NOT_SUPPORTED = CMD_MEMORY_TO_MEMORY | CMD_FIXED_ADDRESS |
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75 | | CMD_COMPRESSED_TIME | CMD_CYCLIC_PRIORITY | CMD_EXTENDED_WRITE |
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76 | | CMD_LOW_DREQ | CMD_LOW_DACK |
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77 | |
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78 | }; |
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79 | |
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80 | static int channels[8] = {-1, 2, 3, 1, -1, -1, -1, 0}; |
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81 | |
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82 | static void write_page (void *opaque, uint32_t nport, uint32_t data) |
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83 | { |
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84 | struct dma_cont *d = opaque; |
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85 | int ichan; |
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86 | |
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87 | ichan = channels[nport & 7]; |
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88 | if (-1 == ichan) { |
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89 | dolog ("invalid channel %#x %#x\n", nport, data); |
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90 | return; |
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91 | } |
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92 | d->regs[ichan].page = data; |
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93 | } |
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94 | |
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95 | static void write_pageh (void *opaque, uint32_t nport, uint32_t data) |
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96 | { |
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97 | struct dma_cont *d = opaque; |
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98 | int ichan; |
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99 | |
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100 | ichan = channels[nport & 7]; |
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101 | if (-1 == ichan) { |
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102 | dolog ("invalid channel %#x %#x\n", nport, data); |
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103 | return; |
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104 | } |
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105 | d->regs[ichan].pageh = data; |
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106 | } |
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107 | |
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108 | static uint32_t read_page (void *opaque, uint32_t nport) |
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109 | { |
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110 | struct dma_cont *d = opaque; |
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111 | int ichan; |
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112 | |
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113 | ichan = channels[nport & 7]; |
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114 | if (-1 == ichan) { |
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115 | dolog ("invalid channel read %#x\n", nport); |
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116 | return 0; |
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117 | } |
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118 | return d->regs[ichan].page; |
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119 | } |
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120 | |
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121 | static uint32_t read_pageh (void *opaque, uint32_t nport) |
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122 | { |
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123 | struct dma_cont *d = opaque; |
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124 | int ichan; |
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125 | |
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126 | ichan = channels[nport & 7]; |
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127 | if (-1 == ichan) { |
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128 | dolog ("invalid channel read %#x\n", nport); |
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129 | return 0; |
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130 | } |
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131 | return d->regs[ichan].pageh; |
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132 | } |
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133 | |
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134 | static inline void init_chan (struct dma_cont *d, int ichan) |
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135 | { |
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136 | struct dma_regs *r; |
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137 | |
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138 | r = d->regs + ichan; |
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139 | r->now[ADDR] = r->base[ADDR] << d->dshift; |
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140 | r->now[COUNT] = 0; |
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141 | } |
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142 | |
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143 | static inline int getff (struct dma_cont *d) |
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144 | { |
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145 | int ff; |
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146 | |
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147 | ff = d->flip_flop; |
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148 | d->flip_flop = !ff; |
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149 | return ff; |
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150 | } |
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151 | |
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152 | static uint32_t read_chan (void *opaque, uint32_t nport) |
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153 | { |
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154 | struct dma_cont *d = opaque; |
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155 | int ichan, nreg, iport, ff, val, dir; |
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156 | struct dma_regs *r; |
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157 | |
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158 | iport = (nport >> d->dshift) & 0x0f; |
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159 | ichan = iport >> 1; |
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160 | nreg = iport & 1; |
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161 | r = d->regs + ichan; |
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162 | |
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163 | dir = ((r->mode >> 5) & 1) ? -1 : 1; |
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164 | ff = getff (d); |
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165 | if (nreg) |
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166 | val = (r->base[COUNT] << d->dshift) - r->now[COUNT]; |
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167 | else |
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168 | val = r->now[ADDR] + r->now[COUNT] * dir; |
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169 | |
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170 | ldebug ("read_chan %#x -> %d\n", iport, val); |
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171 | return (val >> (d->dshift + (ff << 3))) & 0xff; |
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172 | } |
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173 | |
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174 | static void write_chan (void *opaque, uint32_t nport, uint32_t data) |
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175 | { |
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176 | struct dma_cont *d = opaque; |
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177 | int iport, ichan, nreg; |
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178 | struct dma_regs *r; |
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179 | |
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180 | iport = (nport >> d->dshift) & 0x0f; |
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181 | ichan = iport >> 1; |
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182 | nreg = iport & 1; |
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183 | r = d->regs + ichan; |
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184 | if (getff (d)) { |
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185 | r->base[nreg] = (r->base[nreg] & 0xff) | ((data << 8) & 0xff00); |
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186 | init_chan (d, ichan); |
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187 | } else { |
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188 | r->base[nreg] = (r->base[nreg] & 0xff00) | (data & 0xff); |
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189 | } |
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190 | } |
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191 | |
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192 | static void write_cont (void *opaque, uint32_t nport, uint32_t data) |
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193 | { |
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194 | struct dma_cont *d = opaque; |
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195 | int iport, ichan = 0; |
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196 | |
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197 | iport = (nport >> d->dshift) & 0x0f; |
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198 | switch (iport) { |
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199 | case 0x08: /* command */ |
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200 | if ((data != 0) && (data & CMD_NOT_SUPPORTED)) { |
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201 | dolog ("command %#x not supported\n", data); |
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202 | return; |
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203 | } |
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204 | d->command = data; |
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205 | break; |
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206 | |
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207 | case 0x09: |
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208 | ichan = data & 3; |
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209 | if (data & 4) { |
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210 | d->status |= 1 << (ichan + 4); |
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211 | } |
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212 | else { |
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213 | d->status &= ~(1 << (ichan + 4)); |
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214 | } |
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215 | d->status &= ~(1 << ichan); |
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216 | break; |
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217 | |
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218 | case 0x0a: /* single mask */ |
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219 | if (data & 4) |
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220 | d->mask |= 1 << (data & 3); |
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221 | else |
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222 | d->mask &= ~(1 << (data & 3)); |
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223 | break; |
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224 | |
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225 | case 0x0b: /* mode */ |
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226 | { |
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227 | ichan = data & 3; |
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228 | #ifdef DEBUG_DMA |
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229 | { |
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230 | int op, ai, dir, opmode; |
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231 | op = (data >> 2) & 3; |
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232 | ai = (data >> 4) & 1; |
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233 | dir = (data >> 5) & 1; |
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234 | opmode = (data >> 6) & 3; |
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235 | |
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236 | linfo ("ichan %d, op %d, ai %d, dir %d, opmode %d\n", |
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237 | ichan, op, ai, dir, opmode); |
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238 | } |
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239 | #endif |
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240 | d->regs[ichan].mode = data; |
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241 | break; |
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242 | } |
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243 | |
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244 | case 0x0c: /* clear flip flop */ |
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245 | d->flip_flop = 0; |
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246 | break; |
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247 | |
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248 | case 0x0d: /* reset */ |
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249 | d->flip_flop = 0; |
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250 | d->mask = ~0; |
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251 | d->status = 0; |
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252 | d->command = 0; |
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253 | break; |
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254 | |
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255 | case 0x0e: /* clear mask for all channels */ |
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256 | d->mask = 0; |
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257 | break; |
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258 | |
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259 | case 0x0f: /* write mask for all channels */ |
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260 | d->mask = data; |
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261 | break; |
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262 | |
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263 | default: |
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264 | dolog ("unknown iport %#x\n", iport); |
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265 | break; |
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266 | } |
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267 | |
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268 | #ifdef DEBUG_DMA |
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269 | if (0xc != iport) { |
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270 | linfo ("write_cont: nport %#06x, ichan % 2d, val %#06x\n", |
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271 | nport, ichan, data); |
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272 | } |
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273 | #endif |
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274 | } |
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275 | |
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276 | static uint32_t read_cont (void *opaque, uint32_t nport) |
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277 | { |
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278 | struct dma_cont *d = opaque; |
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279 | int iport, val; |
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280 | |
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281 | iport = (nport >> d->dshift) & 0x0f; |
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282 | switch (iport) { |
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283 | case 0x08: /* status */ |
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284 | val = d->status; |
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285 | d->status &= 0xf0; |
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286 | break; |
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287 | case 0x0f: /* mask */ |
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288 | val = d->mask; |
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289 | break; |
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290 | default: |
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291 | val = 0; |
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292 | break; |
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293 | } |
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294 | |
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295 | ldebug ("read_cont: nport %#06x, iport %#04x val %#x\n", nport, iport, val); |
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296 | return val; |
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297 | } |
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298 | |
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299 | int DMA_get_channel_mode (int nchan) |
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300 | { |
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301 | return dma_controllers[nchan > 3].regs[nchan & 3].mode; |
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302 | } |
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303 | |
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304 | void DMA_hold_DREQ (int nchan) |
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305 | { |
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306 | int ncont, ichan; |
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307 | |
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308 | ncont = nchan > 3; |
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309 | ichan = nchan & 3; |
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310 | linfo ("held cont=%d chan=%d\n", ncont, ichan); |
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311 | dma_controllers[ncont].status |= 1 << (ichan + 4); |
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312 | } |
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313 | |
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314 | void DMA_release_DREQ (int nchan) |
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315 | { |
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316 | int ncont, ichan; |
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317 | |
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318 | ncont = nchan > 3; |
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319 | ichan = nchan & 3; |
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320 | linfo ("released cont=%d chan=%d\n", ncont, ichan); |
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321 | dma_controllers[ncont].status &= ~(1 << (ichan + 4)); |
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322 | } |
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323 | |
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324 | static void channel_run (int ncont, int ichan) |
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325 | { |
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326 | int n; |
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327 | struct dma_regs *r = &dma_controllers[ncont].regs[ichan]; |
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328 | #ifdef DEBUG_DMA |
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329 | int dir, opmode; |
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330 | |
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331 | dir = (r->mode >> 5) & 1; |
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332 | opmode = (r->mode >> 6) & 3; |
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333 | |
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334 | if (dir) { |
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335 | dolog ("DMA in address decrement mode\n"); |
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336 | } |
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337 | if (opmode != 1) { |
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338 | dolog ("DMA not in single mode select %#x\n", opmode); |
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339 | } |
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340 | #endif |
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341 | |
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342 | r = dma_controllers[ncont].regs + ichan; |
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343 | if (r->transfer_handler == NULL) |
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344 | return; |
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345 | n = r->transfer_handler (r->opaque, ichan + (ncont << 2), |
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346 | r->now[COUNT], (r->base[COUNT] + 1) << ncont); |
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347 | r->now[COUNT] = n; |
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348 | ldebug ("dma_pos %d size %d\n", n, (r->base[COUNT] + 1) << ncont); |
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349 | } |
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350 | |
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351 | void DMA_run (void) |
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352 | { |
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353 | struct dma_cont *d; |
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354 | int icont, ichan; |
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355 | |
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356 | d = dma_controllers; |
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357 | |
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358 | for (icont = 0; icont < 2; icont++, d++) { |
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359 | for (ichan = 0; ichan < 4; ichan++) { |
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360 | int mask; |
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361 | |
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362 | mask = 1 << ichan; |
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363 | |
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364 | if ((0 == (d->mask & mask)) && (0 != (d->status & (mask << 4)))) |
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365 | channel_run (icont, ichan); |
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366 | } |
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367 | } |
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368 | } |
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369 | |
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370 | void DMA_register_channel (int nchan, |
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371 | DMA_transfer_handler transfer_handler, |
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372 | void *opaque) |
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373 | { |
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374 | struct dma_regs *r; |
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375 | int ichan, ncont; |
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376 | |
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377 | ncont = nchan > 3; |
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378 | ichan = nchan & 3; |
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379 | |
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380 | r = dma_controllers[ncont].regs + ichan; |
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381 | r->transfer_handler = transfer_handler; |
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382 | r->opaque = opaque; |
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383 | } |
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384 | |
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385 | int DMA_read_memory (int nchan, void *buf, int pos, int len) |
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386 | { |
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387 | struct dma_regs *r = &dma_controllers[nchan > 3].regs[nchan & 3]; |
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388 | target_ulong addr = ((r->pageh & 0x7f) << 24) | (r->page << 16) | r->now[ADDR]; |
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389 | |
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390 | if (r->mode & 0x20) { |
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391 | int i; |
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392 | uint8_t *p = buf; |
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393 | |
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394 | cpu_physical_memory_read (addr - pos - len, buf, len); |
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395 | /* What about 16bit transfers? */ |
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396 | for (i = 0; i < len >> 1; i++) { |
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397 | uint8_t b = p[len - i - 1]; |
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398 | p[i] = b; |
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399 | } |
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400 | } |
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401 | else |
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402 | cpu_physical_memory_read (addr + pos, buf, len); |
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403 | |
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404 | return len; |
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405 | } |
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406 | |
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407 | int DMA_write_memory (int nchan, void *buf, int pos, int len) |
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408 | { |
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409 | struct dma_regs *r = &dma_controllers[nchan > 3].regs[nchan & 3]; |
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410 | target_ulong addr = ((r->pageh & 0x7f) << 24) | (r->page << 16) | r->now[ADDR]; |
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411 | |
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412 | if (r->mode & 0x20) { |
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413 | int i; |
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414 | uint8_t *p = buf; |
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415 | |
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416 | cpu_physical_memory_write (addr - pos - len, buf, len); |
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417 | /* What about 16bit transfers? */ |
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418 | for (i = 0; i < len; i++) { |
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419 | uint8_t b = p[len - i - 1]; |
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420 | p[i] = b; |
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421 | } |
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422 | } |
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423 | else |
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424 | cpu_physical_memory_write (addr + pos, buf, len); |
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425 | |
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426 | return len; |
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427 | } |
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428 | |
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429 | /* request the emulator to transfer a new DMA memory block ASAP */ |
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430 | void DMA_schedule(int nchan) |
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431 | { |
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432 | CPUState *env = cpu_single_env; |
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433 | if (env) |
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434 | cpu_interrupt(env, CPU_INTERRUPT_EXIT); |
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435 | } |
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436 | |
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437 | static void dma_reset(void *opaque) |
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438 | { |
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439 | struct dma_cont *d = opaque; |
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440 | write_cont (d, (0x0d << d->dshift), 0); |
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441 | } |
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442 | |
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443 | /* dshift = 0: 8 bit DMA, 1 = 16 bit DMA */ |
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444 | static void dma_init2(struct dma_cont *d, int base, int dshift, |
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445 | int page_base, int pageh_base) |
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446 | { |
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447 | const static int page_port_list[] = { 0x1, 0x2, 0x3, 0x7 }; |
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448 | int i; |
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449 | |
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450 | d->dshift = dshift; |
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451 | for (i = 0; i < 8; i++) { |
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452 | register_ioport_write (base + (i << dshift), 1, 1, write_chan, d); |
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453 | register_ioport_read (base + (i << dshift), 1, 1, read_chan, d); |
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454 | } |
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455 | for (i = 0; i < LENOFA (page_port_list); i++) { |
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456 | register_ioport_write (page_base + page_port_list[i], 1, 1, |
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457 | write_page, d); |
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458 | register_ioport_read (page_base + page_port_list[i], 1, 1, |
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459 | read_page, d); |
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460 | if (pageh_base >= 0) { |
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461 | register_ioport_write (pageh_base + page_port_list[i], 1, 1, |
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462 | write_pageh, d); |
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463 | register_ioport_read (pageh_base + page_port_list[i], 1, 1, |
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464 | read_pageh, d); |
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465 | } |
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466 | } |
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467 | for (i = 0; i < 8; i++) { |
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468 | register_ioport_write (base + ((i + 8) << dshift), 1, 1, |
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469 | write_cont, d); |
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470 | register_ioport_read (base + ((i + 8) << dshift), 1, 1, |
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471 | read_cont, d); |
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472 | } |
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473 | qemu_register_reset(dma_reset, d); |
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474 | dma_reset(d); |
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475 | } |
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476 | |
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477 | static void dma_save (QEMUFile *f, void *opaque) |
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478 | { |
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479 | struct dma_cont *d = opaque; |
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480 | int i; |
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481 | |
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482 | /* qemu_put_8s (f, &d->status); */ |
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483 | qemu_put_8s (f, &d->command); |
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484 | qemu_put_8s (f, &d->mask); |
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485 | qemu_put_8s (f, &d->flip_flop); |
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486 | qemu_put_be32s (f, &d->dshift); |
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487 | |
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488 | for (i = 0; i < 4; ++i) { |
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489 | struct dma_regs *r = &d->regs[i]; |
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490 | qemu_put_be32s (f, &r->now[0]); |
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491 | qemu_put_be32s (f, &r->now[1]); |
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492 | qemu_put_be16s (f, &r->base[0]); |
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493 | qemu_put_be16s (f, &r->base[1]); |
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494 | qemu_put_8s (f, &r->mode); |
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495 | qemu_put_8s (f, &r->page); |
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496 | qemu_put_8s (f, &r->pageh); |
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497 | qemu_put_8s (f, &r->dack); |
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498 | qemu_put_8s (f, &r->eop); |
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499 | } |
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500 | } |
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501 | |
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502 | static int dma_load (QEMUFile *f, void *opaque, int version_id) |
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503 | { |
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504 | struct dma_cont *d = opaque; |
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505 | int i; |
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506 | |
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507 | if (version_id != 1) |
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508 | return -EINVAL; |
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509 | |
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510 | /* qemu_get_8s (f, &d->status); */ |
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511 | qemu_get_8s (f, &d->command); |
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512 | qemu_get_8s (f, &d->mask); |
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513 | qemu_get_8s (f, &d->flip_flop); |
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514 | qemu_get_be32s (f, &d->dshift); |
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515 | |
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516 | for (i = 0; i < 4; ++i) { |
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517 | struct dma_regs *r = &d->regs[i]; |
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518 | qemu_get_be32s (f, &r->now[0]); |
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519 | qemu_get_be32s (f, &r->now[1]); |
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520 | qemu_get_be16s (f, &r->base[0]); |
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521 | qemu_get_be16s (f, &r->base[1]); |
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522 | qemu_get_8s (f, &r->mode); |
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523 | qemu_get_8s (f, &r->page); |
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524 | qemu_get_8s (f, &r->pageh); |
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525 | qemu_get_8s (f, &r->dack); |
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526 | qemu_get_8s (f, &r->eop); |
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527 | } |
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528 | return 0; |
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529 | } |
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530 | |
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531 | void DMA_init (int high_page_enable) |
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532 | { |
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533 | dma_init2(&dma_controllers[0], 0x00, 0, 0x80, |
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534 | high_page_enable ? 0x480 : -1); |
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535 | dma_init2(&dma_controllers[1], 0xc0, 1, 0x88, |
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536 | high_page_enable ? 0x488 : -1); |
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537 | register_savevm ("dma", 0, 1, dma_save, dma_load, &dma_controllers[0]); |
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538 | register_savevm ("dma", 1, 1, dma_save, dma_load, &dma_controllers[1]); |
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539 | } |
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