1 | /* |
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2 | * ACPI implementation |
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3 | * |
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4 | * Copyright (c) 2006 Fabrice Bellard |
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5 | * |
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6 | * This library is free software; you can redistribute it and/or |
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7 | * modify it under the terms of the GNU Lesser General Public |
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8 | * License version 2 as published by the Free Software Foundation. |
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9 | * |
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10 | * This library is distributed in the hope that it will be useful, |
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11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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13 | * Lesser General Public License for more details. |
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14 | * |
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15 | * You should have received a copy of the GNU Lesser General Public |
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16 | * License along with this library; if not, write to the Free Software |
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17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
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18 | */ |
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19 | #include "vl.h" |
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20 | |
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21 | //#define DEBUG |
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22 | |
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23 | /* i82731AB (PIIX4) compatible power management function */ |
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24 | #define PM_FREQ 3579545 |
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25 | |
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26 | /* XXX: make them variable */ |
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27 | #define PM_IO_BASE 0xb000 |
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28 | #define SMI_CMD_IO_ADDR 0xb040 |
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29 | #define ACPI_DBG_IO_ADDR 0xb044 |
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30 | |
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31 | typedef struct PIIX4PMState { |
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32 | PCIDevice dev; |
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33 | uint16_t pmsts; |
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34 | uint16_t pmen; |
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35 | uint16_t pmcntrl; |
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36 | QEMUTimer *tmr_timer; |
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37 | int64_t tmr_overflow_time; |
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38 | } PIIX4PMState; |
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39 | |
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40 | #define RTC_EN (1 << 10) |
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41 | #define PWRBTN_EN (1 << 8) |
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42 | #define GBL_EN (1 << 5) |
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43 | #define TMROF_EN (1 << 0) |
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44 | |
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45 | #define SCI_EN (1 << 0) |
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46 | |
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47 | #define SUS_EN (1 << 13) |
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48 | |
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49 | /* Note: only used for ACPI bios init. Could be deleted when ACPI init |
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50 | is integrated in Bochs BIOS */ |
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51 | static PIIX4PMState *piix4_pm_state; |
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52 | |
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53 | static uint32_t get_pmtmr(PIIX4PMState *s) |
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54 | { |
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55 | uint32_t d; |
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56 | d = muldiv64(qemu_get_clock(vm_clock), PM_FREQ, ticks_per_sec); |
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57 | return d & 0xffffff; |
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58 | } |
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59 | |
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60 | static int get_pmsts(PIIX4PMState *s) |
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61 | { |
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62 | int64_t d; |
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63 | int pmsts; |
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64 | pmsts = s->pmsts; |
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65 | d = muldiv64(qemu_get_clock(vm_clock), PM_FREQ, ticks_per_sec); |
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66 | if (d >= s->tmr_overflow_time) |
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67 | s->pmsts |= TMROF_EN; |
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68 | return pmsts; |
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69 | } |
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70 | |
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71 | static void pm_update_sci(PIIX4PMState *s) |
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72 | { |
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73 | int sci_level, pmsts; |
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74 | int64_t expire_time; |
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75 | |
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76 | pmsts = get_pmsts(s); |
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77 | sci_level = (((pmsts & s->pmen) & |
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78 | (RTC_EN | PWRBTN_EN | GBL_EN | TMROF_EN)) != 0); |
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79 | pci_set_irq(&s->dev, 0, sci_level); |
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80 | /* schedule a timer interruption if needed */ |
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81 | if ((s->pmen & TMROF_EN) && !(pmsts & TMROF_EN)) { |
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82 | expire_time = muldiv64(s->tmr_overflow_time, ticks_per_sec, PM_FREQ); |
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83 | qemu_mod_timer(s->tmr_timer, expire_time); |
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84 | } else { |
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85 | qemu_del_timer(s->tmr_timer); |
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86 | } |
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87 | } |
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88 | |
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89 | static void pm_tmr_timer(void *opaque) |
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90 | { |
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91 | PIIX4PMState *s = opaque; |
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92 | pm_update_sci(s); |
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93 | } |
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94 | |
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95 | static void pm_ioport_writew(void *opaque, uint32_t addr, uint32_t val) |
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96 | { |
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97 | PIIX4PMState *s = opaque; |
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98 | addr &= 0x3f; |
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99 | switch(addr) { |
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100 | case 0x00: |
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101 | { |
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102 | int64_t d; |
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103 | int pmsts; |
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104 | pmsts = get_pmsts(s); |
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105 | if (pmsts & val & TMROF_EN) { |
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106 | /* if TMRSTS is reset, then compute the new overflow time */ |
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107 | d = muldiv64(qemu_get_clock(vm_clock), PM_FREQ, ticks_per_sec); |
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108 | s->tmr_overflow_time = (d + 0x800000LL) & ~0x7fffffLL; |
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109 | } |
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110 | s->pmsts &= ~val; |
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111 | pm_update_sci(s); |
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112 | } |
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113 | break; |
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114 | case 0x02: |
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115 | s->pmen = val; |
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116 | pm_update_sci(s); |
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117 | break; |
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118 | case 0x04: |
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119 | { |
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120 | int sus_typ; |
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121 | s->pmcntrl = val & ~(SUS_EN); |
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122 | if (val & SUS_EN) { |
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123 | /* change suspend type */ |
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124 | sus_typ = (val >> 10) & 3; |
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125 | switch(sus_typ) { |
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126 | case 0: /* soft power off */ |
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127 | qemu_system_shutdown_request(); |
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128 | break; |
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129 | default: |
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130 | break; |
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131 | } |
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132 | } |
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133 | } |
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134 | break; |
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135 | default: |
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136 | break; |
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137 | } |
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138 | #ifdef DEBUG |
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139 | printf("PM writew port=0x%04x val=0x%04x\n", addr, val); |
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140 | #endif |
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141 | } |
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142 | |
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143 | static uint32_t pm_ioport_readw(void *opaque, uint32_t addr) |
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144 | { |
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145 | PIIX4PMState *s = opaque; |
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146 | uint32_t val; |
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147 | |
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148 | addr &= 0x3f; |
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149 | switch(addr) { |
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150 | case 0x00: |
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151 | val = get_pmsts(s); |
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152 | break; |
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153 | case 0x02: |
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154 | val = s->pmen; |
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155 | break; |
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156 | case 0x04: |
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157 | val = s->pmcntrl; |
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158 | break; |
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159 | default: |
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160 | val = 0; |
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161 | break; |
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162 | } |
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163 | #ifdef DEBUG |
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164 | printf("PM readw port=0x%04x val=0x%04x\n", addr, val); |
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165 | #endif |
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166 | return val; |
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167 | } |
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168 | |
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169 | static void pm_ioport_writel(void *opaque, uint32_t addr, uint32_t val) |
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170 | { |
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171 | // PIIX4PMState *s = opaque; |
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172 | addr &= 0x3f; |
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173 | #ifdef DEBUG |
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174 | printf("PM writel port=0x%04x val=0x%08x\n", addr, val); |
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175 | #endif |
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176 | } |
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177 | |
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178 | static uint32_t pm_ioport_readl(void *opaque, uint32_t addr) |
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179 | { |
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180 | PIIX4PMState *s = opaque; |
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181 | uint32_t val; |
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182 | |
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183 | addr &= 0x3f; |
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184 | switch(addr) { |
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185 | case 0x08: |
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186 | val = get_pmtmr(s); |
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187 | break; |
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188 | default: |
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189 | val = 0; |
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190 | break; |
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191 | } |
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192 | #ifdef DEBUG |
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193 | printf("PM readl port=0x%04x val=0x%08x\n", addr, val); |
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194 | #endif |
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195 | return val; |
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196 | } |
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197 | |
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198 | static void smi_cmd_writeb(void *opaque, uint32_t addr, uint32_t val) |
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199 | { |
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200 | PIIX4PMState *s = opaque; |
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201 | #ifdef DEBUG |
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202 | printf("SMI cmd val=0x%02x\n", val); |
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203 | #endif |
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204 | switch(val) { |
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205 | case 0xf0: /* ACPI disable */ |
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206 | s->pmcntrl &= ~SCI_EN; |
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207 | break; |
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208 | case 0xf1: /* ACPI enable */ |
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209 | s->pmcntrl |= SCI_EN; |
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210 | break; |
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211 | } |
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212 | } |
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213 | |
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214 | static void acpi_dbg_writel(void *opaque, uint32_t addr, uint32_t val) |
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215 | { |
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216 | #if defined(DEBUG) |
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217 | printf("ACPI: DBG: 0x%08x\n", val); |
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218 | #endif |
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219 | } |
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220 | |
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221 | /* XXX: we still add it to the PIIX3 and we count on the fact that |
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222 | OSes are smart enough to accept this strange configuration */ |
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223 | void piix4_pm_init(PCIBus *bus, int devfn) |
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224 | { |
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225 | PIIX4PMState *s; |
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226 | uint8_t *pci_conf; |
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227 | uint32_t pm_io_base; |
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228 | |
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229 | s = (PIIX4PMState *)pci_register_device(bus, |
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230 | "PM", sizeof(PIIX4PMState), |
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231 | devfn, NULL, NULL); |
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232 | pci_conf = s->dev.config; |
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233 | pci_conf[0x00] = 0x86; |
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234 | pci_conf[0x01] = 0x80; |
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235 | pci_conf[0x02] = 0x13; |
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236 | pci_conf[0x03] = 0x71; |
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237 | pci_conf[0x08] = 0x00; // revision number |
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238 | pci_conf[0x09] = 0x00; |
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239 | pci_conf[0x0a] = 0x80; // other bridge device |
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240 | pci_conf[0x0b] = 0x06; // bridge device |
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241 | pci_conf[0x0e] = 0x00; // header_type |
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242 | pci_conf[0x3d] = 0x01; // interrupt pin 1 |
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243 | |
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244 | pm_io_base = PM_IO_BASE; |
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245 | pci_conf[0x40] = pm_io_base | 1; |
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246 | pci_conf[0x41] = pm_io_base >> 8; |
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247 | register_ioport_write(pm_io_base, 64, 2, pm_ioport_writew, s); |
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248 | register_ioport_read(pm_io_base, 64, 2, pm_ioport_readw, s); |
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249 | register_ioport_write(pm_io_base, 64, 4, pm_ioport_writel, s); |
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250 | register_ioport_read(pm_io_base, 64, 4, pm_ioport_readl, s); |
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251 | |
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252 | register_ioport_write(SMI_CMD_IO_ADDR, 1, 1, smi_cmd_writeb, s); |
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253 | register_ioport_write(ACPI_DBG_IO_ADDR, 4, 4, acpi_dbg_writel, s); |
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254 | |
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255 | /* XXX: which specification is used ? The i82731AB has different |
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256 | mappings */ |
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257 | pci_conf[0x5f] = (parallel_hds[0] != NULL ? 0x80 : 0) | 0x10; |
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258 | pci_conf[0x63] = 0x60; |
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259 | pci_conf[0x67] = (serial_hds[0] != NULL ? 0x08 : 0) | |
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260 | (serial_hds[1] != NULL ? 0x90 : 0); |
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261 | |
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262 | s->tmr_timer = qemu_new_timer(vm_clock, pm_tmr_timer, s); |
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263 | piix4_pm_state = s; |
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264 | } |
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265 | |
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266 | /* ACPI tables */ |
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267 | /* XXX: move them in the Bochs BIOS ? */ |
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268 | |
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269 | /*************************************************/ |
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270 | |
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271 | /* Table structure from Linux kernel (the ACPI tables are under the |
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272 | BSD license) */ |
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273 | |
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274 | #define ACPI_TABLE_HEADER_DEF /* ACPI common table header */ \ |
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275 | uint8_t signature [4]; /* ACPI signature (4 ASCII characters) */\ |
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276 | uint32_t length; /* Length of table, in bytes, including header */\ |
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277 | uint8_t revision; /* ACPI Specification minor version # */\ |
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278 | uint8_t checksum; /* To make sum of entire table == 0 */\ |
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279 | uint8_t oem_id [6]; /* OEM identification */\ |
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280 | uint8_t oem_table_id [8]; /* OEM table identification */\ |
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281 | uint32_t oem_revision; /* OEM revision number */\ |
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282 | uint8_t asl_compiler_id [4]; /* ASL compiler vendor ID */\ |
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283 | uint32_t asl_compiler_revision; /* ASL compiler revision number */ |
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284 | |
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285 | |
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286 | struct acpi_table_header /* ACPI common table header */ |
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287 | { |
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288 | ACPI_TABLE_HEADER_DEF |
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289 | }; |
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290 | |
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291 | struct rsdp_descriptor /* Root System Descriptor Pointer */ |
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292 | { |
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293 | uint8_t signature [8]; /* ACPI signature, contains "RSD PTR " */ |
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294 | uint8_t checksum; /* To make sum of struct == 0 */ |
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295 | uint8_t oem_id [6]; /* OEM identification */ |
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296 | uint8_t revision; /* Must be 0 for 1.0, 2 for 2.0 */ |
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297 | uint32_t rsdt_physical_address; /* 32-bit physical address of RSDT */ |
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298 | uint32_t length; /* XSDT Length in bytes including hdr */ |
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299 | uint64_t xsdt_physical_address; /* 64-bit physical address of XSDT */ |
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300 | uint8_t extended_checksum; /* Checksum of entire table */ |
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301 | uint8_t reserved [3]; /* Reserved field must be 0 */ |
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302 | }; |
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303 | |
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304 | /* |
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305 | * ACPI 1.0 Root System Description Table (RSDT) |
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306 | */ |
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307 | struct rsdt_descriptor_rev1 |
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308 | { |
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309 | ACPI_TABLE_HEADER_DEF /* ACPI common table header */ |
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310 | uint32_t table_offset_entry [2]; /* Array of pointers to other */ |
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311 | /* ACPI tables */ |
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312 | }; |
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313 | |
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314 | /* |
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315 | * ACPI 1.0 Firmware ACPI Control Structure (FACS) |
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316 | */ |
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317 | struct facs_descriptor_rev1 |
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318 | { |
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319 | uint8_t signature[4]; /* ACPI Signature */ |
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320 | uint32_t length; /* Length of structure, in bytes */ |
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321 | uint32_t hardware_signature; /* Hardware configuration signature */ |
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322 | uint32_t firmware_waking_vector; /* ACPI OS waking vector */ |
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323 | uint32_t global_lock; /* Global Lock */ |
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324 | uint32_t S4bios_f : 1; /* Indicates if S4BIOS support is present */ |
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325 | uint32_t reserved1 : 31; /* Must be 0 */ |
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326 | uint8_t resverved3 [40]; /* Reserved - must be zero */ |
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327 | }; |
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328 | |
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329 | |
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330 | /* |
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331 | * ACPI 1.0 Fixed ACPI Description Table (FADT) |
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332 | */ |
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333 | struct fadt_descriptor_rev1 |
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334 | { |
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335 | ACPI_TABLE_HEADER_DEF /* ACPI common table header */ |
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336 | uint32_t firmware_ctrl; /* Physical address of FACS */ |
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337 | uint32_t dsdt; /* Physical address of DSDT */ |
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338 | uint8_t model; /* System Interrupt Model */ |
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339 | uint8_t reserved1; /* Reserved */ |
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340 | uint16_t sci_int; /* System vector of SCI interrupt */ |
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341 | uint32_t smi_cmd; /* Port address of SMI command port */ |
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342 | uint8_t acpi_enable; /* Value to write to smi_cmd to enable ACPI */ |
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343 | uint8_t acpi_disable; /* Value to write to smi_cmd to disable ACPI */ |
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344 | uint8_t S4bios_req; /* Value to write to SMI CMD to enter S4BIOS state */ |
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345 | uint8_t reserved2; /* Reserved - must be zero */ |
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346 | uint32_t pm1a_evt_blk; /* Port address of Power Mgt 1a acpi_event Reg Blk */ |
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347 | uint32_t pm1b_evt_blk; /* Port address of Power Mgt 1b acpi_event Reg Blk */ |
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348 | uint32_t pm1a_cnt_blk; /* Port address of Power Mgt 1a Control Reg Blk */ |
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349 | uint32_t pm1b_cnt_blk; /* Port address of Power Mgt 1b Control Reg Blk */ |
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350 | uint32_t pm2_cnt_blk; /* Port address of Power Mgt 2 Control Reg Blk */ |
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351 | uint32_t pm_tmr_blk; /* Port address of Power Mgt Timer Ctrl Reg Blk */ |
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352 | uint32_t gpe0_blk; /* Port addr of General Purpose acpi_event 0 Reg Blk */ |
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353 | uint32_t gpe1_blk; /* Port addr of General Purpose acpi_event 1 Reg Blk */ |
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354 | uint8_t pm1_evt_len; /* Byte length of ports at pm1_x_evt_blk */ |
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355 | uint8_t pm1_cnt_len; /* Byte length of ports at pm1_x_cnt_blk */ |
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356 | uint8_t pm2_cnt_len; /* Byte Length of ports at pm2_cnt_blk */ |
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357 | uint8_t pm_tmr_len; /* Byte Length of ports at pm_tm_blk */ |
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358 | uint8_t gpe0_blk_len; /* Byte Length of ports at gpe0_blk */ |
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359 | uint8_t gpe1_blk_len; /* Byte Length of ports at gpe1_blk */ |
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360 | uint8_t gpe1_base; /* Offset in gpe model where gpe1 events start */ |
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361 | uint8_t reserved3; /* Reserved */ |
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362 | uint16_t plvl2_lat; /* Worst case HW latency to enter/exit C2 state */ |
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363 | uint16_t plvl3_lat; /* Worst case HW latency to enter/exit C3 state */ |
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364 | uint16_t flush_size; /* Size of area read to flush caches */ |
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365 | uint16_t flush_stride; /* Stride used in flushing caches */ |
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366 | uint8_t duty_offset; /* Bit location of duty cycle field in p_cnt reg */ |
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367 | uint8_t duty_width; /* Bit width of duty cycle field in p_cnt reg */ |
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368 | uint8_t day_alrm; /* Index to day-of-month alarm in RTC CMOS RAM */ |
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369 | uint8_t mon_alrm; /* Index to month-of-year alarm in RTC CMOS RAM */ |
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370 | uint8_t century; /* Index to century in RTC CMOS RAM */ |
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371 | uint8_t reserved4; /* Reserved */ |
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372 | uint8_t reserved4a; /* Reserved */ |
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373 | uint8_t reserved4b; /* Reserved */ |
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374 | #if 0 |
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375 | uint32_t wb_invd : 1; /* The wbinvd instruction works properly */ |
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376 | uint32_t wb_invd_flush : 1; /* The wbinvd flushes but does not invalidate */ |
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377 | uint32_t proc_c1 : 1; /* All processors support C1 state */ |
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378 | uint32_t plvl2_up : 1; /* C2 state works on MP system */ |
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379 | uint32_t pwr_button : 1; /* Power button is handled as a generic feature */ |
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380 | uint32_t sleep_button : 1; /* Sleep button is handled as a generic feature, or not present */ |
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381 | uint32_t fixed_rTC : 1; /* RTC wakeup stat not in fixed register space */ |
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382 | uint32_t rtcs4 : 1; /* RTC wakeup stat not possible from S4 */ |
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383 | uint32_t tmr_val_ext : 1; /* The tmr_val width is 32 bits (0 = 24 bits) */ |
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384 | uint32_t reserved5 : 23; /* Reserved - must be zero */ |
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385 | #else |
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386 | uint32_t flags; |
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387 | #endif |
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388 | }; |
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389 | |
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390 | /* |
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391 | * MADT values and structures |
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392 | */ |
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393 | |
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394 | /* Values for MADT PCATCompat */ |
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395 | |
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396 | #define DUAL_PIC 0 |
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397 | #define MULTIPLE_APIC 1 |
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398 | |
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399 | |
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400 | /* Master MADT */ |
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401 | |
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402 | struct multiple_apic_table |
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403 | { |
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404 | ACPI_TABLE_HEADER_DEF /* ACPI common table header */ |
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405 | uint32_t local_apic_address; /* Physical address of local APIC */ |
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406 | #if 0 |
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407 | uint32_t PCATcompat : 1; /* A one indicates system also has dual 8259s */ |
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408 | uint32_t reserved1 : 31; |
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409 | #else |
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410 | uint32_t flags; |
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411 | #endif |
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412 | }; |
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413 | |
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414 | |
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415 | /* Values for Type in APIC_HEADER_DEF */ |
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416 | |
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417 | #define APIC_PROCESSOR 0 |
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418 | #define APIC_IO 1 |
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419 | #define APIC_XRUPT_OVERRIDE 2 |
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420 | #define APIC_NMI 3 |
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421 | #define APIC_LOCAL_NMI 4 |
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422 | #define APIC_ADDRESS_OVERRIDE 5 |
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423 | #define APIC_IO_SAPIC 6 |
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424 | #define APIC_LOCAL_SAPIC 7 |
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425 | #define APIC_XRUPT_SOURCE 8 |
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426 | #define APIC_RESERVED 9 /* 9 and greater are reserved */ |
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427 | |
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428 | /* |
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429 | * MADT sub-structures (Follow MULTIPLE_APIC_DESCRIPTION_TABLE) |
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430 | */ |
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431 | #define APIC_HEADER_DEF /* Common APIC sub-structure header */\ |
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432 | uint8_t type; \ |
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433 | uint8_t length; |
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434 | |
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435 | /* Sub-structures for MADT */ |
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436 | |
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437 | struct madt_processor_apic |
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438 | { |
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439 | APIC_HEADER_DEF |
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440 | uint8_t processor_id; /* ACPI processor id */ |
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441 | uint8_t local_apic_id; /* Processor's local APIC id */ |
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442 | #if 0 |
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443 | uint32_t processor_enabled: 1; /* Processor is usable if set */ |
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444 | uint32_t reserved2 : 31; /* Reserved, must be zero */ |
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445 | #else |
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446 | uint32_t flags; |
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447 | #endif |
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448 | }; |
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449 | |
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450 | struct madt_io_apic |
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451 | { |
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452 | APIC_HEADER_DEF |
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453 | uint8_t io_apic_id; /* I/O APIC ID */ |
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454 | uint8_t reserved; /* Reserved - must be zero */ |
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455 | uint32_t address; /* APIC physical address */ |
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456 | uint32_t interrupt; /* Global system interrupt where INTI |
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457 | * lines start */ |
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458 | }; |
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459 | |
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460 | #include "acpi-dsdt.hex" |
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461 | |
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462 | static int acpi_checksum(const uint8_t *data, int len) |
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463 | { |
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464 | int sum, i; |
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465 | sum = 0; |
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466 | for(i = 0; i < len; i++) |
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467 | sum += data[i]; |
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468 | return (-sum) & 0xff; |
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469 | } |
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470 | |
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471 | static void acpi_build_table_header(struct acpi_table_header *h, |
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472 | char *sig, int len) |
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473 | { |
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474 | memcpy(h->signature, sig, 4); |
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475 | h->length = cpu_to_le32(len); |
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476 | h->revision = 0; |
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477 | memcpy(h->oem_id, "QEMU ", 6); |
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478 | memcpy(h->oem_table_id, "QEMU", 4); |
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479 | memcpy(h->oem_table_id + 4, sig, 4); |
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480 | h->oem_revision = cpu_to_le32(1); |
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481 | memcpy(h->asl_compiler_id, "QEMU", 4); |
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482 | h->asl_compiler_revision = cpu_to_le32(1); |
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483 | h->checksum = acpi_checksum((void *)h, len); |
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484 | } |
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485 | |
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486 | #define ACPI_TABLES_BASE 0x000e8000 |
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487 | |
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488 | /* base_addr must be a multiple of 4KB */ |
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489 | void acpi_bios_init(void) |
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490 | { |
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491 | struct rsdp_descriptor *rsdp; |
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492 | struct rsdt_descriptor_rev1 *rsdt; |
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493 | struct fadt_descriptor_rev1 *fadt; |
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494 | struct facs_descriptor_rev1 *facs; |
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495 | struct multiple_apic_table *madt; |
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496 | uint8_t *dsdt; |
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497 | uint32_t base_addr, rsdt_addr, fadt_addr, addr, facs_addr, dsdt_addr; |
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498 | uint32_t pm_io_base, acpi_tables_size, madt_addr, madt_size; |
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499 | int i; |
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500 | |
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501 | /* compute PCI I/O addresses */ |
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502 | pm_io_base = (piix4_pm_state->dev.config[0x40] | |
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503 | (piix4_pm_state->dev.config[0x41] << 8)) & ~0x3f; |
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504 | |
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505 | base_addr = ACPI_TABLES_BASE; |
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506 | |
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507 | /* reserve memory space for tables */ |
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508 | addr = base_addr; |
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509 | rsdp = (void *)(phys_ram_base + addr); |
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510 | addr += sizeof(*rsdp); |
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511 | |
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512 | rsdt_addr = addr; |
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513 | rsdt = (void *)(phys_ram_base + addr); |
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514 | addr += sizeof(*rsdt); |
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515 | |
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516 | fadt_addr = addr; |
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517 | fadt = (void *)(phys_ram_base + addr); |
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518 | addr += sizeof(*fadt); |
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519 | |
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520 | /* XXX: FACS should be in RAM */ |
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521 | addr = (addr + 63) & ~63; /* 64 byte alignment for FACS */ |
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522 | facs_addr = addr; |
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523 | facs = (void *)(phys_ram_base + addr); |
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524 | addr += sizeof(*facs); |
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525 | |
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526 | dsdt_addr = addr; |
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527 | dsdt = (void *)(phys_ram_base + addr); |
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528 | addr += sizeof(AmlCode); |
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529 | |
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530 | addr = (addr + 7) & ~7; |
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531 | madt_addr = addr; |
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532 | madt_size = sizeof(*madt) + |
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533 | sizeof(struct madt_processor_apic) * smp_cpus + |
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534 | sizeof(struct madt_io_apic); |
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535 | madt = (void *)(phys_ram_base + addr); |
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536 | addr += madt_size; |
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537 | |
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538 | acpi_tables_size = addr - base_addr; |
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539 | |
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540 | cpu_register_physical_memory(base_addr, acpi_tables_size, |
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541 | base_addr | IO_MEM_ROM); |
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542 | |
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543 | /* RSDP */ |
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544 | memset(rsdp, 0, sizeof(*rsdp)); |
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545 | memcpy(rsdp->signature, "RSD PTR ", 8); |
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546 | memcpy(rsdp->oem_id, "QEMU ", 6); |
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547 | rsdp->rsdt_physical_address = cpu_to_le32(rsdt_addr); |
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548 | rsdp->checksum = acpi_checksum((void *)rsdp, 20); |
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549 | |
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550 | /* RSDT */ |
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551 | rsdt->table_offset_entry[0] = cpu_to_le32(fadt_addr); |
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552 | rsdt->table_offset_entry[1] = cpu_to_le32(madt_addr); |
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553 | acpi_build_table_header((struct acpi_table_header *)rsdt, |
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554 | "RSDT", sizeof(*rsdt)); |
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555 | |
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556 | /* FADT */ |
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557 | memset(fadt, 0, sizeof(*fadt)); |
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558 | fadt->firmware_ctrl = cpu_to_le32(facs_addr); |
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559 | fadt->dsdt = cpu_to_le32(dsdt_addr); |
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560 | fadt->model = 1; |
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561 | fadt->reserved1 = 0; |
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562 | fadt->sci_int = cpu_to_le16(piix4_pm_state->dev.config[0x3c]); |
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563 | fadt->smi_cmd = cpu_to_le32(SMI_CMD_IO_ADDR); |
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564 | fadt->acpi_enable = 0xf1; |
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565 | fadt->acpi_disable = 0xf0; |
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566 | fadt->pm1a_evt_blk = cpu_to_le32(pm_io_base); |
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567 | fadt->pm1a_cnt_blk = cpu_to_le32(pm_io_base + 0x04); |
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568 | fadt->pm_tmr_blk = cpu_to_le32(pm_io_base + 0x08); |
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569 | fadt->pm1_evt_len = 4; |
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570 | fadt->pm1_cnt_len = 2; |
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571 | fadt->pm_tmr_len = 4; |
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572 | fadt->plvl2_lat = cpu_to_le16(50); |
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573 | fadt->plvl3_lat = cpu_to_le16(50); |
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574 | fadt->plvl3_lat = cpu_to_le16(50); |
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575 | /* WBINVD + PROC_C1 + PWR_BUTTON + SLP_BUTTON + FIX_RTC */ |
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576 | fadt->flags = cpu_to_le32((1 << 0) | (1 << 2) | (1 << 4) | (1 << 5) | (1 << 6)); |
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577 | acpi_build_table_header((struct acpi_table_header *)fadt, "FACP", |
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578 | sizeof(*fadt)); |
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579 | |
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580 | /* FACS */ |
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581 | memset(facs, 0, sizeof(*facs)); |
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582 | memcpy(facs->signature, "FACS", 4); |
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583 | facs->length = cpu_to_le32(sizeof(*facs)); |
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584 | |
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585 | /* DSDT */ |
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586 | memcpy(dsdt, AmlCode, sizeof(AmlCode)); |
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587 | |
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588 | /* MADT */ |
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589 | { |
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590 | struct madt_processor_apic *apic; |
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591 | struct madt_io_apic *io_apic; |
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592 | |
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593 | memset(madt, 0, madt_size); |
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594 | madt->local_apic_address = cpu_to_le32(0xfee00000); |
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595 | madt->flags = cpu_to_le32(1); |
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596 | apic = (void *)(madt + 1); |
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597 | for(i=0;i<smp_cpus;i++) { |
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598 | apic->type = APIC_PROCESSOR; |
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599 | apic->length = sizeof(*apic); |
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600 | apic->processor_id = i; |
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601 | apic->local_apic_id = i; |
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602 | apic->flags = cpu_to_le32(1); |
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603 | apic++; |
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604 | } |
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605 | io_apic = (void *)apic; |
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606 | io_apic->type = APIC_IO; |
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607 | io_apic->length = sizeof(*io_apic); |
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608 | io_apic->io_apic_id = smp_cpus; |
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609 | io_apic->address = cpu_to_le32(0xfec00000); |
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610 | io_apic->interrupt = cpu_to_le32(0); |
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611 | |
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612 | acpi_build_table_header((struct acpi_table_header *)madt, |
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613 | "APIC", madt_size); |
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614 | } |
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615 | } |
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