1 | /* |
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2 | * dyngen helpers |
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3 | * |
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4 | * Copyright (c) 2003 Fabrice Bellard |
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5 | * |
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6 | * This library is free software; you can redistribute it and/or |
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7 | * modify it under the terms of the GNU Lesser General Public |
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8 | * License as published by the Free Software Foundation; either |
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9 | * version 2 of the License, or (at your option) any later version. |
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10 | * |
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11 | * This library is distributed in the hope that it will be useful, |
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12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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14 | * Lesser General Public License for more details. |
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15 | * |
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16 | * You should have received a copy of the GNU Lesser General Public |
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17 | * License along with this library; if not, write to the Free Software |
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18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
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19 | */ |
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20 | |
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21 | int __op_param1, __op_param2, __op_param3; |
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22 | #ifdef __sparc__ |
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23 | void __op_gen_label1(){} |
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24 | void __op_gen_label2(){} |
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25 | void __op_gen_label3(){} |
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26 | #else |
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27 | int __op_gen_label1, __op_gen_label2, __op_gen_label3; |
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28 | #endif |
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29 | int __op_jmp0, __op_jmp1, __op_jmp2, __op_jmp3; |
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30 | |
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31 | #ifdef __i386__ |
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32 | static inline void flush_icache_range(unsigned long start, unsigned long stop) |
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33 | { |
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34 | } |
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35 | #endif |
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36 | |
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37 | #ifdef __x86_64__ |
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38 | static inline void flush_icache_range(unsigned long start, unsigned long stop) |
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39 | { |
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40 | } |
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41 | #endif |
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42 | |
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43 | #ifdef __s390__ |
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44 | static inline void flush_icache_range(unsigned long start, unsigned long stop) |
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45 | { |
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46 | } |
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47 | #endif |
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48 | |
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49 | #ifdef __ia64__ |
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50 | static inline void flush_icache_range(unsigned long start, unsigned long stop) |
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51 | { |
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52 | while (start < stop) { |
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53 | asm volatile ("fc %0" :: "r"(start)); |
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54 | start += 32; |
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55 | } |
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56 | asm volatile (";;sync.i;;srlz.i;;"); |
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57 | } |
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58 | #endif |
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59 | |
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60 | #ifdef __powerpc__ |
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61 | |
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62 | #define MIN_CACHE_LINE_SIZE 8 /* conservative value */ |
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63 | |
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64 | static void inline flush_icache_range(unsigned long start, unsigned long stop) |
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65 | { |
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66 | unsigned long p; |
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67 | |
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68 | start &= ~(MIN_CACHE_LINE_SIZE - 1); |
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69 | stop = (stop + MIN_CACHE_LINE_SIZE - 1) & ~(MIN_CACHE_LINE_SIZE - 1); |
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70 | |
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71 | for (p = start; p < stop; p += MIN_CACHE_LINE_SIZE) { |
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72 | asm volatile ("dcbst 0,%0" : : "r"(p) : "memory"); |
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73 | } |
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74 | asm volatile ("sync" : : : "memory"); |
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75 | for (p = start; p < stop; p += MIN_CACHE_LINE_SIZE) { |
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76 | asm volatile ("icbi 0,%0" : : "r"(p) : "memory"); |
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77 | } |
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78 | asm volatile ("sync" : : : "memory"); |
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79 | asm volatile ("isync" : : : "memory"); |
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80 | } |
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81 | #endif |
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82 | |
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83 | #ifdef __alpha__ |
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84 | static inline void flush_icache_range(unsigned long start, unsigned long stop) |
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85 | { |
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86 | asm ("imb"); |
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87 | } |
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88 | #endif |
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89 | |
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90 | #ifdef __sparc__ |
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91 | |
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92 | static void inline flush_icache_range(unsigned long start, unsigned long stop) |
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93 | { |
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94 | unsigned long p; |
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95 | |
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96 | p = start & ~(8UL - 1UL); |
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97 | stop = (stop + (8UL - 1UL)) & ~(8UL - 1UL); |
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98 | |
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99 | for (; p < stop; p += 8) |
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100 | __asm__ __volatile__("flush\t%0" : : "r" (p)); |
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101 | } |
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102 | |
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103 | #endif |
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104 | |
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105 | #ifdef __arm__ |
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106 | static inline void flush_icache_range(unsigned long start, unsigned long stop) |
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107 | { |
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108 | register unsigned long _beg __asm ("a1") = start; |
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109 | register unsigned long _end __asm ("a2") = stop; |
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110 | register unsigned long _flg __asm ("a3") = 0; |
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111 | __asm __volatile__ ("swi 0x9f0002" : : "r" (_beg), "r" (_end), "r" (_flg)); |
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112 | } |
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113 | #endif |
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114 | |
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115 | #ifdef __mc68000 |
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116 | #include <asm/cachectl.h> |
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117 | static inline void flush_icache_range(unsigned long start, unsigned long stop) |
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118 | { |
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119 | cacheflush(start,FLUSH_SCOPE_LINE,FLUSH_CACHE_BOTH,stop-start+16); |
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120 | } |
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121 | #endif |
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122 | |
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123 | #ifdef __alpha__ |
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124 | |
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125 | register int gp asm("$29"); |
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126 | |
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127 | static inline void immediate_ldah(void *p, int val) { |
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128 | uint32_t *dest = p; |
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129 | long high = ((val >> 16) + ((val >> 15) & 1)) & 0xffff; |
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130 | |
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131 | *dest &= ~0xffff; |
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132 | *dest |= high; |
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133 | *dest |= 31 << 16; |
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134 | } |
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135 | static inline void immediate_lda(void *dest, int val) { |
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136 | *(uint16_t *) dest = val; |
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137 | } |
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138 | void fix_bsr(void *p, int offset) { |
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139 | uint32_t *dest = p; |
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140 | *dest &= ~((1 << 21) - 1); |
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141 | *dest |= (offset >> 2) & ((1 << 21) - 1); |
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142 | } |
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143 | |
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144 | #endif /* __alpha__ */ |
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145 | |
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146 | #ifdef __arm__ |
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147 | |
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148 | #define MAX_OP_SIZE (128 * 4) /* in bytes */ |
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149 | /* max size of the code that can be generated without calling arm_flush_ldr */ |
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150 | #define MAX_FRAG_SIZE (1024 * 4) |
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151 | //#define MAX_FRAG_SIZE (135 * 4) /* for testing */ |
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152 | |
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153 | typedef struct LDREntry { |
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154 | uint8_t *ptr; |
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155 | uint32_t *data_ptr; |
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156 | } LDREntry; |
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157 | |
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158 | static LDREntry arm_ldr_table[1024]; |
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159 | static uint32_t arm_data_table[1024]; |
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160 | |
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161 | extern char exec_loop; |
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162 | |
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163 | static inline void arm_reloc_pc24(uint32_t *ptr, uint32_t insn, int val) |
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164 | { |
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165 | *ptr = (insn & ~0xffffff) | ((insn + ((val - (int)ptr) >> 2)) & 0xffffff); |
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166 | } |
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167 | |
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168 | static uint8_t *arm_flush_ldr(uint8_t *gen_code_ptr, |
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169 | LDREntry *ldr_start, LDREntry *ldr_end, |
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170 | uint32_t *data_start, uint32_t *data_end, |
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171 | int gen_jmp) |
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172 | { |
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173 | LDREntry *le; |
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174 | uint32_t *ptr; |
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175 | int offset, data_size, target; |
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176 | uint8_t *data_ptr; |
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177 | uint32_t insn; |
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178 | |
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179 | data_size = (uint8_t *)data_end - (uint8_t *)data_start; |
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180 | |
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181 | if (gen_jmp) { |
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182 | /* generate branch to skip the data */ |
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183 | if (data_size == 0) |
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184 | return gen_code_ptr; |
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185 | target = (long)gen_code_ptr + data_size + 4; |
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186 | arm_reloc_pc24((uint32_t *)gen_code_ptr, 0xeafffffe, target); |
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187 | gen_code_ptr += 4; |
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188 | } |
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189 | |
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190 | /* copy the data */ |
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191 | data_ptr = gen_code_ptr; |
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192 | memcpy(gen_code_ptr, data_start, data_size); |
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193 | gen_code_ptr += data_size; |
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194 | |
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195 | /* patch the ldr to point to the data */ |
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196 | for(le = ldr_start; le < ldr_end; le++) { |
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197 | ptr = (uint32_t *)le->ptr; |
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198 | offset = ((unsigned long)(le->data_ptr) - (unsigned long)data_start) + |
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199 | (unsigned long)data_ptr - |
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200 | (unsigned long)ptr - 8; |
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201 | insn = *ptr & ~(0xfff | 0x00800000); |
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202 | if (offset < 0) { |
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203 | offset = - offset; |
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204 | } else { |
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205 | insn |= 0x00800000; |
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206 | } |
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207 | if (offset > 0xfff) { |
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208 | fprintf(stderr, "Error ldr offset\n"); |
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209 | abort(); |
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210 | } |
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211 | insn |= offset; |
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212 | *ptr = insn; |
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213 | } |
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214 | return gen_code_ptr; |
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215 | } |
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216 | |
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217 | #endif /* __arm__ */ |
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218 | |
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219 | #ifdef __ia64 |
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220 | |
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221 | |
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222 | /* Patch instruction with "val" where "mask" has 1 bits. */ |
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223 | static inline void ia64_patch (uint64_t insn_addr, uint64_t mask, uint64_t val) |
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224 | { |
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225 | uint64_t m0, m1, v0, v1, b0, b1, *b = (uint64_t *) (insn_addr & -16); |
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226 | # define insn_mask ((1UL << 41) - 1) |
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227 | unsigned long shift; |
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228 | |
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229 | b0 = b[0]; b1 = b[1]; |
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230 | shift = 5 + 41 * (insn_addr % 16); /* 5 template, 3 x 41-bit insns */ |
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231 | if (shift >= 64) { |
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232 | m1 = mask << (shift - 64); |
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233 | v1 = val << (shift - 64); |
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234 | } else { |
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235 | m0 = mask << shift; m1 = mask >> (64 - shift); |
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236 | v0 = val << shift; v1 = val >> (64 - shift); |
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237 | b[0] = (b0 & ~m0) | (v0 & m0); |
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238 | } |
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239 | b[1] = (b1 & ~m1) | (v1 & m1); |
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240 | } |
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241 | |
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242 | static inline void ia64_patch_imm60 (uint64_t insn_addr, uint64_t val) |
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243 | { |
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244 | ia64_patch(insn_addr, |
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245 | 0x011ffffe000UL, |
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246 | ( ((val & 0x0800000000000000UL) >> 23) /* bit 59 -> 36 */ |
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247 | | ((val & 0x00000000000fffffUL) << 13) /* bit 0 -> 13 */)); |
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248 | ia64_patch(insn_addr - 1, 0x1fffffffffcUL, val >> 18); |
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249 | } |
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250 | |
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251 | static inline void ia64_imm64 (void *insn, uint64_t val) |
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252 | { |
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253 | /* Ignore the slot number of the relocation; GCC and Intel |
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254 | toolchains differed for some time on whether IMM64 relocs are |
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255 | against slot 1 (Intel) or slot 2 (GCC). */ |
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256 | uint64_t insn_addr = (uint64_t) insn & ~3UL; |
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257 | |
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258 | ia64_patch(insn_addr + 2, |
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259 | 0x01fffefe000UL, |
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260 | ( ((val & 0x8000000000000000UL) >> 27) /* bit 63 -> 36 */ |
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261 | | ((val & 0x0000000000200000UL) << 0) /* bit 21 -> 21 */ |
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262 | | ((val & 0x00000000001f0000UL) << 6) /* bit 16 -> 22 */ |
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263 | | ((val & 0x000000000000ff80UL) << 20) /* bit 7 -> 27 */ |
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264 | | ((val & 0x000000000000007fUL) << 13) /* bit 0 -> 13 */) |
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265 | ); |
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266 | ia64_patch(insn_addr + 1, 0x1ffffffffffUL, val >> 22); |
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267 | } |
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268 | |
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269 | static inline void ia64_imm60b (void *insn, uint64_t val) |
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270 | { |
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271 | /* Ignore the slot number of the relocation; GCC and Intel |
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272 | toolchains differed for some time on whether IMM64 relocs are |
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273 | against slot 1 (Intel) or slot 2 (GCC). */ |
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274 | uint64_t insn_addr = (uint64_t) insn & ~3UL; |
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275 | |
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276 | if (val + ((uint64_t) 1 << 59) >= (1UL << 60)) |
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277 | fprintf(stderr, "%s: value %ld out of IMM60 range\n", |
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278 | __FUNCTION__, (int64_t) val); |
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279 | ia64_patch_imm60(insn_addr + 2, val); |
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280 | } |
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281 | |
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282 | static inline void ia64_imm22 (void *insn, uint64_t val) |
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283 | { |
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284 | if (val + (1 << 21) >= (1 << 22)) |
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285 | fprintf(stderr, "%s: value %li out of IMM22 range\n", |
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286 | __FUNCTION__, (int64_t)val); |
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287 | ia64_patch((uint64_t) insn, 0x01fffcfe000UL, |
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288 | ( ((val & 0x200000UL) << 15) /* bit 21 -> 36 */ |
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289 | | ((val & 0x1f0000UL) << 6) /* bit 16 -> 22 */ |
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290 | | ((val & 0x00ff80UL) << 20) /* bit 7 -> 27 */ |
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291 | | ((val & 0x00007fUL) << 13) /* bit 0 -> 13 */)); |
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292 | } |
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293 | |
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294 | /* Like ia64_imm22(), but also clear bits 20-21. For addl, this has |
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295 | the effect of turning "addl rX=imm22,rY" into "addl |
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296 | rX=imm22,r0". */ |
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297 | static inline void ia64_imm22_r0 (void *insn, uint64_t val) |
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298 | { |
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299 | if (val + (1 << 21) >= (1 << 22)) |
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300 | fprintf(stderr, "%s: value %li out of IMM22 range\n", |
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301 | __FUNCTION__, (int64_t)val); |
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302 | ia64_patch((uint64_t) insn, 0x01fffcfe000UL | (0x3UL << 20), |
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303 | ( ((val & 0x200000UL) << 15) /* bit 21 -> 36 */ |
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304 | | ((val & 0x1f0000UL) << 6) /* bit 16 -> 22 */ |
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305 | | ((val & 0x00ff80UL) << 20) /* bit 7 -> 27 */ |
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306 | | ((val & 0x00007fUL) << 13) /* bit 0 -> 13 */)); |
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307 | } |
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308 | |
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309 | static inline void ia64_imm21b (void *insn, uint64_t val) |
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310 | { |
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311 | if (val + (1 << 20) >= (1 << 21)) |
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312 | fprintf(stderr, "%s: value %li out of IMM21b range\n", |
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313 | __FUNCTION__, (int64_t)val); |
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314 | ia64_patch((uint64_t) insn, 0x11ffffe000UL, |
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315 | ( ((val & 0x100000UL) << 16) /* bit 20 -> 36 */ |
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316 | | ((val & 0x0fffffUL) << 13) /* bit 0 -> 13 */)); |
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317 | } |
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318 | |
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319 | static inline void ia64_nop_b (void *insn) |
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320 | { |
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321 | ia64_patch((uint64_t) insn, (1UL << 41) - 1, 2UL << 37); |
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322 | } |
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323 | |
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324 | static inline void ia64_ldxmov(void *insn, uint64_t val) |
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325 | { |
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326 | if (val + (1 << 21) < (1 << 22)) |
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327 | ia64_patch((uint64_t) insn, 0x1fff80fe000UL, 8UL << 37); |
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328 | } |
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329 | |
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330 | static inline int ia64_patch_ltoff(void *insn, uint64_t val, |
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331 | int relaxable) |
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332 | { |
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333 | if (relaxable && (val + (1 << 21) < (1 << 22))) { |
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334 | ia64_imm22_r0(insn, val); |
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335 | return 0; |
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336 | } |
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337 | return 1; |
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338 | } |
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339 | |
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340 | struct ia64_fixup { |
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341 | struct ia64_fixup *next; |
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342 | void *addr; /* address that needs to be patched */ |
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343 | long value; |
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344 | }; |
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345 | |
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346 | #define IA64_PLT(insn, plt_index) \ |
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347 | do { \ |
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348 | struct ia64_fixup *fixup = alloca(sizeof(*fixup)); \ |
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349 | fixup->next = plt_fixes; \ |
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350 | plt_fixes = fixup; \ |
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351 | fixup->addr = (insn); \ |
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352 | fixup->value = (plt_index); \ |
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353 | plt_offset[(plt_index)] = 1; \ |
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354 | } while (0) |
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355 | |
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356 | #define IA64_LTOFF(insn, val, relaxable) \ |
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357 | do { \ |
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358 | if (ia64_patch_ltoff(insn, val, relaxable)) { \ |
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359 | struct ia64_fixup *fixup = alloca(sizeof(*fixup)); \ |
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360 | fixup->next = ltoff_fixes; \ |
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361 | ltoff_fixes = fixup; \ |
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362 | fixup->addr = (insn); \ |
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363 | fixup->value = (val); \ |
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364 | } \ |
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365 | } while (0) |
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366 | |
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367 | static inline void ia64_apply_fixes (uint8_t **gen_code_pp, |
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368 | struct ia64_fixup *ltoff_fixes, |
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369 | uint64_t gp, |
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370 | struct ia64_fixup *plt_fixes, |
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371 | int num_plts, |
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372 | unsigned long *plt_target, |
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373 | unsigned int *plt_offset) |
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374 | { |
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375 | static const uint8_t plt_bundle[] = { |
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376 | 0x04, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, /* nop 0; movl r1=GP */ |
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377 | 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x60, |
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378 | |
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379 | 0x05, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, /* nop 0; brl IP */ |
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380 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0 |
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381 | }; |
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382 | uint8_t *gen_code_ptr = *gen_code_pp, *plt_start, *got_start, *vp; |
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383 | struct ia64_fixup *fixup; |
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384 | unsigned int offset = 0; |
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385 | struct fdesc { |
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386 | long ip; |
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387 | long gp; |
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388 | } *fdesc; |
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389 | int i; |
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390 | |
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391 | if (plt_fixes) { |
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392 | plt_start = gen_code_ptr; |
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393 | |
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394 | for (i = 0; i < num_plts; ++i) { |
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395 | if (plt_offset[i]) { |
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396 | plt_offset[i] = offset; |
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397 | offset += sizeof(plt_bundle); |
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398 | |
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399 | fdesc = (struct fdesc *) plt_target[i]; |
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400 | memcpy(gen_code_ptr, plt_bundle, sizeof(plt_bundle)); |
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401 | ia64_imm64 (gen_code_ptr + 0x02, fdesc->gp); |
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402 | ia64_imm60b(gen_code_ptr + 0x12, |
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403 | (fdesc->ip - (long) (gen_code_ptr + 0x10)) >> 4); |
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404 | gen_code_ptr += sizeof(plt_bundle); |
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405 | } |
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406 | } |
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407 | |
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408 | for (fixup = plt_fixes; fixup; fixup = fixup->next) |
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409 | ia64_imm21b(fixup->addr, |
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410 | ((long) plt_start + plt_offset[fixup->value] |
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411 | - ((long) fixup->addr & ~0xf)) >> 4); |
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412 | } |
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413 | |
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414 | got_start = gen_code_ptr; |
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415 | |
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416 | /* First, create the GOT: */ |
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417 | for (fixup = ltoff_fixes; fixup; fixup = fixup->next) { |
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418 | /* first check if we already have this value in the GOT: */ |
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419 | for (vp = got_start; vp < gen_code_ptr; ++vp) |
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420 | if (*(uint64_t *) vp == fixup->value) |
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421 | break; |
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422 | if (vp == gen_code_ptr) { |
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423 | /* Nope, we need to put the value in the GOT: */ |
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424 | *(uint64_t *) vp = fixup->value; |
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425 | gen_code_ptr += 8; |
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426 | } |
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427 | ia64_imm22(fixup->addr, (long) vp - gp); |
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428 | } |
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429 | /* Keep code ptr aligned. */ |
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430 | if ((long) gen_code_ptr & 15) |
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431 | gen_code_ptr += 8; |
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432 | *gen_code_pp = gen_code_ptr; |
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433 | } |
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434 | |
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435 | #endif |
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