1 | /* |
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2 | * include/asm-i386/processor.h |
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3 | * |
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4 | * Copyright (C) 1994 Linus Torvalds |
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5 | */ |
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6 | |
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7 | #ifndef __ASM_I386_PROCESSOR_H |
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8 | #define __ASM_I386_PROCESSOR_H |
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9 | |
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10 | #include <asm/vm86.h> |
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11 | #include <asm/math_emu.h> |
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12 | #include <asm/segment.h> |
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13 | #include <asm/page.h> |
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14 | #include <asm/types.h> |
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15 | #include <asm/sigcontext.h> |
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16 | #include <asm/cpufeature.h> |
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17 | #include <asm/msr.h> |
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18 | #include <asm/system.h> |
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19 | #include <linux/cache.h> |
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20 | #include <linux/threads.h> |
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21 | #include <asm/percpu.h> |
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22 | #include <linux/cpumask.h> |
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23 | #include <xen/interface/physdev.h> |
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24 | |
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25 | /* flag for disabling the tsc */ |
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26 | extern int tsc_disable; |
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27 | |
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28 | struct desc_struct { |
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29 | unsigned long a,b; |
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30 | }; |
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31 | |
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32 | #define desc_empty(desc) \ |
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33 | (!((desc)->a | (desc)->b)) |
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34 | |
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35 | #define desc_equal(desc1, desc2) \ |
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36 | (((desc1)->a == (desc2)->a) && ((desc1)->b == (desc2)->b)) |
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37 | /* |
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38 | * Default implementation of macro that returns current |
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39 | * instruction pointer ("program counter"). |
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40 | */ |
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41 | #define current_text_addr() ({ void *pc; __asm__("movl $1f,%0\n1:":"=g" (pc)); pc; }) |
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42 | |
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43 | /* |
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44 | * CPU type and hardware bug flags. Kept separately for each CPU. |
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45 | * Members of this structure are referenced in head.S, so think twice |
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46 | * before touching them. [mj] |
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47 | */ |
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48 | |
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49 | struct cpuinfo_x86 { |
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50 | __u8 x86; /* CPU family */ |
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51 | __u8 x86_vendor; /* CPU vendor */ |
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52 | __u8 x86_model; |
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53 | __u8 x86_mask; |
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54 | char wp_works_ok; /* It doesn't on 386's */ |
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55 | char hlt_works_ok; /* Problems on some 486Dx4's and old 386's */ |
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56 | char hard_math; |
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57 | char rfu; |
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58 | int cpuid_level; /* Maximum supported CPUID level, -1=no CPUID */ |
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59 | unsigned long x86_capability[NCAPINTS]; |
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60 | char x86_vendor_id[16]; |
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61 | char x86_model_id[64]; |
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62 | int x86_cache_size; /* in KB - valid for CPUS which support this |
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63 | call */ |
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64 | int x86_cache_alignment; /* In bytes */ |
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65 | char fdiv_bug; |
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66 | char f00f_bug; |
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67 | char coma_bug; |
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68 | char pad0; |
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69 | int x86_power; |
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70 | unsigned long loops_per_jiffy; |
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71 | #ifdef CONFIG_SMP |
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72 | cpumask_t llc_shared_map; /* cpus sharing the last level cache */ |
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73 | #endif |
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74 | unsigned char x86_max_cores; /* cpuid returned max cores value */ |
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75 | unsigned char apicid; |
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76 | #ifdef CONFIG_SMP |
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77 | unsigned char booted_cores; /* number of cores as seen by OS */ |
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78 | __u8 phys_proc_id; /* Physical processor id. */ |
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79 | __u8 cpu_core_id; /* Core id */ |
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80 | #endif |
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81 | } __attribute__((__aligned__(SMP_CACHE_BYTES))); |
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82 | |
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83 | #define X86_VENDOR_INTEL 0 |
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84 | #define X86_VENDOR_CYRIX 1 |
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85 | #define X86_VENDOR_AMD 2 |
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86 | #define X86_VENDOR_UMC 3 |
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87 | #define X86_VENDOR_NEXGEN 4 |
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88 | #define X86_VENDOR_CENTAUR 5 |
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89 | #define X86_VENDOR_RISE 6 |
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90 | #define X86_VENDOR_TRANSMETA 7 |
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91 | #define X86_VENDOR_NSC 8 |
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92 | #define X86_VENDOR_NUM 9 |
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93 | #define X86_VENDOR_UNKNOWN 0xff |
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94 | |
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95 | /* |
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96 | * capabilities of CPUs |
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97 | */ |
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98 | |
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99 | extern struct cpuinfo_x86 boot_cpu_data; |
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100 | extern struct cpuinfo_x86 new_cpu_data; |
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101 | #ifndef CONFIG_X86_NO_TSS |
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102 | extern struct tss_struct doublefault_tss; |
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103 | DECLARE_PER_CPU(struct tss_struct, init_tss); |
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104 | #endif |
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105 | |
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106 | #ifdef CONFIG_SMP |
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107 | extern struct cpuinfo_x86 cpu_data[]; |
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108 | #define current_cpu_data cpu_data[smp_processor_id()] |
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109 | #else |
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110 | #define cpu_data (&boot_cpu_data) |
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111 | #define current_cpu_data boot_cpu_data |
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112 | #endif |
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113 | |
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114 | extern int cpu_llc_id[NR_CPUS]; |
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115 | extern char ignore_fpu_irq; |
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116 | |
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117 | extern void identify_cpu(struct cpuinfo_x86 *); |
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118 | extern void print_cpu_info(struct cpuinfo_x86 *); |
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119 | extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c); |
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120 | extern unsigned short num_cache_leaves; |
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121 | |
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122 | #ifdef CONFIG_X86_HT |
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123 | extern void detect_ht(struct cpuinfo_x86 *c); |
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124 | #else |
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125 | static inline void detect_ht(struct cpuinfo_x86 *c) {} |
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126 | #endif |
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127 | |
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128 | /* |
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129 | * EFLAGS bits |
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130 | */ |
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131 | #define X86_EFLAGS_CF 0x00000001 /* Carry Flag */ |
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132 | #define X86_EFLAGS_PF 0x00000004 /* Parity Flag */ |
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133 | #define X86_EFLAGS_AF 0x00000010 /* Auxillary carry Flag */ |
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134 | #define X86_EFLAGS_ZF 0x00000040 /* Zero Flag */ |
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135 | #define X86_EFLAGS_SF 0x00000080 /* Sign Flag */ |
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136 | #define X86_EFLAGS_TF 0x00000100 /* Trap Flag */ |
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137 | #define X86_EFLAGS_IF 0x00000200 /* Interrupt Flag */ |
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138 | #define X86_EFLAGS_DF 0x00000400 /* Direction Flag */ |
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139 | #define X86_EFLAGS_OF 0x00000800 /* Overflow Flag */ |
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140 | #define X86_EFLAGS_IOPL 0x00003000 /* IOPL mask */ |
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141 | #define X86_EFLAGS_NT 0x00004000 /* Nested Task */ |
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142 | #define X86_EFLAGS_RF 0x00010000 /* Resume Flag */ |
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143 | #define X86_EFLAGS_VM 0x00020000 /* Virtual Mode */ |
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144 | #define X86_EFLAGS_AC 0x00040000 /* Alignment Check */ |
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145 | #define X86_EFLAGS_VIF 0x00080000 /* Virtual Interrupt Flag */ |
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146 | #define X86_EFLAGS_VIP 0x00100000 /* Virtual Interrupt Pending */ |
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147 | #define X86_EFLAGS_ID 0x00200000 /* CPUID detection flag */ |
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148 | |
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149 | /* |
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150 | * Generic CPUID function |
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151 | * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx |
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152 | * resulting in stale register contents being returned. |
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153 | */ |
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154 | static inline void cpuid(unsigned int op, unsigned int *eax, unsigned int *ebx, unsigned int *ecx, unsigned int *edx) |
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155 | { |
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156 | __asm__(XEN_CPUID |
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157 | : "=a" (*eax), |
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158 | "=b" (*ebx), |
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159 | "=c" (*ecx), |
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160 | "=d" (*edx) |
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161 | : "0" (op), "c"(0)); |
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162 | } |
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163 | |
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164 | /* Some CPUID calls want 'count' to be placed in ecx */ |
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165 | static inline void cpuid_count(int op, int count, int *eax, int *ebx, int *ecx, |
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166 | int *edx) |
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167 | { |
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168 | __asm__(XEN_CPUID |
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169 | : "=a" (*eax), |
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170 | "=b" (*ebx), |
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171 | "=c" (*ecx), |
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172 | "=d" (*edx) |
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173 | : "0" (op), "c" (count)); |
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174 | } |
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175 | |
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176 | /* |
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177 | * CPUID functions returning a single datum |
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178 | */ |
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179 | static inline unsigned int cpuid_eax(unsigned int op) |
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180 | { |
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181 | unsigned int eax; |
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182 | |
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183 | __asm__(XEN_CPUID |
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184 | : "=a" (eax) |
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185 | : "0" (op) |
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186 | : "bx", "cx", "dx"); |
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187 | return eax; |
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188 | } |
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189 | static inline unsigned int cpuid_ebx(unsigned int op) |
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190 | { |
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191 | unsigned int eax, ebx; |
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192 | |
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193 | __asm__(XEN_CPUID |
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194 | : "=a" (eax), "=b" (ebx) |
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195 | : "0" (op) |
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196 | : "cx", "dx" ); |
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197 | return ebx; |
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198 | } |
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199 | static inline unsigned int cpuid_ecx(unsigned int op) |
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200 | { |
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201 | unsigned int eax, ecx; |
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202 | |
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203 | __asm__(XEN_CPUID |
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204 | : "=a" (eax), "=c" (ecx) |
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205 | : "0" (op) |
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206 | : "bx", "dx" ); |
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207 | return ecx; |
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208 | } |
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209 | static inline unsigned int cpuid_edx(unsigned int op) |
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210 | { |
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211 | unsigned int eax, edx; |
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212 | |
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213 | __asm__(XEN_CPUID |
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214 | : "=a" (eax), "=d" (edx) |
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215 | : "0" (op) |
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216 | : "bx", "cx"); |
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217 | return edx; |
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218 | } |
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219 | |
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220 | #define load_cr3(pgdir) write_cr3(__pa(pgdir)) |
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221 | |
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222 | /* |
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223 | * Intel CPU features in CR4 |
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224 | */ |
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225 | #define X86_CR4_VME 0x0001 /* enable vm86 extensions */ |
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226 | #define X86_CR4_PVI 0x0002 /* virtual interrupts flag enable */ |
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227 | #define X86_CR4_TSD 0x0004 /* disable time stamp at ipl 3 */ |
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228 | #define X86_CR4_DE 0x0008 /* enable debugging extensions */ |
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229 | #define X86_CR4_PSE 0x0010 /* enable page size extensions */ |
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230 | #define X86_CR4_PAE 0x0020 /* enable physical address extensions */ |
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231 | #define X86_CR4_MCE 0x0040 /* Machine check enable */ |
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232 | #define X86_CR4_PGE 0x0080 /* enable global pages */ |
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233 | #define X86_CR4_PCE 0x0100 /* enable performance counters at ipl 3 */ |
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234 | #define X86_CR4_OSFXSR 0x0200 /* enable fast FPU save and restore */ |
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235 | #define X86_CR4_OSXMMEXCPT 0x0400 /* enable unmasked SSE exceptions */ |
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236 | |
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237 | /* |
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238 | * Save the cr4 feature set we're using (ie |
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239 | * Pentium 4MB enable and PPro Global page |
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240 | * enable), so that any CPU's that boot up |
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241 | * after us can get the correct flags. |
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242 | */ |
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243 | extern unsigned long mmu_cr4_features; |
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244 | |
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245 | static inline void set_in_cr4 (unsigned long mask) |
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246 | { |
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247 | unsigned cr4; |
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248 | mmu_cr4_features |= mask; |
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249 | cr4 = read_cr4(); |
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250 | cr4 |= mask; |
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251 | write_cr4(cr4); |
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252 | } |
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253 | |
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254 | static inline void clear_in_cr4 (unsigned long mask) |
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255 | { |
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256 | unsigned cr4; |
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257 | mmu_cr4_features &= ~mask; |
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258 | cr4 = read_cr4(); |
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259 | cr4 &= ~mask; |
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260 | write_cr4(cr4); |
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261 | } |
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262 | |
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263 | /* |
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264 | * NSC/Cyrix CPU configuration register indexes |
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265 | */ |
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266 | |
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267 | #define CX86_PCR0 0x20 |
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268 | #define CX86_GCR 0xb8 |
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269 | #define CX86_CCR0 0xc0 |
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270 | #define CX86_CCR1 0xc1 |
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271 | #define CX86_CCR2 0xc2 |
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272 | #define CX86_CCR3 0xc3 |
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273 | #define CX86_CCR4 0xe8 |
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274 | #define CX86_CCR5 0xe9 |
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275 | #define CX86_CCR6 0xea |
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276 | #define CX86_CCR7 0xeb |
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277 | #define CX86_PCR1 0xf0 |
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278 | #define CX86_DIR0 0xfe |
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279 | #define CX86_DIR1 0xff |
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280 | #define CX86_ARR_BASE 0xc4 |
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281 | #define CX86_RCR_BASE 0xdc |
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282 | |
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283 | /* |
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284 | * NSC/Cyrix CPU indexed register access macros |
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285 | */ |
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286 | |
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287 | #define getCx86(reg) ({ outb((reg), 0x22); inb(0x23); }) |
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288 | |
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289 | #define setCx86(reg, data) do { \ |
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290 | outb((reg), 0x22); \ |
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291 | outb((data), 0x23); \ |
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292 | } while (0) |
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293 | |
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294 | /* Stop speculative execution */ |
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295 | static inline void sync_core(void) |
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296 | { |
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297 | int tmp; |
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298 | asm volatile("cpuid" : "=a" (tmp) : "0" (1) : "ebx","ecx","edx","memory"); |
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299 | } |
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300 | |
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301 | static inline void __monitor(const void *eax, unsigned long ecx, |
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302 | unsigned long edx) |
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303 | { |
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304 | /* "monitor %eax,%ecx,%edx;" */ |
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305 | asm volatile( |
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306 | ".byte 0x0f,0x01,0xc8;" |
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307 | : :"a" (eax), "c" (ecx), "d"(edx)); |
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308 | } |
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309 | |
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310 | static inline void __mwait(unsigned long eax, unsigned long ecx) |
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311 | { |
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312 | /* "mwait %eax,%ecx;" */ |
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313 | asm volatile( |
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314 | ".byte 0x0f,0x01,0xc9;" |
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315 | : :"a" (eax), "c" (ecx)); |
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316 | } |
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317 | |
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318 | /* from system description table in BIOS. Mostly for MCA use, but |
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319 | others may find it useful. */ |
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320 | extern unsigned int machine_id; |
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321 | extern unsigned int machine_submodel_id; |
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322 | extern unsigned int BIOS_revision; |
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323 | extern unsigned int mca_pentium_flag; |
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324 | |
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325 | /* Boot loader type from the setup header */ |
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326 | extern int bootloader_type; |
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327 | |
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328 | /* |
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329 | * User space process size: 3GB (default). |
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330 | */ |
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331 | #define TASK_SIZE (PAGE_OFFSET) |
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332 | |
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333 | /* This decides where the kernel will search for a free chunk of vm |
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334 | * space during mmap's. |
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335 | */ |
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336 | #define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 3)) |
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337 | |
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338 | #define HAVE_ARCH_PICK_MMAP_LAYOUT |
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339 | |
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340 | /* |
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341 | * Size of io_bitmap. |
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342 | */ |
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343 | #define IO_BITMAP_BITS 65536 |
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344 | #define IO_BITMAP_BYTES (IO_BITMAP_BITS/8) |
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345 | #define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long)) |
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346 | #ifndef CONFIG_X86_NO_TSS |
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347 | #define IO_BITMAP_OFFSET offsetof(struct tss_struct,io_bitmap) |
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348 | #endif |
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349 | #define INVALID_IO_BITMAP_OFFSET 0x8000 |
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350 | #define INVALID_IO_BITMAP_OFFSET_LAZY 0x9000 |
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351 | |
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352 | struct i387_fsave_struct { |
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353 | long cwd; |
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354 | long swd; |
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355 | long twd; |
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356 | long fip; |
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357 | long fcs; |
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358 | long foo; |
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359 | long fos; |
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360 | long st_space[20]; /* 8*10 bytes for each FP-reg = 80 bytes */ |
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361 | long status; /* software status information */ |
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362 | }; |
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363 | |
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364 | struct i387_fxsave_struct { |
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365 | unsigned short cwd; |
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366 | unsigned short swd; |
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367 | unsigned short twd; |
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368 | unsigned short fop; |
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369 | long fip; |
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370 | long fcs; |
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371 | long foo; |
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372 | long fos; |
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373 | long mxcsr; |
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374 | long mxcsr_mask; |
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375 | long st_space[32]; /* 8*16 bytes for each FP-reg = 128 bytes */ |
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376 | long xmm_space[32]; /* 8*16 bytes for each XMM-reg = 128 bytes */ |
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377 | long padding[56]; |
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378 | } __attribute__ ((aligned (16))); |
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379 | |
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380 | struct i387_soft_struct { |
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381 | long cwd; |
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382 | long swd; |
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383 | long twd; |
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384 | long fip; |
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385 | long fcs; |
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386 | long foo; |
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387 | long fos; |
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388 | long st_space[20]; /* 8*10 bytes for each FP-reg = 80 bytes */ |
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389 | unsigned char ftop, changed, lookahead, no_update, rm, alimit; |
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390 | struct info *info; |
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391 | unsigned long entry_eip; |
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392 | }; |
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393 | |
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394 | union i387_union { |
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395 | struct i387_fsave_struct fsave; |
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396 | struct i387_fxsave_struct fxsave; |
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397 | struct i387_soft_struct soft; |
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398 | }; |
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399 | |
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400 | typedef struct { |
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401 | unsigned long seg; |
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402 | } mm_segment_t; |
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403 | |
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404 | struct thread_struct; |
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405 | |
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406 | #ifndef CONFIG_X86_NO_TSS |
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407 | struct tss_struct { |
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408 | unsigned short back_link,__blh; |
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409 | unsigned long esp0; |
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410 | unsigned short ss0,__ss0h; |
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411 | unsigned long esp1; |
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412 | unsigned short ss1,__ss1h; /* ss1 is used to cache MSR_IA32_SYSENTER_CS */ |
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413 | unsigned long esp2; |
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414 | unsigned short ss2,__ss2h; |
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415 | unsigned long __cr3; |
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416 | unsigned long eip; |
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417 | unsigned long eflags; |
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418 | unsigned long eax,ecx,edx,ebx; |
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419 | unsigned long esp; |
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420 | unsigned long ebp; |
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421 | unsigned long esi; |
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422 | unsigned long edi; |
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423 | unsigned short es, __esh; |
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424 | unsigned short cs, __csh; |
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425 | unsigned short ss, __ssh; |
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426 | unsigned short ds, __dsh; |
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427 | unsigned short fs, __fsh; |
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428 | unsigned short gs, __gsh; |
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429 | unsigned short ldt, __ldth; |
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430 | unsigned short trace, io_bitmap_base; |
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431 | /* |
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432 | * The extra 1 is there because the CPU will access an |
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433 | * additional byte beyond the end of the IO permission |
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434 | * bitmap. The extra byte must be all 1 bits, and must |
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435 | * be within the limit. |
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436 | */ |
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437 | unsigned long io_bitmap[IO_BITMAP_LONGS + 1]; |
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438 | /* |
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439 | * Cache the current maximum and the last task that used the bitmap: |
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440 | */ |
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441 | unsigned long io_bitmap_max; |
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442 | struct thread_struct *io_bitmap_owner; |
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443 | /* |
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444 | * pads the TSS to be cacheline-aligned (size is 0x100) |
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445 | */ |
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446 | unsigned long __cacheline_filler[35]; |
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447 | /* |
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448 | * .. and then another 0x100 bytes for emergency kernel stack |
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449 | */ |
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450 | unsigned long stack[64]; |
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451 | } __attribute__((packed)); |
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452 | #endif |
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453 | |
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454 | #define ARCH_MIN_TASKALIGN 16 |
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455 | |
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456 | struct thread_struct { |
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457 | /* cached TLS descriptors. */ |
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458 | struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES]; |
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459 | unsigned long esp0; |
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460 | unsigned long sysenter_cs; |
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461 | unsigned long eip; |
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462 | unsigned long esp; |
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463 | unsigned long fs; |
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464 | unsigned long gs; |
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465 | /* Hardware debugging registers */ |
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466 | unsigned long debugreg[8]; /* %%db0-7 debug registers */ |
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467 | /* fault info */ |
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468 | unsigned long cr2, trap_no, error_code; |
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469 | /* floating point info */ |
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470 | union i387_union i387; |
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471 | /* virtual 86 mode info */ |
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472 | struct vm86_struct __user * vm86_info; |
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473 | unsigned long screen_bitmap; |
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474 | unsigned long v86flags, v86mask, saved_esp0; |
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475 | unsigned int saved_fs, saved_gs; |
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476 | /* IO permissions */ |
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477 | unsigned long *io_bitmap_ptr; |
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478 | unsigned long iopl; |
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479 | /* max allowed port in the bitmap, in bytes: */ |
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480 | unsigned long io_bitmap_max; |
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481 | }; |
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482 | |
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483 | #define INIT_THREAD { \ |
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484 | .vm86_info = NULL, \ |
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485 | .sysenter_cs = __KERNEL_CS, \ |
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486 | .io_bitmap_ptr = NULL, \ |
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487 | } |
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488 | |
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489 | #ifndef CONFIG_X86_NO_TSS |
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490 | /* |
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491 | * Note that the .io_bitmap member must be extra-big. This is because |
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492 | * the CPU will access an additional byte beyond the end of the IO |
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493 | * permission bitmap. The extra byte must be all 1 bits, and must |
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494 | * be within the limit. |
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495 | */ |
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496 | #define INIT_TSS { \ |
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497 | .esp0 = sizeof(init_stack) + (long)&init_stack, \ |
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498 | .ss0 = __KERNEL_DS, \ |
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499 | .ss1 = __KERNEL_CS, \ |
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500 | .io_bitmap_base = INVALID_IO_BITMAP_OFFSET, \ |
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501 | .io_bitmap = { [ 0 ... IO_BITMAP_LONGS] = ~0 }, \ |
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502 | } |
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503 | |
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504 | static inline void __load_esp0(struct tss_struct *tss, struct thread_struct *thread) |
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505 | { |
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506 | tss->esp0 = thread->esp0; |
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507 | /* This can only happen when SEP is enabled, no need to test "SEP"arately */ |
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508 | if (unlikely(tss->ss1 != thread->sysenter_cs)) { |
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509 | tss->ss1 = thread->sysenter_cs; |
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510 | wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0); |
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511 | } |
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512 | } |
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513 | #define load_esp0(tss, thread) \ |
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514 | __load_esp0(tss, thread) |
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515 | #else |
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516 | #define load_esp0(tss, thread) \ |
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517 | HYPERVISOR_stack_switch(__KERNEL_DS, (thread)->esp0) |
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518 | #endif |
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519 | |
---|
520 | #define start_thread(regs, new_eip, new_esp) do { \ |
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521 | __asm__("movl %0,%%fs ; movl %0,%%gs": :"r" (0)); \ |
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522 | set_fs(USER_DS); \ |
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523 | regs->xds = __USER_DS; \ |
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524 | regs->xes = __USER_DS; \ |
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525 | regs->xss = __USER_DS; \ |
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526 | regs->xcs = __USER_CS; \ |
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527 | regs->eip = new_eip; \ |
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528 | regs->esp = new_esp; \ |
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529 | } while (0) |
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530 | |
---|
531 | /* |
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532 | * These special macros can be used to get or set a debugging register |
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533 | */ |
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534 | #define get_debugreg(var, register) \ |
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535 | (var) = HYPERVISOR_get_debugreg((register)) |
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536 | #define set_debugreg(value, register) \ |
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537 | HYPERVISOR_set_debugreg((register), (value)) |
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538 | |
---|
539 | /* |
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540 | * Set IOPL bits in EFLAGS from given mask |
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541 | */ |
---|
542 | static inline void set_iopl_mask(unsigned mask) |
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543 | { |
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544 | struct physdev_set_iopl set_iopl; |
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545 | |
---|
546 | /* Force the change at ring 0. */ |
---|
547 | set_iopl.iopl = (mask == 0) ? 1 : (mask >> 12) & 3; |
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548 | HYPERVISOR_physdev_op(PHYSDEVOP_set_iopl, &set_iopl); |
---|
549 | } |
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550 | |
---|
551 | /* Forward declaration, a strange C thing */ |
---|
552 | struct task_struct; |
---|
553 | struct mm_struct; |
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554 | |
---|
555 | /* Free all resources held by a thread. */ |
---|
556 | extern void release_thread(struct task_struct *); |
---|
557 | |
---|
558 | /* Prepare to copy thread state - unlazy all lazy status */ |
---|
559 | extern void prepare_to_copy(struct task_struct *tsk); |
---|
560 | |
---|
561 | /* |
---|
562 | * create a kernel thread without removing it from tasklists |
---|
563 | */ |
---|
564 | extern int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags); |
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565 | |
---|
566 | extern unsigned long thread_saved_pc(struct task_struct *tsk); |
---|
567 | void show_trace(struct task_struct *task, struct pt_regs *regs, unsigned long *stack); |
---|
568 | |
---|
569 | unsigned long get_wchan(struct task_struct *p); |
---|
570 | |
---|
571 | #define THREAD_SIZE_LONGS (THREAD_SIZE/sizeof(unsigned long)) |
---|
572 | #define KSTK_TOP(info) \ |
---|
573 | ({ \ |
---|
574 | unsigned long *__ptr = (unsigned long *)(info); \ |
---|
575 | (unsigned long)(&__ptr[THREAD_SIZE_LONGS]); \ |
---|
576 | }) |
---|
577 | |
---|
578 | /* |
---|
579 | * The below -8 is to reserve 8 bytes on top of the ring0 stack. |
---|
580 | * This is necessary to guarantee that the entire "struct pt_regs" |
---|
581 | * is accessable even if the CPU haven't stored the SS/ESP registers |
---|
582 | * on the stack (interrupt gate does not save these registers |
---|
583 | * when switching to the same priv ring). |
---|
584 | * Therefore beware: accessing the xss/esp fields of the |
---|
585 | * "struct pt_regs" is possible, but they may contain the |
---|
586 | * completely wrong values. |
---|
587 | */ |
---|
588 | #define task_pt_regs(task) \ |
---|
589 | ({ \ |
---|
590 | struct pt_regs *__regs__; \ |
---|
591 | __regs__ = (struct pt_regs *)(KSTK_TOP(task_stack_page(task))-8); \ |
---|
592 | __regs__ - 1; \ |
---|
593 | }) |
---|
594 | |
---|
595 | #define KSTK_EIP(task) (task_pt_regs(task)->eip) |
---|
596 | #define KSTK_ESP(task) (task_pt_regs(task)->esp) |
---|
597 | |
---|
598 | |
---|
599 | struct microcode_header { |
---|
600 | unsigned int hdrver; |
---|
601 | unsigned int rev; |
---|
602 | unsigned int date; |
---|
603 | unsigned int sig; |
---|
604 | unsigned int cksum; |
---|
605 | unsigned int ldrver; |
---|
606 | unsigned int pf; |
---|
607 | unsigned int datasize; |
---|
608 | unsigned int totalsize; |
---|
609 | unsigned int reserved[3]; |
---|
610 | }; |
---|
611 | |
---|
612 | struct microcode { |
---|
613 | struct microcode_header hdr; |
---|
614 | unsigned int bits[0]; |
---|
615 | }; |
---|
616 | |
---|
617 | typedef struct microcode microcode_t; |
---|
618 | typedef struct microcode_header microcode_header_t; |
---|
619 | |
---|
620 | /* microcode format is extended from prescott processors */ |
---|
621 | struct extended_signature { |
---|
622 | unsigned int sig; |
---|
623 | unsigned int pf; |
---|
624 | unsigned int cksum; |
---|
625 | }; |
---|
626 | |
---|
627 | struct extended_sigtable { |
---|
628 | unsigned int count; |
---|
629 | unsigned int cksum; |
---|
630 | unsigned int reserved[3]; |
---|
631 | struct extended_signature sigs[0]; |
---|
632 | }; |
---|
633 | |
---|
634 | /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */ |
---|
635 | static inline void rep_nop(void) |
---|
636 | { |
---|
637 | __asm__ __volatile__("rep;nop": : :"memory"); |
---|
638 | } |
---|
639 | |
---|
640 | #define cpu_relax() rep_nop() |
---|
641 | |
---|
642 | /* generic versions from gas */ |
---|
643 | #define GENERIC_NOP1 ".byte 0x90\n" |
---|
644 | #define GENERIC_NOP2 ".byte 0x89,0xf6\n" |
---|
645 | #define GENERIC_NOP3 ".byte 0x8d,0x76,0x00\n" |
---|
646 | #define GENERIC_NOP4 ".byte 0x8d,0x74,0x26,0x00\n" |
---|
647 | #define GENERIC_NOP5 GENERIC_NOP1 GENERIC_NOP4 |
---|
648 | #define GENERIC_NOP6 ".byte 0x8d,0xb6,0x00,0x00,0x00,0x00\n" |
---|
649 | #define GENERIC_NOP7 ".byte 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00\n" |
---|
650 | #define GENERIC_NOP8 GENERIC_NOP1 GENERIC_NOP7 |
---|
651 | |
---|
652 | /* Opteron nops */ |
---|
653 | #define K8_NOP1 GENERIC_NOP1 |
---|
654 | #define K8_NOP2 ".byte 0x66,0x90\n" |
---|
655 | #define K8_NOP3 ".byte 0x66,0x66,0x90\n" |
---|
656 | #define K8_NOP4 ".byte 0x66,0x66,0x66,0x90\n" |
---|
657 | #define K8_NOP5 K8_NOP3 K8_NOP2 |
---|
658 | #define K8_NOP6 K8_NOP3 K8_NOP3 |
---|
659 | #define K8_NOP7 K8_NOP4 K8_NOP3 |
---|
660 | #define K8_NOP8 K8_NOP4 K8_NOP4 |
---|
661 | |
---|
662 | /* K7 nops */ |
---|
663 | /* uses eax dependencies (arbitary choice) */ |
---|
664 | #define K7_NOP1 GENERIC_NOP1 |
---|
665 | #define K7_NOP2 ".byte 0x8b,0xc0\n" |
---|
666 | #define K7_NOP3 ".byte 0x8d,0x04,0x20\n" |
---|
667 | #define K7_NOP4 ".byte 0x8d,0x44,0x20,0x00\n" |
---|
668 | #define K7_NOP5 K7_NOP4 ASM_NOP1 |
---|
669 | #define K7_NOP6 ".byte 0x8d,0x80,0,0,0,0\n" |
---|
670 | #define K7_NOP7 ".byte 0x8D,0x04,0x05,0,0,0,0\n" |
---|
671 | #define K7_NOP8 K7_NOP7 ASM_NOP1 |
---|
672 | |
---|
673 | #ifdef CONFIG_MK8 |
---|
674 | #define ASM_NOP1 K8_NOP1 |
---|
675 | #define ASM_NOP2 K8_NOP2 |
---|
676 | #define ASM_NOP3 K8_NOP3 |
---|
677 | #define ASM_NOP4 K8_NOP4 |
---|
678 | #define ASM_NOP5 K8_NOP5 |
---|
679 | #define ASM_NOP6 K8_NOP6 |
---|
680 | #define ASM_NOP7 K8_NOP7 |
---|
681 | #define ASM_NOP8 K8_NOP8 |
---|
682 | #elif defined(CONFIG_MK7) |
---|
683 | #define ASM_NOP1 K7_NOP1 |
---|
684 | #define ASM_NOP2 K7_NOP2 |
---|
685 | #define ASM_NOP3 K7_NOP3 |
---|
686 | #define ASM_NOP4 K7_NOP4 |
---|
687 | #define ASM_NOP5 K7_NOP5 |
---|
688 | #define ASM_NOP6 K7_NOP6 |
---|
689 | #define ASM_NOP7 K7_NOP7 |
---|
690 | #define ASM_NOP8 K7_NOP8 |
---|
691 | #else |
---|
692 | #define ASM_NOP1 GENERIC_NOP1 |
---|
693 | #define ASM_NOP2 GENERIC_NOP2 |
---|
694 | #define ASM_NOP3 GENERIC_NOP3 |
---|
695 | #define ASM_NOP4 GENERIC_NOP4 |
---|
696 | #define ASM_NOP5 GENERIC_NOP5 |
---|
697 | #define ASM_NOP6 GENERIC_NOP6 |
---|
698 | #define ASM_NOP7 GENERIC_NOP7 |
---|
699 | #define ASM_NOP8 GENERIC_NOP8 |
---|
700 | #endif |
---|
701 | |
---|
702 | #define ASM_NOP_MAX 8 |
---|
703 | |
---|
704 | /* Prefetch instructions for Pentium III and AMD Athlon */ |
---|
705 | /* It's not worth to care about 3dnow! prefetches for the K6 |
---|
706 | because they are microcoded there and very slow. |
---|
707 | However we don't do prefetches for pre XP Athlons currently |
---|
708 | That should be fixed. */ |
---|
709 | #define ARCH_HAS_PREFETCH |
---|
710 | static inline void prefetch(const void *x) |
---|
711 | { |
---|
712 | alternative_input(ASM_NOP4, |
---|
713 | "prefetchnta (%1)", |
---|
714 | X86_FEATURE_XMM, |
---|
715 | "r" (x)); |
---|
716 | } |
---|
717 | |
---|
718 | #define ARCH_HAS_PREFETCH |
---|
719 | #define ARCH_HAS_PREFETCHW |
---|
720 | #define ARCH_HAS_SPINLOCK_PREFETCH |
---|
721 | |
---|
722 | /* 3dnow! prefetch to get an exclusive cache line. Useful for |
---|
723 | spinlocks to avoid one state transition in the cache coherency protocol. */ |
---|
724 | static inline void prefetchw(const void *x) |
---|
725 | { |
---|
726 | alternative_input(ASM_NOP4, |
---|
727 | "prefetchw (%1)", |
---|
728 | X86_FEATURE_3DNOW, |
---|
729 | "r" (x)); |
---|
730 | } |
---|
731 | #define spin_lock_prefetch(x) prefetchw(x) |
---|
732 | |
---|
733 | extern void select_idle_routine(const struct cpuinfo_x86 *c); |
---|
734 | |
---|
735 | #define cache_line_size() (boot_cpu_data.x86_cache_alignment) |
---|
736 | |
---|
737 | extern unsigned long boot_option_idle_override; |
---|
738 | extern void enable_sep_cpu(void); |
---|
739 | extern int sysenter_setup(void); |
---|
740 | |
---|
741 | #endif /* __ASM_I386_PROCESSOR_H */ |
---|