1 | #ifndef AGP_H |
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2 | #define AGP_H 1 |
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3 | |
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4 | #include <asm/pgtable.h> |
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5 | #include <asm/cacheflush.h> |
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6 | #include <asm/system.h> |
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7 | |
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8 | /* |
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9 | * Functions to keep the agpgart mappings coherent with the MMU. |
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10 | * The GART gives the CPU a physical alias of pages in memory. The alias region is |
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11 | * mapped uncacheable. Make sure there are no conflicting mappings |
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12 | * with different cachability attributes for the same page. This avoids |
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13 | * data corruption on some CPUs. |
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14 | */ |
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15 | |
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16 | int map_page_into_agp(struct page *page); |
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17 | int unmap_page_from_agp(struct page *page); |
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18 | #define flush_agp_mappings() global_flush_tlb() |
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19 | |
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20 | /* Could use CLFLUSH here if the cpu supports it. But then it would |
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21 | need to be called for each cacheline of the whole page so it may not be |
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22 | worth it. Would need a page for it. */ |
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23 | #define flush_agp_cache() wbinvd() |
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24 | |
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25 | /* Convert a physical address to an address suitable for the GART. */ |
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26 | #define phys_to_gart(x) phys_to_machine(x) |
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27 | #define gart_to_phys(x) machine_to_phys(x) |
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28 | |
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29 | /* GATT allocation. Returns/accepts GATT kernel virtual address. */ |
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30 | #define alloc_gatt_pages(order) ({ \ |
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31 | char *_t; dma_addr_t _d; \ |
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32 | _t = dma_alloc_coherent(NULL,PAGE_SIZE<<(order),&_d,GFP_KERNEL); \ |
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33 | _t; }) |
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34 | #define free_gatt_pages(table, order) \ |
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35 | dma_free_coherent(NULL,PAGE_SIZE<<(order),(table),virt_to_bus(table)) |
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36 | |
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37 | #endif |
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