1 | /* |
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2 | * Intel IO-APIC support for multi-Pentium hosts. |
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3 | * |
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4 | * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo |
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5 | * |
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6 | * Many thanks to Stig Venaas for trying out countless experimental |
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7 | * patches and reporting/debugging problems patiently! |
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8 | * |
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9 | * (c) 1999, Multiple IO-APIC support, developed by |
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10 | * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and |
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11 | * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>, |
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12 | * further tested and cleaned up by Zach Brown <zab@redhat.com> |
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13 | * and Ingo Molnar <mingo@redhat.com> |
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14 | * |
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15 | * Fixes |
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16 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs; |
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17 | * thanks to Eric Gilmore |
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18 | * and Rolf G. Tews |
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19 | * for testing these extensively |
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20 | * Paul Diefenbaugh : Added full ACPI support |
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21 | */ |
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22 | |
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23 | #include <linux/mm.h> |
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24 | #include <linux/interrupt.h> |
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25 | #include <linux/init.h> |
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26 | #include <linux/delay.h> |
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27 | #include <linux/sched.h> |
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28 | #include <linux/smp_lock.h> |
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29 | #include <linux/mc146818rtc.h> |
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30 | #include <linux/acpi.h> |
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31 | #include <linux/sysdev.h> |
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32 | #ifdef CONFIG_ACPI |
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33 | #include <acpi/acpi_bus.h> |
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34 | #endif |
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35 | |
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36 | #include <asm/io.h> |
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37 | #include <asm/smp.h> |
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38 | #include <asm/desc.h> |
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39 | #include <asm/proto.h> |
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40 | #include <asm/mach_apic.h> |
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41 | #include <asm/acpi.h> |
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42 | #include <asm/dma.h> |
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43 | #include <asm/nmi.h> |
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44 | |
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45 | #define __apicdebuginit __init |
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46 | |
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47 | int sis_apic_bug; /* not actually supported, dummy for compile */ |
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48 | |
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49 | static int no_timer_check; |
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50 | |
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51 | int disable_timer_pin_1 __initdata; |
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52 | |
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53 | #ifndef CONFIG_XEN |
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54 | int timer_over_8254 __initdata = 0; |
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55 | |
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56 | /* Where if anywhere is the i8259 connect in external int mode */ |
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57 | static struct { int pin, apic; } ioapic_i8259 = { -1, -1 }; |
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58 | #endif |
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59 | |
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60 | static DEFINE_SPINLOCK(ioapic_lock); |
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61 | static DEFINE_SPINLOCK(vector_lock); |
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62 | |
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63 | /* |
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64 | * # of IRQ routing registers |
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65 | */ |
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66 | int nr_ioapic_registers[MAX_IO_APICS]; |
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67 | |
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68 | /* |
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69 | * Rough estimation of how many shared IRQs there are, can |
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70 | * be changed anytime. |
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71 | */ |
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72 | #define MAX_PLUS_SHARED_IRQS NR_IRQ_VECTORS |
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73 | #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS) |
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74 | |
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75 | /* |
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76 | * This is performance-critical, we want to do it O(1) |
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77 | * |
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78 | * the indexing order of this array favors 1:1 mappings |
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79 | * between pins and IRQs. |
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80 | */ |
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81 | |
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82 | static struct irq_pin_list { |
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83 | short apic, pin, next; |
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84 | } irq_2_pin[PIN_MAP_SIZE]; |
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85 | |
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86 | int vector_irq[NR_VECTORS] __read_mostly = { [0 ... NR_VECTORS - 1] = -1}; |
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87 | #ifdef CONFIG_PCI_MSI |
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88 | #define vector_to_irq(vector) \ |
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89 | (platform_legacy_irq(vector) ? vector : vector_irq[vector]) |
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90 | #else |
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91 | #define vector_to_irq(vector) (vector) |
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92 | #endif |
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93 | |
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94 | #ifdef CONFIG_XEN |
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95 | |
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96 | #include <xen/interface/xen.h> |
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97 | #include <xen/interface/physdev.h> |
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98 | |
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99 | /* Fake i8259 */ |
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100 | #define make_8259A_irq(_irq) (io_apic_irqs &= ~(1UL<<(_irq))) |
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101 | #define disable_8259A_irq(_irq) ((void)0) |
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102 | #define i8259A_irq_pending(_irq) (0) |
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103 | |
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104 | unsigned long io_apic_irqs; |
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105 | |
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106 | static inline unsigned int xen_io_apic_read(unsigned int apic, unsigned int reg) |
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107 | { |
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108 | struct physdev_apic apic_op; |
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109 | int ret; |
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110 | |
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111 | apic_op.apic_physbase = mp_ioapics[apic].mpc_apicaddr; |
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112 | apic_op.reg = reg; |
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113 | ret = HYPERVISOR_physdev_op(PHYSDEVOP_apic_read, &apic_op); |
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114 | if (ret) |
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115 | return ret; |
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116 | return apic_op.value; |
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117 | } |
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118 | |
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119 | static inline void xen_io_apic_write(unsigned int apic, unsigned int reg, unsigned int value) |
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120 | { |
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121 | struct physdev_apic apic_op; |
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122 | |
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123 | apic_op.apic_physbase = mp_ioapics[apic].mpc_apicaddr; |
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124 | apic_op.reg = reg; |
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125 | apic_op.value = value; |
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126 | HYPERVISOR_physdev_op(PHYSDEVOP_apic_write, &apic_op); |
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127 | } |
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128 | |
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129 | #define io_apic_read(a,r) xen_io_apic_read(a,r) |
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130 | #define io_apic_write(a,r,v) xen_io_apic_write(a,r,v) |
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131 | |
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132 | #define clear_IO_APIC() ((void)0) |
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133 | |
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134 | #else |
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135 | |
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136 | #ifdef CONFIG_SMP |
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137 | static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t mask) |
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138 | { |
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139 | unsigned long flags; |
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140 | unsigned int dest; |
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141 | cpumask_t tmp; |
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142 | |
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143 | cpus_and(tmp, mask, cpu_online_map); |
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144 | if (cpus_empty(tmp)) |
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145 | tmp = TARGET_CPUS; |
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146 | |
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147 | cpus_and(mask, tmp, CPU_MASK_ALL); |
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148 | |
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149 | dest = cpu_mask_to_apicid(mask); |
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150 | |
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151 | /* |
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152 | * Only the high 8 bits are valid. |
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153 | */ |
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154 | dest = SET_APIC_LOGICAL_ID(dest); |
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155 | |
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156 | spin_lock_irqsave(&ioapic_lock, flags); |
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157 | __DO_ACTION(1, = dest, ) |
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158 | set_irq_info(irq, mask); |
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159 | spin_unlock_irqrestore(&ioapic_lock, flags); |
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160 | } |
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161 | #endif |
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162 | |
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163 | #endif /* !CONFIG_XEN */ |
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164 | |
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165 | /* |
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166 | * The common case is 1:1 IRQ<->pin mappings. Sometimes there are |
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167 | * shared ISA-space IRQs, so we have to support them. We are super |
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168 | * fast in the common case, and fast for shared ISA-space IRQs. |
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169 | */ |
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170 | static void add_pin_to_irq(unsigned int irq, int apic, int pin) |
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171 | { |
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172 | static int first_free_entry = NR_IRQS; |
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173 | struct irq_pin_list *entry = irq_2_pin + irq; |
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174 | |
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175 | BUG_ON(irq >= NR_IRQS); |
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176 | while (entry->next) |
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177 | entry = irq_2_pin + entry->next; |
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178 | |
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179 | if (entry->pin != -1) { |
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180 | entry->next = first_free_entry; |
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181 | entry = irq_2_pin + entry->next; |
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182 | if (++first_free_entry >= PIN_MAP_SIZE) |
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183 | panic("io_apic.c: ran out of irq_2_pin entries!"); |
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184 | } |
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185 | entry->apic = apic; |
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186 | entry->pin = pin; |
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187 | } |
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188 | |
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189 | #ifndef CONFIG_XEN |
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190 | #define __DO_ACTION(R, ACTION, FINAL) \ |
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191 | \ |
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192 | { \ |
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193 | int pin; \ |
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194 | struct irq_pin_list *entry = irq_2_pin + irq; \ |
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195 | \ |
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196 | BUG_ON(irq >= NR_IRQS); \ |
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197 | for (;;) { \ |
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198 | unsigned int reg; \ |
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199 | pin = entry->pin; \ |
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200 | if (pin == -1) \ |
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201 | break; \ |
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202 | reg = io_apic_read(entry->apic, 0x10 + R + pin*2); \ |
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203 | reg ACTION; \ |
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204 | io_apic_modify(entry->apic, reg); \ |
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205 | if (!entry->next) \ |
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206 | break; \ |
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207 | entry = irq_2_pin + entry->next; \ |
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208 | } \ |
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209 | FINAL; \ |
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210 | } |
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211 | |
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212 | #define DO_ACTION(name,R,ACTION, FINAL) \ |
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213 | \ |
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214 | static void name##_IO_APIC_irq (unsigned int irq) \ |
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215 | __DO_ACTION(R, ACTION, FINAL) |
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216 | |
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217 | DO_ACTION( __mask, 0, |= 0x00010000, io_apic_sync(entry->apic) ) |
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218 | /* mask = 1 */ |
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219 | DO_ACTION( __unmask, 0, &= 0xfffeffff, ) |
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220 | /* mask = 0 */ |
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221 | |
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222 | static void mask_IO_APIC_irq (unsigned int irq) |
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223 | { |
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224 | unsigned long flags; |
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225 | |
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226 | spin_lock_irqsave(&ioapic_lock, flags); |
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227 | __mask_IO_APIC_irq(irq); |
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228 | spin_unlock_irqrestore(&ioapic_lock, flags); |
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229 | } |
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230 | |
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231 | static void unmask_IO_APIC_irq (unsigned int irq) |
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232 | { |
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233 | unsigned long flags; |
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234 | |
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235 | spin_lock_irqsave(&ioapic_lock, flags); |
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236 | __unmask_IO_APIC_irq(irq); |
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237 | spin_unlock_irqrestore(&ioapic_lock, flags); |
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238 | } |
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239 | |
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240 | static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin) |
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241 | { |
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242 | struct IO_APIC_route_entry entry; |
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243 | unsigned long flags; |
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244 | |
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245 | /* Check delivery_mode to be sure we're not clearing an SMI pin */ |
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246 | spin_lock_irqsave(&ioapic_lock, flags); |
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247 | *(((int*)&entry) + 0) = io_apic_read(apic, 0x10 + 2 * pin); |
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248 | *(((int*)&entry) + 1) = io_apic_read(apic, 0x11 + 2 * pin); |
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249 | spin_unlock_irqrestore(&ioapic_lock, flags); |
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250 | if (entry.delivery_mode == dest_SMI) |
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251 | return; |
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252 | /* |
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253 | * Disable it in the IO-APIC irq-routing table: |
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254 | */ |
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255 | memset(&entry, 0, sizeof(entry)); |
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256 | entry.mask = 1; |
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257 | spin_lock_irqsave(&ioapic_lock, flags); |
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258 | io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry) + 0)); |
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259 | io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry) + 1)); |
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260 | spin_unlock_irqrestore(&ioapic_lock, flags); |
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261 | } |
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262 | |
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263 | static void clear_IO_APIC (void) |
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264 | { |
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265 | int apic, pin; |
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266 | |
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267 | for (apic = 0; apic < nr_ioapics; apic++) |
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268 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) |
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269 | clear_IO_APIC_pin(apic, pin); |
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270 | } |
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271 | |
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272 | #endif /* !CONFIG_XEN */ |
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273 | |
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274 | static u8 gsi_2_irq[NR_IRQ_VECTORS] = { [0 ... NR_IRQ_VECTORS-1] = 0xFF }; |
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275 | |
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276 | /* |
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277 | * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to |
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278 | * specific CPU-side IRQs. |
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279 | */ |
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280 | |
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281 | #define MAX_PIRQS 8 |
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282 | static int pirq_entries [MAX_PIRQS]; |
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283 | static int pirqs_enabled; |
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284 | int skip_ioapic_setup; |
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285 | int ioapic_force; |
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286 | |
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287 | /* dummy parsing: see setup.c */ |
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288 | |
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289 | static int __init disable_ioapic_setup(char *str) |
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290 | { |
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291 | skip_ioapic_setup = 1; |
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292 | return 1; |
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293 | } |
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294 | |
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295 | static int __init enable_ioapic_setup(char *str) |
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296 | { |
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297 | ioapic_force = 1; |
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298 | skip_ioapic_setup = 0; |
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299 | return 1; |
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300 | } |
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301 | |
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302 | __setup("noapic", disable_ioapic_setup); |
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303 | __setup("apic", enable_ioapic_setup); |
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304 | |
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305 | #ifndef CONFIG_XEN |
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306 | static int __init setup_disable_8254_timer(char *s) |
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307 | { |
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308 | timer_over_8254 = -1; |
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309 | return 1; |
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310 | } |
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311 | static int __init setup_enable_8254_timer(char *s) |
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312 | { |
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313 | timer_over_8254 = 2; |
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314 | return 1; |
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315 | } |
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316 | |
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317 | __setup("disable_8254_timer", setup_disable_8254_timer); |
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318 | __setup("enable_8254_timer", setup_enable_8254_timer); |
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319 | #endif /* !CONFIG_XEN */ |
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320 | |
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321 | #include <asm/pci-direct.h> |
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322 | #include <linux/pci_ids.h> |
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323 | #include <linux/pci.h> |
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324 | |
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325 | |
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326 | #ifdef CONFIG_ACPI |
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327 | |
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328 | static int nvidia_hpet_detected __initdata; |
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329 | |
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330 | static int __init nvidia_hpet_check(unsigned long phys, unsigned long size) |
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331 | { |
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332 | nvidia_hpet_detected = 1; |
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333 | return 0; |
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334 | } |
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335 | #endif |
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336 | |
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337 | /* Temporary Hack. Nvidia and VIA boards currently only work with IO-APIC |
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338 | off. Check for an Nvidia or VIA PCI bridge and turn it off. |
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339 | Use pci direct infrastructure because this runs before the PCI subsystem. |
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340 | |
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341 | Can be overwritten with "apic" |
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342 | |
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343 | And another hack to disable the IOMMU on VIA chipsets. |
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344 | |
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345 | ... and others. Really should move this somewhere else. |
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346 | |
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347 | Kludge-O-Rama. */ |
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348 | void __init check_ioapic(void) |
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349 | { |
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350 | int num,slot,func; |
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351 | /* Poor man's PCI discovery */ |
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352 | for (num = 0; num < 32; num++) { |
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353 | for (slot = 0; slot < 32; slot++) { |
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354 | for (func = 0; func < 8; func++) { |
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355 | u32 class; |
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356 | u32 vendor; |
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357 | u8 type; |
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358 | class = read_pci_config(num,slot,func, |
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359 | PCI_CLASS_REVISION); |
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360 | if (class == 0xffffffff) |
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361 | break; |
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362 | |
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363 | if ((class >> 16) != PCI_CLASS_BRIDGE_PCI) |
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364 | continue; |
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365 | |
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366 | vendor = read_pci_config(num, slot, func, |
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367 | PCI_VENDOR_ID); |
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368 | vendor &= 0xffff; |
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369 | switch (vendor) { |
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370 | case PCI_VENDOR_ID_VIA: |
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371 | #ifdef CONFIG_IOMMU |
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372 | if ((end_pfn > MAX_DMA32_PFN || |
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373 | force_iommu) && |
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374 | !iommu_aperture_allowed) { |
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375 | printk(KERN_INFO |
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376 | "Looks like a VIA chipset. Disabling IOMMU. Override with \"iommu=allowed\"\n"); |
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377 | iommu_aperture_disabled = 1; |
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378 | } |
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379 | #endif |
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380 | return; |
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381 | case PCI_VENDOR_ID_NVIDIA: |
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382 | #ifdef CONFIG_ACPI |
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383 | /* |
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384 | * All timer overrides on Nvidia are |
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385 | * wrong unless HPET is enabled. |
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386 | */ |
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387 | nvidia_hpet_detected = 0; |
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388 | acpi_table_parse(ACPI_HPET, |
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389 | nvidia_hpet_check); |
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390 | if (nvidia_hpet_detected == 0) { |
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391 | acpi_skip_timer_override = 1; |
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392 | printk(KERN_INFO "Nvidia board " |
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393 | "detected. Ignoring ACPI " |
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394 | "timer override.\n"); |
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395 | } |
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396 | #endif |
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397 | /* RED-PEN skip them on mptables too? */ |
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398 | return; |
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399 | case PCI_VENDOR_ID_ATI: |
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400 | |
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401 | /* This should be actually default, but |
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402 | for 2.6.16 let's do it for ATI only where |
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403 | it's really needed. */ |
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404 | #ifndef CONFIG_XEN |
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405 | if (timer_over_8254 == 1) { |
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406 | timer_over_8254 = 0; |
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407 | printk(KERN_INFO |
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408 | "ATI board detected. Disabling timer routing over 8254.\n"); |
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409 | } |
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410 | #endif |
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411 | return; |
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412 | } |
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413 | |
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414 | |
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415 | /* No multi-function device? */ |
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416 | type = read_pci_config_byte(num,slot,func, |
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417 | PCI_HEADER_TYPE); |
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418 | if (!(type & 0x80)) |
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419 | break; |
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420 | } |
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421 | } |
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422 | } |
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423 | } |
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424 | |
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425 | static int __init ioapic_pirq_setup(char *str) |
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426 | { |
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427 | int i, max; |
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428 | int ints[MAX_PIRQS+1]; |
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429 | |
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430 | get_options(str, ARRAY_SIZE(ints), ints); |
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431 | |
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432 | for (i = 0; i < MAX_PIRQS; i++) |
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433 | pirq_entries[i] = -1; |
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434 | |
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435 | pirqs_enabled = 1; |
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436 | apic_printk(APIC_VERBOSE, "PIRQ redirection, working around broken MP-BIOS.\n"); |
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437 | max = MAX_PIRQS; |
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438 | if (ints[0] < MAX_PIRQS) |
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439 | max = ints[0]; |
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440 | |
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441 | for (i = 0; i < max; i++) { |
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442 | apic_printk(APIC_VERBOSE, "... PIRQ%d -> IRQ %d\n", i, ints[i+1]); |
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443 | /* |
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444 | * PIRQs are mapped upside down, usually. |
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445 | */ |
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446 | pirq_entries[MAX_PIRQS-i-1] = ints[i+1]; |
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447 | } |
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448 | return 1; |
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449 | } |
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450 | |
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451 | __setup("pirq=", ioapic_pirq_setup); |
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452 | |
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453 | /* |
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454 | * Find the IRQ entry number of a certain pin. |
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455 | */ |
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456 | static int find_irq_entry(int apic, int pin, int type) |
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457 | { |
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458 | int i; |
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459 | |
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460 | for (i = 0; i < mp_irq_entries; i++) |
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461 | if (mp_irqs[i].mpc_irqtype == type && |
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462 | (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid || |
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463 | mp_irqs[i].mpc_dstapic == MP_APIC_ALL) && |
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464 | mp_irqs[i].mpc_dstirq == pin) |
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465 | return i; |
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466 | |
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467 | return -1; |
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468 | } |
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469 | |
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470 | #ifndef CONFIG_XEN |
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471 | /* |
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472 | * Find the pin to which IRQ[irq] (ISA) is connected |
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473 | */ |
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474 | static int __init find_isa_irq_pin(int irq, int type) |
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475 | { |
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476 | int i; |
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477 | |
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478 | for (i = 0; i < mp_irq_entries; i++) { |
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479 | int lbus = mp_irqs[i].mpc_srcbus; |
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480 | |
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481 | if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA || |
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482 | mp_bus_id_to_type[lbus] == MP_BUS_EISA || |
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483 | mp_bus_id_to_type[lbus] == MP_BUS_MCA) && |
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484 | (mp_irqs[i].mpc_irqtype == type) && |
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485 | (mp_irqs[i].mpc_srcbusirq == irq)) |
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486 | |
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487 | return mp_irqs[i].mpc_dstirq; |
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488 | } |
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489 | return -1; |
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490 | } |
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491 | |
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492 | static int __init find_isa_irq_apic(int irq, int type) |
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493 | { |
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494 | int i; |
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495 | |
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496 | for (i = 0; i < mp_irq_entries; i++) { |
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497 | int lbus = mp_irqs[i].mpc_srcbus; |
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498 | |
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499 | if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA || |
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500 | mp_bus_id_to_type[lbus] == MP_BUS_EISA || |
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501 | mp_bus_id_to_type[lbus] == MP_BUS_MCA) && |
---|
502 | (mp_irqs[i].mpc_irqtype == type) && |
---|
503 | (mp_irqs[i].mpc_srcbusirq == irq)) |
---|
504 | break; |
---|
505 | } |
---|
506 | if (i < mp_irq_entries) { |
---|
507 | int apic; |
---|
508 | for(apic = 0; apic < nr_ioapics; apic++) { |
---|
509 | if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic) |
---|
510 | return apic; |
---|
511 | } |
---|
512 | } |
---|
513 | |
---|
514 | return -1; |
---|
515 | } |
---|
516 | #endif |
---|
517 | |
---|
518 | /* |
---|
519 | * Find a specific PCI IRQ entry. |
---|
520 | * Not an __init, possibly needed by modules |
---|
521 | */ |
---|
522 | static int pin_2_irq(int idx, int apic, int pin); |
---|
523 | |
---|
524 | int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin) |
---|
525 | { |
---|
526 | int apic, i, best_guess = -1; |
---|
527 | |
---|
528 | apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n", |
---|
529 | bus, slot, pin); |
---|
530 | if (mp_bus_id_to_pci_bus[bus] == -1) { |
---|
531 | apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus); |
---|
532 | return -1; |
---|
533 | } |
---|
534 | for (i = 0; i < mp_irq_entries; i++) { |
---|
535 | int lbus = mp_irqs[i].mpc_srcbus; |
---|
536 | |
---|
537 | for (apic = 0; apic < nr_ioapics; apic++) |
---|
538 | if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic || |
---|
539 | mp_irqs[i].mpc_dstapic == MP_APIC_ALL) |
---|
540 | break; |
---|
541 | |
---|
542 | if ((mp_bus_id_to_type[lbus] == MP_BUS_PCI) && |
---|
543 | !mp_irqs[i].mpc_irqtype && |
---|
544 | (bus == lbus) && |
---|
545 | (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) { |
---|
546 | int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq); |
---|
547 | |
---|
548 | if (!(apic || IO_APIC_IRQ(irq))) |
---|
549 | continue; |
---|
550 | |
---|
551 | if (pin == (mp_irqs[i].mpc_srcbusirq & 3)) |
---|
552 | return irq; |
---|
553 | /* |
---|
554 | * Use the first all-but-pin matching entry as a |
---|
555 | * best-guess fuzzy result for broken mptables. |
---|
556 | */ |
---|
557 | if (best_guess < 0) |
---|
558 | best_guess = irq; |
---|
559 | } |
---|
560 | } |
---|
561 | BUG_ON(best_guess >= NR_IRQS); |
---|
562 | return best_guess; |
---|
563 | } |
---|
564 | |
---|
565 | /* |
---|
566 | * EISA Edge/Level control register, ELCR |
---|
567 | */ |
---|
568 | static int EISA_ELCR(unsigned int irq) |
---|
569 | { |
---|
570 | if (irq < 16) { |
---|
571 | unsigned int port = 0x4d0 + (irq >> 3); |
---|
572 | return (inb(port) >> (irq & 7)) & 1; |
---|
573 | } |
---|
574 | apic_printk(APIC_VERBOSE, "Broken MPtable reports ISA irq %d\n", irq); |
---|
575 | return 0; |
---|
576 | } |
---|
577 | |
---|
578 | /* EISA interrupts are always polarity zero and can be edge or level |
---|
579 | * trigger depending on the ELCR value. If an interrupt is listed as |
---|
580 | * EISA conforming in the MP table, that means its trigger type must |
---|
581 | * be read in from the ELCR */ |
---|
582 | |
---|
583 | #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].mpc_srcbusirq)) |
---|
584 | #define default_EISA_polarity(idx) (0) |
---|
585 | |
---|
586 | /* ISA interrupts are always polarity zero edge triggered, |
---|
587 | * when listed as conforming in the MP table. */ |
---|
588 | |
---|
589 | #define default_ISA_trigger(idx) (0) |
---|
590 | #define default_ISA_polarity(idx) (0) |
---|
591 | |
---|
592 | /* PCI interrupts are always polarity one level triggered, |
---|
593 | * when listed as conforming in the MP table. */ |
---|
594 | |
---|
595 | #define default_PCI_trigger(idx) (1) |
---|
596 | #define default_PCI_polarity(idx) (1) |
---|
597 | |
---|
598 | /* MCA interrupts are always polarity zero level triggered, |
---|
599 | * when listed as conforming in the MP table. */ |
---|
600 | |
---|
601 | #define default_MCA_trigger(idx) (1) |
---|
602 | #define default_MCA_polarity(idx) (0) |
---|
603 | |
---|
604 | static int __init MPBIOS_polarity(int idx) |
---|
605 | { |
---|
606 | int bus = mp_irqs[idx].mpc_srcbus; |
---|
607 | int polarity; |
---|
608 | |
---|
609 | /* |
---|
610 | * Determine IRQ line polarity (high active or low active): |
---|
611 | */ |
---|
612 | switch (mp_irqs[idx].mpc_irqflag & 3) |
---|
613 | { |
---|
614 | case 0: /* conforms, ie. bus-type dependent polarity */ |
---|
615 | { |
---|
616 | switch (mp_bus_id_to_type[bus]) |
---|
617 | { |
---|
618 | case MP_BUS_ISA: /* ISA pin */ |
---|
619 | { |
---|
620 | polarity = default_ISA_polarity(idx); |
---|
621 | break; |
---|
622 | } |
---|
623 | case MP_BUS_EISA: /* EISA pin */ |
---|
624 | { |
---|
625 | polarity = default_EISA_polarity(idx); |
---|
626 | break; |
---|
627 | } |
---|
628 | case MP_BUS_PCI: /* PCI pin */ |
---|
629 | { |
---|
630 | polarity = default_PCI_polarity(idx); |
---|
631 | break; |
---|
632 | } |
---|
633 | case MP_BUS_MCA: /* MCA pin */ |
---|
634 | { |
---|
635 | polarity = default_MCA_polarity(idx); |
---|
636 | break; |
---|
637 | } |
---|
638 | default: |
---|
639 | { |
---|
640 | printk(KERN_WARNING "broken BIOS!!\n"); |
---|
641 | polarity = 1; |
---|
642 | break; |
---|
643 | } |
---|
644 | } |
---|
645 | break; |
---|
646 | } |
---|
647 | case 1: /* high active */ |
---|
648 | { |
---|
649 | polarity = 0; |
---|
650 | break; |
---|
651 | } |
---|
652 | case 2: /* reserved */ |
---|
653 | { |
---|
654 | printk(KERN_WARNING "broken BIOS!!\n"); |
---|
655 | polarity = 1; |
---|
656 | break; |
---|
657 | } |
---|
658 | case 3: /* low active */ |
---|
659 | { |
---|
660 | polarity = 1; |
---|
661 | break; |
---|
662 | } |
---|
663 | default: /* invalid */ |
---|
664 | { |
---|
665 | printk(KERN_WARNING "broken BIOS!!\n"); |
---|
666 | polarity = 1; |
---|
667 | break; |
---|
668 | } |
---|
669 | } |
---|
670 | return polarity; |
---|
671 | } |
---|
672 | |
---|
673 | static int MPBIOS_trigger(int idx) |
---|
674 | { |
---|
675 | int bus = mp_irqs[idx].mpc_srcbus; |
---|
676 | int trigger; |
---|
677 | |
---|
678 | /* |
---|
679 | * Determine IRQ trigger mode (edge or level sensitive): |
---|
680 | */ |
---|
681 | switch ((mp_irqs[idx].mpc_irqflag>>2) & 3) |
---|
682 | { |
---|
683 | case 0: /* conforms, ie. bus-type dependent */ |
---|
684 | { |
---|
685 | switch (mp_bus_id_to_type[bus]) |
---|
686 | { |
---|
687 | case MP_BUS_ISA: /* ISA pin */ |
---|
688 | { |
---|
689 | trigger = default_ISA_trigger(idx); |
---|
690 | break; |
---|
691 | } |
---|
692 | case MP_BUS_EISA: /* EISA pin */ |
---|
693 | { |
---|
694 | trigger = default_EISA_trigger(idx); |
---|
695 | break; |
---|
696 | } |
---|
697 | case MP_BUS_PCI: /* PCI pin */ |
---|
698 | { |
---|
699 | trigger = default_PCI_trigger(idx); |
---|
700 | break; |
---|
701 | } |
---|
702 | case MP_BUS_MCA: /* MCA pin */ |
---|
703 | { |
---|
704 | trigger = default_MCA_trigger(idx); |
---|
705 | break; |
---|
706 | } |
---|
707 | default: |
---|
708 | { |
---|
709 | printk(KERN_WARNING "broken BIOS!!\n"); |
---|
710 | trigger = 1; |
---|
711 | break; |
---|
712 | } |
---|
713 | } |
---|
714 | break; |
---|
715 | } |
---|
716 | case 1: /* edge */ |
---|
717 | { |
---|
718 | trigger = 0; |
---|
719 | break; |
---|
720 | } |
---|
721 | case 2: /* reserved */ |
---|
722 | { |
---|
723 | printk(KERN_WARNING "broken BIOS!!\n"); |
---|
724 | trigger = 1; |
---|
725 | break; |
---|
726 | } |
---|
727 | case 3: /* level */ |
---|
728 | { |
---|
729 | trigger = 1; |
---|
730 | break; |
---|
731 | } |
---|
732 | default: /* invalid */ |
---|
733 | { |
---|
734 | printk(KERN_WARNING "broken BIOS!!\n"); |
---|
735 | trigger = 0; |
---|
736 | break; |
---|
737 | } |
---|
738 | } |
---|
739 | return trigger; |
---|
740 | } |
---|
741 | |
---|
742 | static inline int irq_polarity(int idx) |
---|
743 | { |
---|
744 | return MPBIOS_polarity(idx); |
---|
745 | } |
---|
746 | |
---|
747 | static inline int irq_trigger(int idx) |
---|
748 | { |
---|
749 | return MPBIOS_trigger(idx); |
---|
750 | } |
---|
751 | |
---|
752 | static int next_irq = 16; |
---|
753 | |
---|
754 | /* |
---|
755 | * gsi_irq_sharing -- Name overload! "irq" can be either a legacy IRQ |
---|
756 | * in the range 0-15, a linux IRQ in the range 0-223, or a GSI number |
---|
757 | * from ACPI, which can reach 800 in large boxen. |
---|
758 | * |
---|
759 | * Compact the sparse GSI space into a sequential IRQ series and reuse |
---|
760 | * vectors if possible. |
---|
761 | */ |
---|
762 | int gsi_irq_sharing(int gsi) |
---|
763 | { |
---|
764 | int i, tries, vector; |
---|
765 | |
---|
766 | BUG_ON(gsi >= NR_IRQ_VECTORS); |
---|
767 | |
---|
768 | if (platform_legacy_irq(gsi)) |
---|
769 | return gsi; |
---|
770 | |
---|
771 | if (gsi_2_irq[gsi] != 0xFF) |
---|
772 | return (int)gsi_2_irq[gsi]; |
---|
773 | |
---|
774 | tries = NR_IRQS; |
---|
775 | try_again: |
---|
776 | vector = assign_irq_vector(gsi); |
---|
777 | |
---|
778 | /* |
---|
779 | * Sharing vectors means sharing IRQs, so scan irq_vectors for previous |
---|
780 | * use of vector and if found, return that IRQ. However, we never want |
---|
781 | * to share legacy IRQs, which usually have a different trigger mode |
---|
782 | * than PCI. |
---|
783 | */ |
---|
784 | for (i = 0; i < NR_IRQS; i++) |
---|
785 | if (IO_APIC_VECTOR(i) == vector) |
---|
786 | break; |
---|
787 | if (platform_legacy_irq(i)) { |
---|
788 | if (--tries >= 0) { |
---|
789 | IO_APIC_VECTOR(i) = 0; |
---|
790 | goto try_again; |
---|
791 | } |
---|
792 | panic("gsi_irq_sharing: didn't find an IRQ using vector 0x%02X for GSI %d", vector, gsi); |
---|
793 | } |
---|
794 | if (i < NR_IRQS) { |
---|
795 | gsi_2_irq[gsi] = i; |
---|
796 | printk(KERN_INFO "GSI %d sharing vector 0x%02X and IRQ %d\n", |
---|
797 | gsi, vector, i); |
---|
798 | return i; |
---|
799 | } |
---|
800 | |
---|
801 | i = next_irq++; |
---|
802 | BUG_ON(i >= NR_IRQS); |
---|
803 | gsi_2_irq[gsi] = i; |
---|
804 | IO_APIC_VECTOR(i) = vector; |
---|
805 | printk(KERN_INFO "GSI %d assigned vector 0x%02X and IRQ %d\n", |
---|
806 | gsi, vector, i); |
---|
807 | return i; |
---|
808 | } |
---|
809 | |
---|
810 | static int pin_2_irq(int idx, int apic, int pin) |
---|
811 | { |
---|
812 | int irq, i; |
---|
813 | int bus = mp_irqs[idx].mpc_srcbus; |
---|
814 | |
---|
815 | /* |
---|
816 | * Debugging check, we are in big trouble if this message pops up! |
---|
817 | */ |
---|
818 | if (mp_irqs[idx].mpc_dstirq != pin) |
---|
819 | printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n"); |
---|
820 | |
---|
821 | switch (mp_bus_id_to_type[bus]) |
---|
822 | { |
---|
823 | case MP_BUS_ISA: /* ISA pin */ |
---|
824 | case MP_BUS_EISA: |
---|
825 | case MP_BUS_MCA: |
---|
826 | { |
---|
827 | irq = mp_irqs[idx].mpc_srcbusirq; |
---|
828 | break; |
---|
829 | } |
---|
830 | case MP_BUS_PCI: /* PCI pin */ |
---|
831 | { |
---|
832 | /* |
---|
833 | * PCI IRQs are mapped in order |
---|
834 | */ |
---|
835 | i = irq = 0; |
---|
836 | while (i < apic) |
---|
837 | irq += nr_ioapic_registers[i++]; |
---|
838 | irq += pin; |
---|
839 | irq = gsi_irq_sharing(irq); |
---|
840 | break; |
---|
841 | } |
---|
842 | default: |
---|
843 | { |
---|
844 | printk(KERN_ERR "unknown bus type %d.\n",bus); |
---|
845 | irq = 0; |
---|
846 | break; |
---|
847 | } |
---|
848 | } |
---|
849 | BUG_ON(irq >= NR_IRQS); |
---|
850 | |
---|
851 | /* |
---|
852 | * PCI IRQ command line redirection. Yes, limits are hardcoded. |
---|
853 | */ |
---|
854 | if ((pin >= 16) && (pin <= 23)) { |
---|
855 | if (pirq_entries[pin-16] != -1) { |
---|
856 | if (!pirq_entries[pin-16]) { |
---|
857 | apic_printk(APIC_VERBOSE, "disabling PIRQ%d\n", pin-16); |
---|
858 | } else { |
---|
859 | irq = pirq_entries[pin-16]; |
---|
860 | apic_printk(APIC_VERBOSE, "using PIRQ%d -> IRQ %d\n", |
---|
861 | pin-16, irq); |
---|
862 | } |
---|
863 | } |
---|
864 | } |
---|
865 | BUG_ON(irq >= NR_IRQS); |
---|
866 | return irq; |
---|
867 | } |
---|
868 | |
---|
869 | static inline int IO_APIC_irq_trigger(int irq) |
---|
870 | { |
---|
871 | int apic, idx, pin; |
---|
872 | |
---|
873 | for (apic = 0; apic < nr_ioapics; apic++) { |
---|
874 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { |
---|
875 | idx = find_irq_entry(apic,pin,mp_INT); |
---|
876 | if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin))) |
---|
877 | return irq_trigger(idx); |
---|
878 | } |
---|
879 | } |
---|
880 | /* |
---|
881 | * nonexistent IRQs are edge default |
---|
882 | */ |
---|
883 | return 0; |
---|
884 | } |
---|
885 | |
---|
886 | /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */ |
---|
887 | u8 irq_vector[NR_IRQ_VECTORS] __read_mostly; |
---|
888 | |
---|
889 | int assign_irq_vector(int irq) |
---|
890 | { |
---|
891 | unsigned long flags; |
---|
892 | int vector; |
---|
893 | struct physdev_irq irq_op; |
---|
894 | |
---|
895 | BUG_ON(irq != AUTO_ASSIGN && (unsigned)irq >= NR_IRQ_VECTORS); |
---|
896 | |
---|
897 | spin_lock_irqsave(&vector_lock, flags); |
---|
898 | |
---|
899 | if (irq != AUTO_ASSIGN && IO_APIC_VECTOR(irq) > 0) { |
---|
900 | spin_unlock_irqrestore(&vector_lock, flags); |
---|
901 | return IO_APIC_VECTOR(irq); |
---|
902 | } |
---|
903 | |
---|
904 | irq_op.irq = irq; |
---|
905 | if (HYPERVISOR_physdev_op(PHYSDEVOP_alloc_irq_vector, &irq_op)) { |
---|
906 | spin_unlock_irqrestore(&vector_lock, flags); |
---|
907 | return -ENOSPC; |
---|
908 | } |
---|
909 | |
---|
910 | vector = irq_op.vector; |
---|
911 | vector_irq[vector] = irq; |
---|
912 | if (irq != AUTO_ASSIGN) |
---|
913 | IO_APIC_VECTOR(irq) = vector; |
---|
914 | |
---|
915 | spin_unlock_irqrestore(&vector_lock, flags); |
---|
916 | |
---|
917 | return vector; |
---|
918 | } |
---|
919 | |
---|
920 | extern void (*interrupt[NR_IRQS])(void); |
---|
921 | #ifndef CONFIG_XEN |
---|
922 | static struct hw_interrupt_type ioapic_level_type; |
---|
923 | static struct hw_interrupt_type ioapic_edge_type; |
---|
924 | |
---|
925 | #define IOAPIC_AUTO -1 |
---|
926 | #define IOAPIC_EDGE 0 |
---|
927 | #define IOAPIC_LEVEL 1 |
---|
928 | |
---|
929 | static void ioapic_register_intr(int irq, int vector, unsigned long trigger) |
---|
930 | { |
---|
931 | unsigned idx; |
---|
932 | |
---|
933 | idx = use_pci_vector() && !platform_legacy_irq(irq) ? vector : irq; |
---|
934 | |
---|
935 | if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) || |
---|
936 | trigger == IOAPIC_LEVEL) |
---|
937 | irq_desc[idx].chip = &ioapic_level_type; |
---|
938 | else |
---|
939 | irq_desc[idx].chip = &ioapic_edge_type; |
---|
940 | set_intr_gate(vector, interrupt[idx]); |
---|
941 | } |
---|
942 | #else |
---|
943 | #define ioapic_register_intr(_irq,_vector,_trigger) ((void)0) |
---|
944 | #endif /* !CONFIG_XEN */ |
---|
945 | |
---|
946 | static void __init setup_IO_APIC_irqs(void) |
---|
947 | { |
---|
948 | struct IO_APIC_route_entry entry; |
---|
949 | int apic, pin, idx, irq, first_notcon = 1, vector; |
---|
950 | unsigned long flags; |
---|
951 | |
---|
952 | apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n"); |
---|
953 | |
---|
954 | for (apic = 0; apic < nr_ioapics; apic++) { |
---|
955 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { |
---|
956 | |
---|
957 | /* |
---|
958 | * add it to the IO-APIC irq-routing table: |
---|
959 | */ |
---|
960 | memset(&entry,0,sizeof(entry)); |
---|
961 | |
---|
962 | entry.delivery_mode = INT_DELIVERY_MODE; |
---|
963 | entry.dest_mode = INT_DEST_MODE; |
---|
964 | entry.mask = 0; /* enable IRQ */ |
---|
965 | entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS); |
---|
966 | |
---|
967 | idx = find_irq_entry(apic,pin,mp_INT); |
---|
968 | if (idx == -1) { |
---|
969 | if (first_notcon) { |
---|
970 | apic_printk(APIC_VERBOSE, KERN_DEBUG " IO-APIC (apicid-pin) %d-%d", mp_ioapics[apic].mpc_apicid, pin); |
---|
971 | first_notcon = 0; |
---|
972 | } else |
---|
973 | apic_printk(APIC_VERBOSE, ", %d-%d", mp_ioapics[apic].mpc_apicid, pin); |
---|
974 | continue; |
---|
975 | } |
---|
976 | |
---|
977 | entry.trigger = irq_trigger(idx); |
---|
978 | entry.polarity = irq_polarity(idx); |
---|
979 | |
---|
980 | if (irq_trigger(idx)) { |
---|
981 | entry.trigger = 1; |
---|
982 | entry.mask = 1; |
---|
983 | entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS); |
---|
984 | } |
---|
985 | |
---|
986 | irq = pin_2_irq(idx, apic, pin); |
---|
987 | add_pin_to_irq(irq, apic, pin); |
---|
988 | |
---|
989 | if (/* !apic && */ !IO_APIC_IRQ(irq)) |
---|
990 | continue; |
---|
991 | |
---|
992 | if (IO_APIC_IRQ(irq)) { |
---|
993 | vector = assign_irq_vector(irq); |
---|
994 | entry.vector = vector; |
---|
995 | |
---|
996 | ioapic_register_intr(irq, vector, IOAPIC_AUTO); |
---|
997 | if (!apic && (irq < 16)) |
---|
998 | disable_8259A_irq(irq); |
---|
999 | } |
---|
1000 | spin_lock_irqsave(&ioapic_lock, flags); |
---|
1001 | io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1)); |
---|
1002 | io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0)); |
---|
1003 | set_native_irq_info(irq, TARGET_CPUS); |
---|
1004 | spin_unlock_irqrestore(&ioapic_lock, flags); |
---|
1005 | } |
---|
1006 | } |
---|
1007 | |
---|
1008 | if (!first_notcon) |
---|
1009 | apic_printk(APIC_VERBOSE," not connected.\n"); |
---|
1010 | } |
---|
1011 | |
---|
1012 | #ifndef CONFIG_XEN |
---|
1013 | /* |
---|
1014 | * Set up the 8259A-master output pin as broadcast to all |
---|
1015 | * CPUs. |
---|
1016 | */ |
---|
1017 | static void __init setup_ExtINT_IRQ0_pin(unsigned int apic, unsigned int pin, int vector) |
---|
1018 | { |
---|
1019 | struct IO_APIC_route_entry entry; |
---|
1020 | unsigned long flags; |
---|
1021 | |
---|
1022 | memset(&entry,0,sizeof(entry)); |
---|
1023 | |
---|
1024 | disable_8259A_irq(0); |
---|
1025 | |
---|
1026 | /* mask LVT0 */ |
---|
1027 | apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT); |
---|
1028 | |
---|
1029 | /* |
---|
1030 | * We use logical delivery to get the timer IRQ |
---|
1031 | * to the first CPU. |
---|
1032 | */ |
---|
1033 | entry.dest_mode = INT_DEST_MODE; |
---|
1034 | entry.mask = 0; /* unmask IRQ now */ |
---|
1035 | entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS); |
---|
1036 | entry.delivery_mode = INT_DELIVERY_MODE; |
---|
1037 | entry.polarity = 0; |
---|
1038 | entry.trigger = 0; |
---|
1039 | entry.vector = vector; |
---|
1040 | |
---|
1041 | /* |
---|
1042 | * The timer IRQ doesn't have to know that behind the |
---|
1043 | * scene we have a 8259A-master in AEOI mode ... |
---|
1044 | */ |
---|
1045 | irq_desc[0].chip = &ioapic_edge_type; |
---|
1046 | |
---|
1047 | /* |
---|
1048 | * Add it to the IO-APIC irq-routing table: |
---|
1049 | */ |
---|
1050 | spin_lock_irqsave(&ioapic_lock, flags); |
---|
1051 | io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1)); |
---|
1052 | io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0)); |
---|
1053 | spin_unlock_irqrestore(&ioapic_lock, flags); |
---|
1054 | |
---|
1055 | enable_8259A_irq(0); |
---|
1056 | } |
---|
1057 | |
---|
1058 | void __init UNEXPECTED_IO_APIC(void) |
---|
1059 | { |
---|
1060 | } |
---|
1061 | |
---|
1062 | void __apicdebuginit print_IO_APIC(void) |
---|
1063 | { |
---|
1064 | int apic, i; |
---|
1065 | union IO_APIC_reg_00 reg_00; |
---|
1066 | union IO_APIC_reg_01 reg_01; |
---|
1067 | union IO_APIC_reg_02 reg_02; |
---|
1068 | unsigned long flags; |
---|
1069 | |
---|
1070 | if (apic_verbosity == APIC_QUIET) |
---|
1071 | return; |
---|
1072 | |
---|
1073 | printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries); |
---|
1074 | for (i = 0; i < nr_ioapics; i++) |
---|
1075 | printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n", |
---|
1076 | mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]); |
---|
1077 | |
---|
1078 | /* |
---|
1079 | * We are a bit conservative about what we expect. We have to |
---|
1080 | * know about every hardware change ASAP. |
---|
1081 | */ |
---|
1082 | printk(KERN_INFO "testing the IO APIC.......................\n"); |
---|
1083 | |
---|
1084 | for (apic = 0; apic < nr_ioapics; apic++) { |
---|
1085 | |
---|
1086 | spin_lock_irqsave(&ioapic_lock, flags); |
---|
1087 | reg_00.raw = io_apic_read(apic, 0); |
---|
1088 | reg_01.raw = io_apic_read(apic, 1); |
---|
1089 | if (reg_01.bits.version >= 0x10) |
---|
1090 | reg_02.raw = io_apic_read(apic, 2); |
---|
1091 | spin_unlock_irqrestore(&ioapic_lock, flags); |
---|
1092 | |
---|
1093 | printk("\n"); |
---|
1094 | printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid); |
---|
1095 | printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw); |
---|
1096 | printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID); |
---|
1097 | if (reg_00.bits.__reserved_1 || reg_00.bits.__reserved_2) |
---|
1098 | UNEXPECTED_IO_APIC(); |
---|
1099 | |
---|
1100 | printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01); |
---|
1101 | printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries); |
---|
1102 | if ( (reg_01.bits.entries != 0x0f) && /* older (Neptune) boards */ |
---|
1103 | (reg_01.bits.entries != 0x17) && /* typical ISA+PCI boards */ |
---|
1104 | (reg_01.bits.entries != 0x1b) && /* Compaq Proliant boards */ |
---|
1105 | (reg_01.bits.entries != 0x1f) && /* dual Xeon boards */ |
---|
1106 | (reg_01.bits.entries != 0x22) && /* bigger Xeon boards */ |
---|
1107 | (reg_01.bits.entries != 0x2E) && |
---|
1108 | (reg_01.bits.entries != 0x3F) && |
---|
1109 | (reg_01.bits.entries != 0x03) |
---|
1110 | ) |
---|
1111 | UNEXPECTED_IO_APIC(); |
---|
1112 | |
---|
1113 | printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ); |
---|
1114 | printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version); |
---|
1115 | if ( (reg_01.bits.version != 0x01) && /* 82489DX IO-APICs */ |
---|
1116 | (reg_01.bits.version != 0x02) && /* 82801BA IO-APICs (ICH2) */ |
---|
1117 | (reg_01.bits.version != 0x10) && /* oldest IO-APICs */ |
---|
1118 | (reg_01.bits.version != 0x11) && /* Pentium/Pro IO-APICs */ |
---|
1119 | (reg_01.bits.version != 0x13) && /* Xeon IO-APICs */ |
---|
1120 | (reg_01.bits.version != 0x20) /* Intel P64H (82806 AA) */ |
---|
1121 | ) |
---|
1122 | UNEXPECTED_IO_APIC(); |
---|
1123 | if (reg_01.bits.__reserved_1 || reg_01.bits.__reserved_2) |
---|
1124 | UNEXPECTED_IO_APIC(); |
---|
1125 | |
---|
1126 | if (reg_01.bits.version >= 0x10) { |
---|
1127 | printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw); |
---|
1128 | printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration); |
---|
1129 | if (reg_02.bits.__reserved_1 || reg_02.bits.__reserved_2) |
---|
1130 | UNEXPECTED_IO_APIC(); |
---|
1131 | } |
---|
1132 | |
---|
1133 | printk(KERN_DEBUG ".... IRQ redirection table:\n"); |
---|
1134 | |
---|
1135 | printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol" |
---|
1136 | " Stat Dest Deli Vect: \n"); |
---|
1137 | |
---|
1138 | for (i = 0; i <= reg_01.bits.entries; i++) { |
---|
1139 | struct IO_APIC_route_entry entry; |
---|
1140 | |
---|
1141 | spin_lock_irqsave(&ioapic_lock, flags); |
---|
1142 | *(((int *)&entry)+0) = io_apic_read(apic, 0x10+i*2); |
---|
1143 | *(((int *)&entry)+1) = io_apic_read(apic, 0x11+i*2); |
---|
1144 | spin_unlock_irqrestore(&ioapic_lock, flags); |
---|
1145 | |
---|
1146 | printk(KERN_DEBUG " %02x %03X %02X ", |
---|
1147 | i, |
---|
1148 | entry.dest.logical.logical_dest, |
---|
1149 | entry.dest.physical.physical_dest |
---|
1150 | ); |
---|
1151 | |
---|
1152 | printk("%1d %1d %1d %1d %1d %1d %1d %02X\n", |
---|
1153 | entry.mask, |
---|
1154 | entry.trigger, |
---|
1155 | entry.irr, |
---|
1156 | entry.polarity, |
---|
1157 | entry.delivery_status, |
---|
1158 | entry.dest_mode, |
---|
1159 | entry.delivery_mode, |
---|
1160 | entry.vector |
---|
1161 | ); |
---|
1162 | } |
---|
1163 | } |
---|
1164 | if (use_pci_vector()) |
---|
1165 | printk(KERN_INFO "Using vector-based indexing\n"); |
---|
1166 | printk(KERN_DEBUG "IRQ to pin mappings:\n"); |
---|
1167 | for (i = 0; i < NR_IRQS; i++) { |
---|
1168 | struct irq_pin_list *entry = irq_2_pin + i; |
---|
1169 | if (entry->pin < 0) |
---|
1170 | continue; |
---|
1171 | if (use_pci_vector() && !platform_legacy_irq(i)) |
---|
1172 | printk(KERN_DEBUG "IRQ%d ", IO_APIC_VECTOR(i)); |
---|
1173 | else |
---|
1174 | printk(KERN_DEBUG "IRQ%d ", i); |
---|
1175 | for (;;) { |
---|
1176 | printk("-> %d:%d", entry->apic, entry->pin); |
---|
1177 | if (!entry->next) |
---|
1178 | break; |
---|
1179 | entry = irq_2_pin + entry->next; |
---|
1180 | } |
---|
1181 | printk("\n"); |
---|
1182 | } |
---|
1183 | |
---|
1184 | printk(KERN_INFO ".................................... done.\n"); |
---|
1185 | |
---|
1186 | return; |
---|
1187 | } |
---|
1188 | |
---|
1189 | #if 0 |
---|
1190 | |
---|
1191 | static __apicdebuginit void print_APIC_bitfield (int base) |
---|
1192 | { |
---|
1193 | unsigned int v; |
---|
1194 | int i, j; |
---|
1195 | |
---|
1196 | if (apic_verbosity == APIC_QUIET) |
---|
1197 | return; |
---|
1198 | |
---|
1199 | printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG); |
---|
1200 | for (i = 0; i < 8; i++) { |
---|
1201 | v = apic_read(base + i*0x10); |
---|
1202 | for (j = 0; j < 32; j++) { |
---|
1203 | if (v & (1<<j)) |
---|
1204 | printk("1"); |
---|
1205 | else |
---|
1206 | printk("0"); |
---|
1207 | } |
---|
1208 | printk("\n"); |
---|
1209 | } |
---|
1210 | } |
---|
1211 | |
---|
1212 | void __apicdebuginit print_local_APIC(void * dummy) |
---|
1213 | { |
---|
1214 | unsigned int v, ver, maxlvt; |
---|
1215 | |
---|
1216 | if (apic_verbosity == APIC_QUIET) |
---|
1217 | return; |
---|
1218 | |
---|
1219 | printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n", |
---|
1220 | smp_processor_id(), hard_smp_processor_id()); |
---|
1221 | v = apic_read(APIC_ID); |
---|
1222 | printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, GET_APIC_ID(v)); |
---|
1223 | v = apic_read(APIC_LVR); |
---|
1224 | printk(KERN_INFO "... APIC VERSION: %08x\n", v); |
---|
1225 | ver = GET_APIC_VERSION(v); |
---|
1226 | maxlvt = get_maxlvt(); |
---|
1227 | |
---|
1228 | v = apic_read(APIC_TASKPRI); |
---|
1229 | printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK); |
---|
1230 | |
---|
1231 | v = apic_read(APIC_ARBPRI); |
---|
1232 | printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v, |
---|
1233 | v & APIC_ARBPRI_MASK); |
---|
1234 | v = apic_read(APIC_PROCPRI); |
---|
1235 | printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v); |
---|
1236 | |
---|
1237 | v = apic_read(APIC_EOI); |
---|
1238 | printk(KERN_DEBUG "... APIC EOI: %08x\n", v); |
---|
1239 | v = apic_read(APIC_RRR); |
---|
1240 | printk(KERN_DEBUG "... APIC RRR: %08x\n", v); |
---|
1241 | v = apic_read(APIC_LDR); |
---|
1242 | printk(KERN_DEBUG "... APIC LDR: %08x\n", v); |
---|
1243 | v = apic_read(APIC_DFR); |
---|
1244 | printk(KERN_DEBUG "... APIC DFR: %08x\n", v); |
---|
1245 | v = apic_read(APIC_SPIV); |
---|
1246 | printk(KERN_DEBUG "... APIC SPIV: %08x\n", v); |
---|
1247 | |
---|
1248 | printk(KERN_DEBUG "... APIC ISR field:\n"); |
---|
1249 | print_APIC_bitfield(APIC_ISR); |
---|
1250 | printk(KERN_DEBUG "... APIC TMR field:\n"); |
---|
1251 | print_APIC_bitfield(APIC_TMR); |
---|
1252 | printk(KERN_DEBUG "... APIC IRR field:\n"); |
---|
1253 | print_APIC_bitfield(APIC_IRR); |
---|
1254 | |
---|
1255 | v = apic_read(APIC_ESR); |
---|
1256 | printk(KERN_DEBUG "... APIC ESR: %08x\n", v); |
---|
1257 | |
---|
1258 | v = apic_read(APIC_ICR); |
---|
1259 | printk(KERN_DEBUG "... APIC ICR: %08x\n", v); |
---|
1260 | v = apic_read(APIC_ICR2); |
---|
1261 | printk(KERN_DEBUG "... APIC ICR2: %08x\n", v); |
---|
1262 | |
---|
1263 | v = apic_read(APIC_LVTT); |
---|
1264 | printk(KERN_DEBUG "... APIC LVTT: %08x\n", v); |
---|
1265 | |
---|
1266 | if (maxlvt > 3) { /* PC is LVT#4. */ |
---|
1267 | v = apic_read(APIC_LVTPC); |
---|
1268 | printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v); |
---|
1269 | } |
---|
1270 | v = apic_read(APIC_LVT0); |
---|
1271 | printk(KERN_DEBUG "... APIC LVT0: %08x\n", v); |
---|
1272 | v = apic_read(APIC_LVT1); |
---|
1273 | printk(KERN_DEBUG "... APIC LVT1: %08x\n", v); |
---|
1274 | |
---|
1275 | if (maxlvt > 2) { /* ERR is LVT#3. */ |
---|
1276 | v = apic_read(APIC_LVTERR); |
---|
1277 | printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v); |
---|
1278 | } |
---|
1279 | |
---|
1280 | v = apic_read(APIC_TMICT); |
---|
1281 | printk(KERN_DEBUG "... APIC TMICT: %08x\n", v); |
---|
1282 | v = apic_read(APIC_TMCCT); |
---|
1283 | printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v); |
---|
1284 | v = apic_read(APIC_TDCR); |
---|
1285 | printk(KERN_DEBUG "... APIC TDCR: %08x\n", v); |
---|
1286 | printk("\n"); |
---|
1287 | } |
---|
1288 | |
---|
1289 | void print_all_local_APICs (void) |
---|
1290 | { |
---|
1291 | on_each_cpu(print_local_APIC, NULL, 1, 1); |
---|
1292 | } |
---|
1293 | |
---|
1294 | void __apicdebuginit print_PIC(void) |
---|
1295 | { |
---|
1296 | unsigned int v; |
---|
1297 | unsigned long flags; |
---|
1298 | |
---|
1299 | if (apic_verbosity == APIC_QUIET) |
---|
1300 | return; |
---|
1301 | |
---|
1302 | printk(KERN_DEBUG "\nprinting PIC contents\n"); |
---|
1303 | |
---|
1304 | spin_lock_irqsave(&i8259A_lock, flags); |
---|
1305 | |
---|
1306 | v = inb(0xa1) << 8 | inb(0x21); |
---|
1307 | printk(KERN_DEBUG "... PIC IMR: %04x\n", v); |
---|
1308 | |
---|
1309 | v = inb(0xa0) << 8 | inb(0x20); |
---|
1310 | printk(KERN_DEBUG "... PIC IRR: %04x\n", v); |
---|
1311 | |
---|
1312 | outb(0x0b,0xa0); |
---|
1313 | outb(0x0b,0x20); |
---|
1314 | v = inb(0xa0) << 8 | inb(0x20); |
---|
1315 | outb(0x0a,0xa0); |
---|
1316 | outb(0x0a,0x20); |
---|
1317 | |
---|
1318 | spin_unlock_irqrestore(&i8259A_lock, flags); |
---|
1319 | |
---|
1320 | printk(KERN_DEBUG "... PIC ISR: %04x\n", v); |
---|
1321 | |
---|
1322 | v = inb(0x4d1) << 8 | inb(0x4d0); |
---|
1323 | printk(KERN_DEBUG "... PIC ELCR: %04x\n", v); |
---|
1324 | } |
---|
1325 | |
---|
1326 | #endif /* 0 */ |
---|
1327 | |
---|
1328 | #else |
---|
1329 | void __init print_IO_APIC(void) { } |
---|
1330 | #endif /* !CONFIG_XEN */ |
---|
1331 | |
---|
1332 | static void __init enable_IO_APIC(void) |
---|
1333 | { |
---|
1334 | union IO_APIC_reg_01 reg_01; |
---|
1335 | #ifndef CONFIG_XEN |
---|
1336 | int i8259_apic, i8259_pin; |
---|
1337 | #endif |
---|
1338 | int i, apic; |
---|
1339 | unsigned long flags; |
---|
1340 | |
---|
1341 | for (i = 0; i < PIN_MAP_SIZE; i++) { |
---|
1342 | irq_2_pin[i].pin = -1; |
---|
1343 | irq_2_pin[i].next = 0; |
---|
1344 | } |
---|
1345 | if (!pirqs_enabled) |
---|
1346 | for (i = 0; i < MAX_PIRQS; i++) |
---|
1347 | pirq_entries[i] = -1; |
---|
1348 | |
---|
1349 | /* |
---|
1350 | * The number of IO-APIC IRQ registers (== #pins): |
---|
1351 | */ |
---|
1352 | for (apic = 0; apic < nr_ioapics; apic++) { |
---|
1353 | spin_lock_irqsave(&ioapic_lock, flags); |
---|
1354 | reg_01.raw = io_apic_read(apic, 1); |
---|
1355 | spin_unlock_irqrestore(&ioapic_lock, flags); |
---|
1356 | nr_ioapic_registers[apic] = reg_01.bits.entries+1; |
---|
1357 | } |
---|
1358 | #ifndef CONFIG_XEN |
---|
1359 | for(apic = 0; apic < nr_ioapics; apic++) { |
---|
1360 | int pin; |
---|
1361 | /* See if any of the pins is in ExtINT mode */ |
---|
1362 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { |
---|
1363 | struct IO_APIC_route_entry entry; |
---|
1364 | spin_lock_irqsave(&ioapic_lock, flags); |
---|
1365 | *(((int *)&entry) + 0) = io_apic_read(apic, 0x10 + 2 * pin); |
---|
1366 | *(((int *)&entry) + 1) = io_apic_read(apic, 0x11 + 2 * pin); |
---|
1367 | spin_unlock_irqrestore(&ioapic_lock, flags); |
---|
1368 | |
---|
1369 | |
---|
1370 | /* If the interrupt line is enabled and in ExtInt mode |
---|
1371 | * I have found the pin where the i8259 is connected. |
---|
1372 | */ |
---|
1373 | if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) { |
---|
1374 | ioapic_i8259.apic = apic; |
---|
1375 | ioapic_i8259.pin = pin; |
---|
1376 | goto found_i8259; |
---|
1377 | } |
---|
1378 | } |
---|
1379 | } |
---|
1380 | found_i8259: |
---|
1381 | /* Look to see what if the MP table has reported the ExtINT */ |
---|
1382 | i8259_pin = find_isa_irq_pin(0, mp_ExtINT); |
---|
1383 | i8259_apic = find_isa_irq_apic(0, mp_ExtINT); |
---|
1384 | /* Trust the MP table if nothing is setup in the hardware */ |
---|
1385 | if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) { |
---|
1386 | printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n"); |
---|
1387 | ioapic_i8259.pin = i8259_pin; |
---|
1388 | ioapic_i8259.apic = i8259_apic; |
---|
1389 | } |
---|
1390 | /* Complain if the MP table and the hardware disagree */ |
---|
1391 | if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) && |
---|
1392 | (i8259_pin >= 0) && (ioapic_i8259.pin >= 0)) |
---|
1393 | { |
---|
1394 | printk(KERN_WARNING "ExtINT in hardware and MP table differ\n"); |
---|
1395 | } |
---|
1396 | #endif |
---|
1397 | |
---|
1398 | /* |
---|
1399 | * Do not trust the IO-APIC being empty at bootup |
---|
1400 | */ |
---|
1401 | clear_IO_APIC(); |
---|
1402 | } |
---|
1403 | |
---|
1404 | /* |
---|
1405 | * Not an __init, needed by the reboot code |
---|
1406 | */ |
---|
1407 | void disable_IO_APIC(void) |
---|
1408 | { |
---|
1409 | /* |
---|
1410 | * Clear the IO-APIC before rebooting: |
---|
1411 | */ |
---|
1412 | clear_IO_APIC(); |
---|
1413 | |
---|
1414 | #ifndef CONFIG_XEN |
---|
1415 | /* |
---|
1416 | * If the i8259 is routed through an IOAPIC |
---|
1417 | * Put that IOAPIC in virtual wire mode |
---|
1418 | * so legacy interrupts can be delivered. |
---|
1419 | */ |
---|
1420 | if (ioapic_i8259.pin != -1) { |
---|
1421 | struct IO_APIC_route_entry entry; |
---|
1422 | unsigned long flags; |
---|
1423 | |
---|
1424 | memset(&entry, 0, sizeof(entry)); |
---|
1425 | entry.mask = 0; /* Enabled */ |
---|
1426 | entry.trigger = 0; /* Edge */ |
---|
1427 | entry.irr = 0; |
---|
1428 | entry.polarity = 0; /* High */ |
---|
1429 | entry.delivery_status = 0; |
---|
1430 | entry.dest_mode = 0; /* Physical */ |
---|
1431 | entry.delivery_mode = dest_ExtINT; /* ExtInt */ |
---|
1432 | entry.vector = 0; |
---|
1433 | entry.dest.physical.physical_dest = |
---|
1434 | GET_APIC_ID(apic_read(APIC_ID)); |
---|
1435 | |
---|
1436 | /* |
---|
1437 | * Add it to the IO-APIC irq-routing table: |
---|
1438 | */ |
---|
1439 | spin_lock_irqsave(&ioapic_lock, flags); |
---|
1440 | io_apic_write(ioapic_i8259.apic, 0x11+2*ioapic_i8259.pin, |
---|
1441 | *(((int *)&entry)+1)); |
---|
1442 | io_apic_write(ioapic_i8259.apic, 0x10+2*ioapic_i8259.pin, |
---|
1443 | *(((int *)&entry)+0)); |
---|
1444 | spin_unlock_irqrestore(&ioapic_lock, flags); |
---|
1445 | } |
---|
1446 | |
---|
1447 | disconnect_bsp_APIC(ioapic_i8259.pin != -1); |
---|
1448 | #endif |
---|
1449 | } |
---|
1450 | |
---|
1451 | /* |
---|
1452 | * function to set the IO-APIC physical IDs based on the |
---|
1453 | * values stored in the MPC table. |
---|
1454 | * |
---|
1455 | * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999 |
---|
1456 | */ |
---|
1457 | |
---|
1458 | #ifndef CONFIG_XEN |
---|
1459 | static void __init setup_ioapic_ids_from_mpc (void) |
---|
1460 | { |
---|
1461 | union IO_APIC_reg_00 reg_00; |
---|
1462 | int apic; |
---|
1463 | int i; |
---|
1464 | unsigned char old_id; |
---|
1465 | unsigned long flags; |
---|
1466 | |
---|
1467 | /* |
---|
1468 | * Set the IOAPIC ID to the value stored in the MPC table. |
---|
1469 | */ |
---|
1470 | for (apic = 0; apic < nr_ioapics; apic++) { |
---|
1471 | |
---|
1472 | /* Read the register 0 value */ |
---|
1473 | spin_lock_irqsave(&ioapic_lock, flags); |
---|
1474 | reg_00.raw = io_apic_read(apic, 0); |
---|
1475 | spin_unlock_irqrestore(&ioapic_lock, flags); |
---|
1476 | |
---|
1477 | old_id = mp_ioapics[apic].mpc_apicid; |
---|
1478 | |
---|
1479 | |
---|
1480 | printk(KERN_INFO "Using IO-APIC %d\n", mp_ioapics[apic].mpc_apicid); |
---|
1481 | |
---|
1482 | |
---|
1483 | /* |
---|
1484 | * We need to adjust the IRQ routing table |
---|
1485 | * if the ID changed. |
---|
1486 | */ |
---|
1487 | if (old_id != mp_ioapics[apic].mpc_apicid) |
---|
1488 | for (i = 0; i < mp_irq_entries; i++) |
---|
1489 | if (mp_irqs[i].mpc_dstapic == old_id) |
---|
1490 | mp_irqs[i].mpc_dstapic |
---|
1491 | = mp_ioapics[apic].mpc_apicid; |
---|
1492 | |
---|
1493 | /* |
---|
1494 | * Read the right value from the MPC table and |
---|
1495 | * write it into the ID register. |
---|
1496 | */ |
---|
1497 | apic_printk(APIC_VERBOSE,KERN_INFO "...changing IO-APIC physical APIC ID to %d ...", |
---|
1498 | mp_ioapics[apic].mpc_apicid); |
---|
1499 | |
---|
1500 | reg_00.bits.ID = mp_ioapics[apic].mpc_apicid; |
---|
1501 | spin_lock_irqsave(&ioapic_lock, flags); |
---|
1502 | io_apic_write(apic, 0, reg_00.raw); |
---|
1503 | spin_unlock_irqrestore(&ioapic_lock, flags); |
---|
1504 | |
---|
1505 | /* |
---|
1506 | * Sanity check |
---|
1507 | */ |
---|
1508 | spin_lock_irqsave(&ioapic_lock, flags); |
---|
1509 | reg_00.raw = io_apic_read(apic, 0); |
---|
1510 | spin_unlock_irqrestore(&ioapic_lock, flags); |
---|
1511 | if (reg_00.bits.ID != mp_ioapics[apic].mpc_apicid) |
---|
1512 | printk("could not set ID!\n"); |
---|
1513 | else |
---|
1514 | apic_printk(APIC_VERBOSE," ok.\n"); |
---|
1515 | } |
---|
1516 | } |
---|
1517 | #else |
---|
1518 | static void __init setup_ioapic_ids_from_mpc(void) { } |
---|
1519 | #endif |
---|
1520 | |
---|
1521 | /* |
---|
1522 | * There is a nasty bug in some older SMP boards, their mptable lies |
---|
1523 | * about the timer IRQ. We do the following to work around the situation: |
---|
1524 | * |
---|
1525 | * - timer IRQ defaults to IO-APIC IRQ |
---|
1526 | * - if this function detects that timer IRQs are defunct, then we fall |
---|
1527 | * back to ISA timer IRQs |
---|
1528 | */ |
---|
1529 | #ifndef CONFIG_XEN |
---|
1530 | static int __init timer_irq_works(void) |
---|
1531 | { |
---|
1532 | unsigned long t1 = jiffies; |
---|
1533 | |
---|
1534 | local_irq_enable(); |
---|
1535 | /* Let ten ticks pass... */ |
---|
1536 | mdelay((10 * 1000) / HZ); |
---|
1537 | |
---|
1538 | /* |
---|
1539 | * Expect a few ticks at least, to be sure some possible |
---|
1540 | * glue logic does not lock up after one or two first |
---|
1541 | * ticks in a non-ExtINT mode. Also the local APIC |
---|
1542 | * might have cached one ExtINT interrupt. Finally, at |
---|
1543 | * least one tick may be lost due to delays. |
---|
1544 | */ |
---|
1545 | |
---|
1546 | /* jiffies wrap? */ |
---|
1547 | if (jiffies - t1 > 4) |
---|
1548 | return 1; |
---|
1549 | return 0; |
---|
1550 | } |
---|
1551 | |
---|
1552 | /* |
---|
1553 | * In the SMP+IOAPIC case it might happen that there are an unspecified |
---|
1554 | * number of pending IRQ events unhandled. These cases are very rare, |
---|
1555 | * so we 'resend' these IRQs via IPIs, to the same CPU. It's much |
---|
1556 | * better to do it this way as thus we do not have to be aware of |
---|
1557 | * 'pending' interrupts in the IRQ path, except at this point. |
---|
1558 | */ |
---|
1559 | /* |
---|
1560 | * Edge triggered needs to resend any interrupt |
---|
1561 | * that was delayed but this is now handled in the device |
---|
1562 | * independent code. |
---|
1563 | */ |
---|
1564 | |
---|
1565 | /* |
---|
1566 | * Starting up a edge-triggered IO-APIC interrupt is |
---|
1567 | * nasty - we need to make sure that we get the edge. |
---|
1568 | * If it is already asserted for some reason, we need |
---|
1569 | * return 1 to indicate that is was pending. |
---|
1570 | * |
---|
1571 | * This is not complete - we should be able to fake |
---|
1572 | * an edge even if it isn't on the 8259A... |
---|
1573 | */ |
---|
1574 | |
---|
1575 | static unsigned int startup_edge_ioapic_irq(unsigned int irq) |
---|
1576 | { |
---|
1577 | int was_pending = 0; |
---|
1578 | unsigned long flags; |
---|
1579 | |
---|
1580 | spin_lock_irqsave(&ioapic_lock, flags); |
---|
1581 | if (irq < 16) { |
---|
1582 | disable_8259A_irq(irq); |
---|
1583 | if (i8259A_irq_pending(irq)) |
---|
1584 | was_pending = 1; |
---|
1585 | } |
---|
1586 | __unmask_IO_APIC_irq(irq); |
---|
1587 | spin_unlock_irqrestore(&ioapic_lock, flags); |
---|
1588 | |
---|
1589 | return was_pending; |
---|
1590 | } |
---|
1591 | |
---|
1592 | /* |
---|
1593 | * Once we have recorded IRQ_PENDING already, we can mask the |
---|
1594 | * interrupt for real. This prevents IRQ storms from unhandled |
---|
1595 | * devices. |
---|
1596 | */ |
---|
1597 | static void ack_edge_ioapic_irq(unsigned int irq) |
---|
1598 | { |
---|
1599 | move_irq(irq); |
---|
1600 | if ((irq_desc[irq].status & (IRQ_PENDING | IRQ_DISABLED)) |
---|
1601 | == (IRQ_PENDING | IRQ_DISABLED)) |
---|
1602 | mask_IO_APIC_irq(irq); |
---|
1603 | ack_APIC_irq(); |
---|
1604 | } |
---|
1605 | |
---|
1606 | /* |
---|
1607 | * Level triggered interrupts can just be masked, |
---|
1608 | * and shutting down and starting up the interrupt |
---|
1609 | * is the same as enabling and disabling them -- except |
---|
1610 | * with a startup need to return a "was pending" value. |
---|
1611 | * |
---|
1612 | * Level triggered interrupts are special because we |
---|
1613 | * do not touch any IO-APIC register while handling |
---|
1614 | * them. We ack the APIC in the end-IRQ handler, not |
---|
1615 | * in the start-IRQ-handler. Protection against reentrance |
---|
1616 | * from the same interrupt is still provided, both by the |
---|
1617 | * generic IRQ layer and by the fact that an unacked local |
---|
1618 | * APIC does not accept IRQs. |
---|
1619 | */ |
---|
1620 | static unsigned int startup_level_ioapic_irq (unsigned int irq) |
---|
1621 | { |
---|
1622 | unmask_IO_APIC_irq(irq); |
---|
1623 | |
---|
1624 | return 0; /* don't check for pending */ |
---|
1625 | } |
---|
1626 | |
---|
1627 | static void end_level_ioapic_irq (unsigned int irq) |
---|
1628 | { |
---|
1629 | move_irq(irq); |
---|
1630 | ack_APIC_irq(); |
---|
1631 | } |
---|
1632 | |
---|
1633 | #ifdef CONFIG_PCI_MSI |
---|
1634 | static unsigned int startup_edge_ioapic_vector(unsigned int vector) |
---|
1635 | { |
---|
1636 | int irq = vector_to_irq(vector); |
---|
1637 | |
---|
1638 | return startup_edge_ioapic_irq(irq); |
---|
1639 | } |
---|
1640 | |
---|
1641 | static void ack_edge_ioapic_vector(unsigned int vector) |
---|
1642 | { |
---|
1643 | int irq = vector_to_irq(vector); |
---|
1644 | |
---|
1645 | move_native_irq(vector); |
---|
1646 | ack_edge_ioapic_irq(irq); |
---|
1647 | } |
---|
1648 | |
---|
1649 | static unsigned int startup_level_ioapic_vector (unsigned int vector) |
---|
1650 | { |
---|
1651 | int irq = vector_to_irq(vector); |
---|
1652 | |
---|
1653 | return startup_level_ioapic_irq (irq); |
---|
1654 | } |
---|
1655 | |
---|
1656 | static void end_level_ioapic_vector (unsigned int vector) |
---|
1657 | { |
---|
1658 | int irq = vector_to_irq(vector); |
---|
1659 | |
---|
1660 | move_native_irq(vector); |
---|
1661 | end_level_ioapic_irq(irq); |
---|
1662 | } |
---|
1663 | |
---|
1664 | static void mask_IO_APIC_vector (unsigned int vector) |
---|
1665 | { |
---|
1666 | int irq = vector_to_irq(vector); |
---|
1667 | |
---|
1668 | mask_IO_APIC_irq(irq); |
---|
1669 | } |
---|
1670 | |
---|
1671 | static void unmask_IO_APIC_vector (unsigned int vector) |
---|
1672 | { |
---|
1673 | int irq = vector_to_irq(vector); |
---|
1674 | |
---|
1675 | unmask_IO_APIC_irq(irq); |
---|
1676 | } |
---|
1677 | |
---|
1678 | #ifdef CONFIG_SMP |
---|
1679 | static void set_ioapic_affinity_vector (unsigned int vector, |
---|
1680 | cpumask_t cpu_mask) |
---|
1681 | { |
---|
1682 | int irq = vector_to_irq(vector); |
---|
1683 | |
---|
1684 | set_native_irq_info(vector, cpu_mask); |
---|
1685 | set_ioapic_affinity_irq(irq, cpu_mask); |
---|
1686 | } |
---|
1687 | #endif // CONFIG_SMP |
---|
1688 | #endif // CONFIG_PCI_MSI |
---|
1689 | |
---|
1690 | static int ioapic_retrigger(unsigned int irq) |
---|
1691 | { |
---|
1692 | send_IPI_self(IO_APIC_VECTOR(irq)); |
---|
1693 | |
---|
1694 | return 1; |
---|
1695 | } |
---|
1696 | |
---|
1697 | /* |
---|
1698 | * Level and edge triggered IO-APIC interrupts need different handling, |
---|
1699 | * so we use two separate IRQ descriptors. Edge triggered IRQs can be |
---|
1700 | * handled with the level-triggered descriptor, but that one has slightly |
---|
1701 | * more overhead. Level-triggered interrupts cannot be handled with the |
---|
1702 | * edge-triggered handler, without risking IRQ storms and other ugly |
---|
1703 | * races. |
---|
1704 | */ |
---|
1705 | |
---|
1706 | static struct hw_interrupt_type ioapic_edge_type __read_mostly = { |
---|
1707 | .typename = "IO-APIC-edge", |
---|
1708 | .startup = startup_edge_ioapic, |
---|
1709 | .shutdown = shutdown_edge_ioapic, |
---|
1710 | .enable = enable_edge_ioapic, |
---|
1711 | .disable = disable_edge_ioapic, |
---|
1712 | .ack = ack_edge_ioapic, |
---|
1713 | .end = end_edge_ioapic, |
---|
1714 | #ifdef CONFIG_SMP |
---|
1715 | .set_affinity = set_ioapic_affinity, |
---|
1716 | #endif |
---|
1717 | .retrigger = ioapic_retrigger, |
---|
1718 | }; |
---|
1719 | |
---|
1720 | static struct hw_interrupt_type ioapic_level_type __read_mostly = { |
---|
1721 | .typename = "IO-APIC-level", |
---|
1722 | .startup = startup_level_ioapic, |
---|
1723 | .shutdown = shutdown_level_ioapic, |
---|
1724 | .enable = enable_level_ioapic, |
---|
1725 | .disable = disable_level_ioapic, |
---|
1726 | .ack = mask_and_ack_level_ioapic, |
---|
1727 | .end = end_level_ioapic, |
---|
1728 | #ifdef CONFIG_SMP |
---|
1729 | .set_affinity = set_ioapic_affinity, |
---|
1730 | #endif |
---|
1731 | .retrigger = ioapic_retrigger, |
---|
1732 | }; |
---|
1733 | #endif /* !CONFIG_XEN */ |
---|
1734 | |
---|
1735 | static inline void init_IO_APIC_traps(void) |
---|
1736 | { |
---|
1737 | int irq; |
---|
1738 | |
---|
1739 | /* |
---|
1740 | * NOTE! The local APIC isn't very good at handling |
---|
1741 | * multiple interrupts at the same interrupt level. |
---|
1742 | * As the interrupt level is determined by taking the |
---|
1743 | * vector number and shifting that right by 4, we |
---|
1744 | * want to spread these out a bit so that they don't |
---|
1745 | * all fall in the same interrupt level. |
---|
1746 | * |
---|
1747 | * Also, we've got to be careful not to trash gate |
---|
1748 | * 0x80, because int 0x80 is hm, kind of importantish. ;) |
---|
1749 | */ |
---|
1750 | for (irq = 0; irq < NR_IRQS ; irq++) { |
---|
1751 | int tmp = irq; |
---|
1752 | if (use_pci_vector()) { |
---|
1753 | if (!platform_legacy_irq(tmp)) |
---|
1754 | if ((tmp = vector_to_irq(tmp)) == -1) |
---|
1755 | continue; |
---|
1756 | } |
---|
1757 | if (IO_APIC_IRQ(tmp) && !IO_APIC_VECTOR(tmp)) { |
---|
1758 | /* |
---|
1759 | * Hmm.. We don't have an entry for this, |
---|
1760 | * so default to an old-fashioned 8259 |
---|
1761 | * interrupt if we can.. |
---|
1762 | */ |
---|
1763 | if (irq < 16) |
---|
1764 | make_8259A_irq(irq); |
---|
1765 | #ifndef CONFIG_XEN |
---|
1766 | else |
---|
1767 | /* Strange. Oh, well.. */ |
---|
1768 | irq_desc[irq].chip = &no_irq_type; |
---|
1769 | #endif |
---|
1770 | } |
---|
1771 | } |
---|
1772 | } |
---|
1773 | |
---|
1774 | #ifndef CONFIG_XEN |
---|
1775 | static void enable_lapic_irq (unsigned int irq) |
---|
1776 | { |
---|
1777 | unsigned long v; |
---|
1778 | |
---|
1779 | v = apic_read(APIC_LVT0); |
---|
1780 | apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED); |
---|
1781 | } |
---|
1782 | |
---|
1783 | static void disable_lapic_irq (unsigned int irq) |
---|
1784 | { |
---|
1785 | unsigned long v; |
---|
1786 | |
---|
1787 | v = apic_read(APIC_LVT0); |
---|
1788 | apic_write(APIC_LVT0, v | APIC_LVT_MASKED); |
---|
1789 | } |
---|
1790 | |
---|
1791 | static void ack_lapic_irq (unsigned int irq) |
---|
1792 | { |
---|
1793 | ack_APIC_irq(); |
---|
1794 | } |
---|
1795 | |
---|
1796 | static void end_lapic_irq (unsigned int i) { /* nothing */ } |
---|
1797 | |
---|
1798 | static struct hw_interrupt_type lapic_irq_type __read_mostly = { |
---|
1799 | .typename = "local-APIC-edge", |
---|
1800 | .startup = NULL, /* startup_irq() not used for IRQ0 */ |
---|
1801 | .shutdown = NULL, /* shutdown_irq() not used for IRQ0 */ |
---|
1802 | .enable = enable_lapic_irq, |
---|
1803 | .disable = disable_lapic_irq, |
---|
1804 | .ack = ack_lapic_irq, |
---|
1805 | .end = end_lapic_irq, |
---|
1806 | }; |
---|
1807 | |
---|
1808 | static void setup_nmi (void) |
---|
1809 | { |
---|
1810 | /* |
---|
1811 | * Dirty trick to enable the NMI watchdog ... |
---|
1812 | * We put the 8259A master into AEOI mode and |
---|
1813 | * unmask on all local APICs LVT0 as NMI. |
---|
1814 | * |
---|
1815 | * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire') |
---|
1816 | * is from Maciej W. Rozycki - so we do not have to EOI from |
---|
1817 | * the NMI handler or the timer interrupt. |
---|
1818 | */ |
---|
1819 | printk(KERN_INFO "activating NMI Watchdog ..."); |
---|
1820 | |
---|
1821 | enable_NMI_through_LVT0(NULL); |
---|
1822 | |
---|
1823 | printk(" done.\n"); |
---|
1824 | } |
---|
1825 | |
---|
1826 | /* |
---|
1827 | * This looks a bit hackish but it's about the only one way of sending |
---|
1828 | * a few INTA cycles to 8259As and any associated glue logic. ICR does |
---|
1829 | * not support the ExtINT mode, unfortunately. We need to send these |
---|
1830 | * cycles as some i82489DX-based boards have glue logic that keeps the |
---|
1831 | * 8259A interrupt line asserted until INTA. --macro |
---|
1832 | */ |
---|
1833 | static inline void unlock_ExtINT_logic(void) |
---|
1834 | { |
---|
1835 | int apic, pin, i; |
---|
1836 | struct IO_APIC_route_entry entry0, entry1; |
---|
1837 | unsigned char save_control, save_freq_select; |
---|
1838 | unsigned long flags; |
---|
1839 | |
---|
1840 | pin = find_isa_irq_pin(8, mp_INT); |
---|
1841 | apic = find_isa_irq_apic(8, mp_INT); |
---|
1842 | if (pin == -1) |
---|
1843 | return; |
---|
1844 | |
---|
1845 | spin_lock_irqsave(&ioapic_lock, flags); |
---|
1846 | *(((int *)&entry0) + 1) = io_apic_read(apic, 0x11 + 2 * pin); |
---|
1847 | *(((int *)&entry0) + 0) = io_apic_read(apic, 0x10 + 2 * pin); |
---|
1848 | spin_unlock_irqrestore(&ioapic_lock, flags); |
---|
1849 | clear_IO_APIC_pin(apic, pin); |
---|
1850 | |
---|
1851 | memset(&entry1, 0, sizeof(entry1)); |
---|
1852 | |
---|
1853 | entry1.dest_mode = 0; /* physical delivery */ |
---|
1854 | entry1.mask = 0; /* unmask IRQ now */ |
---|
1855 | entry1.dest.physical.physical_dest = hard_smp_processor_id(); |
---|
1856 | entry1.delivery_mode = dest_ExtINT; |
---|
1857 | entry1.polarity = entry0.polarity; |
---|
1858 | entry1.trigger = 0; |
---|
1859 | entry1.vector = 0; |
---|
1860 | |
---|
1861 | spin_lock_irqsave(&ioapic_lock, flags); |
---|
1862 | io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry1) + 1)); |
---|
1863 | io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry1) + 0)); |
---|
1864 | spin_unlock_irqrestore(&ioapic_lock, flags); |
---|
1865 | |
---|
1866 | save_control = CMOS_READ(RTC_CONTROL); |
---|
1867 | save_freq_select = CMOS_READ(RTC_FREQ_SELECT); |
---|
1868 | CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6, |
---|
1869 | RTC_FREQ_SELECT); |
---|
1870 | CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL); |
---|
1871 | |
---|
1872 | i = 100; |
---|
1873 | while (i-- > 0) { |
---|
1874 | mdelay(10); |
---|
1875 | if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF) |
---|
1876 | i -= 10; |
---|
1877 | } |
---|
1878 | |
---|
1879 | CMOS_WRITE(save_control, RTC_CONTROL); |
---|
1880 | CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT); |
---|
1881 | clear_IO_APIC_pin(apic, pin); |
---|
1882 | |
---|
1883 | spin_lock_irqsave(&ioapic_lock, flags); |
---|
1884 | io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry0) + 1)); |
---|
1885 | io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry0) + 0)); |
---|
1886 | spin_unlock_irqrestore(&ioapic_lock, flags); |
---|
1887 | } |
---|
1888 | |
---|
1889 | int timer_uses_ioapic_pin_0; |
---|
1890 | |
---|
1891 | /* |
---|
1892 | * This code may look a bit paranoid, but it's supposed to cooperate with |
---|
1893 | * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ |
---|
1894 | * is so screwy. Thanks to Brian Perkins for testing/hacking this beast |
---|
1895 | * fanatically on his truly buggy board. |
---|
1896 | * |
---|
1897 | * FIXME: really need to revamp this for modern platforms only. |
---|
1898 | */ |
---|
1899 | static inline void check_timer(void) |
---|
1900 | { |
---|
1901 | int apic1, pin1, apic2, pin2; |
---|
1902 | int vector; |
---|
1903 | |
---|
1904 | /* |
---|
1905 | * get/set the timer IRQ vector: |
---|
1906 | */ |
---|
1907 | disable_8259A_irq(0); |
---|
1908 | vector = assign_irq_vector(0); |
---|
1909 | set_intr_gate(vector, interrupt[0]); |
---|
1910 | |
---|
1911 | /* |
---|
1912 | * Subtle, code in do_timer_interrupt() expects an AEOI |
---|
1913 | * mode for the 8259A whenever interrupts are routed |
---|
1914 | * through I/O APICs. Also IRQ0 has to be enabled in |
---|
1915 | * the 8259A which implies the virtual wire has to be |
---|
1916 | * disabled in the local APIC. |
---|
1917 | */ |
---|
1918 | apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT); |
---|
1919 | init_8259A(1); |
---|
1920 | if (timer_over_8254 > 0) |
---|
1921 | enable_8259A_irq(0); |
---|
1922 | |
---|
1923 | pin1 = find_isa_irq_pin(0, mp_INT); |
---|
1924 | apic1 = find_isa_irq_apic(0, mp_INT); |
---|
1925 | pin2 = ioapic_i8259.pin; |
---|
1926 | apic2 = ioapic_i8259.apic; |
---|
1927 | |
---|
1928 | if (pin1 == 0) |
---|
1929 | timer_uses_ioapic_pin_0 = 1; |
---|
1930 | |
---|
1931 | apic_printk(APIC_VERBOSE,KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n", |
---|
1932 | vector, apic1, pin1, apic2, pin2); |
---|
1933 | |
---|
1934 | if (pin1 != -1) { |
---|
1935 | /* |
---|
1936 | * Ok, does IRQ0 through the IOAPIC work? |
---|
1937 | */ |
---|
1938 | unmask_IO_APIC_irq(0); |
---|
1939 | if (!no_timer_check && timer_irq_works()) { |
---|
1940 | nmi_watchdog_default(); |
---|
1941 | if (nmi_watchdog == NMI_IO_APIC) { |
---|
1942 | disable_8259A_irq(0); |
---|
1943 | setup_nmi(); |
---|
1944 | enable_8259A_irq(0); |
---|
1945 | } |
---|
1946 | if (disable_timer_pin_1 > 0) |
---|
1947 | clear_IO_APIC_pin(0, pin1); |
---|
1948 | return; |
---|
1949 | } |
---|
1950 | clear_IO_APIC_pin(apic1, pin1); |
---|
1951 | apic_printk(APIC_QUIET,KERN_ERR "..MP-BIOS bug: 8254 timer not " |
---|
1952 | "connected to IO-APIC\n"); |
---|
1953 | } |
---|
1954 | |
---|
1955 | apic_printk(APIC_VERBOSE,KERN_INFO "...trying to set up timer (IRQ0) " |
---|
1956 | "through the 8259A ... "); |
---|
1957 | if (pin2 != -1) { |
---|
1958 | apic_printk(APIC_VERBOSE,"\n..... (found apic %d pin %d) ...", |
---|
1959 | apic2, pin2); |
---|
1960 | /* |
---|
1961 | * legacy devices should be connected to IO APIC #0 |
---|
1962 | */ |
---|
1963 | setup_ExtINT_IRQ0_pin(apic2, pin2, vector); |
---|
1964 | if (timer_irq_works()) { |
---|
1965 | apic_printk(APIC_VERBOSE," works.\n"); |
---|
1966 | nmi_watchdog_default(); |
---|
1967 | if (nmi_watchdog == NMI_IO_APIC) { |
---|
1968 | setup_nmi(); |
---|
1969 | } |
---|
1970 | return; |
---|
1971 | } |
---|
1972 | /* |
---|
1973 | * Cleanup, just in case ... |
---|
1974 | */ |
---|
1975 | clear_IO_APIC_pin(apic2, pin2); |
---|
1976 | } |
---|
1977 | apic_printk(APIC_VERBOSE," failed.\n"); |
---|
1978 | |
---|
1979 | if (nmi_watchdog == NMI_IO_APIC) { |
---|
1980 | printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n"); |
---|
1981 | nmi_watchdog = 0; |
---|
1982 | } |
---|
1983 | |
---|
1984 | apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as Virtual Wire IRQ..."); |
---|
1985 | |
---|
1986 | disable_8259A_irq(0); |
---|
1987 | irq_desc[0].chip = &lapic_irq_type; |
---|
1988 | apic_write(APIC_LVT0, APIC_DM_FIXED | vector); /* Fixed mode */ |
---|
1989 | enable_8259A_irq(0); |
---|
1990 | |
---|
1991 | if (timer_irq_works()) { |
---|
1992 | apic_printk(APIC_VERBOSE," works.\n"); |
---|
1993 | return; |
---|
1994 | } |
---|
1995 | apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector); |
---|
1996 | apic_printk(APIC_VERBOSE," failed.\n"); |
---|
1997 | |
---|
1998 | apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as ExtINT IRQ..."); |
---|
1999 | |
---|
2000 | init_8259A(0); |
---|
2001 | make_8259A_irq(0); |
---|
2002 | apic_write(APIC_LVT0, APIC_DM_EXTINT); |
---|
2003 | |
---|
2004 | unlock_ExtINT_logic(); |
---|
2005 | |
---|
2006 | if (timer_irq_works()) { |
---|
2007 | apic_printk(APIC_VERBOSE," works.\n"); |
---|
2008 | return; |
---|
2009 | } |
---|
2010 | apic_printk(APIC_VERBOSE," failed :(.\n"); |
---|
2011 | panic("IO-APIC + timer doesn't work! Try using the 'noapic' kernel parameter\n"); |
---|
2012 | } |
---|
2013 | #else |
---|
2014 | #define check_timer() ((void)0) |
---|
2015 | int timer_uses_ioapic_pin_0 = 0; |
---|
2016 | #endif /* !CONFIG_XEN */ |
---|
2017 | |
---|
2018 | static int __init notimercheck(char *s) |
---|
2019 | { |
---|
2020 | no_timer_check = 1; |
---|
2021 | return 1; |
---|
2022 | } |
---|
2023 | __setup("no_timer_check", notimercheck); |
---|
2024 | |
---|
2025 | /* |
---|
2026 | * |
---|
2027 | * IRQ's that are handled by the PIC in the MPS IOAPIC case. |
---|
2028 | * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ. |
---|
2029 | * Linux doesn't really care, as it's not actually used |
---|
2030 | * for any interrupt handling anyway. |
---|
2031 | */ |
---|
2032 | #define PIC_IRQS (1<<2) |
---|
2033 | |
---|
2034 | void __init setup_IO_APIC(void) |
---|
2035 | { |
---|
2036 | enable_IO_APIC(); |
---|
2037 | |
---|
2038 | if (acpi_ioapic) |
---|
2039 | io_apic_irqs = ~0; /* all IRQs go through IOAPIC */ |
---|
2040 | else |
---|
2041 | io_apic_irqs = ~PIC_IRQS; |
---|
2042 | |
---|
2043 | apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n"); |
---|
2044 | |
---|
2045 | /* |
---|
2046 | * Set up the IO-APIC IRQ routing table. |
---|
2047 | */ |
---|
2048 | if (!acpi_ioapic) |
---|
2049 | setup_ioapic_ids_from_mpc(); |
---|
2050 | #ifndef CONFIG_XEN |
---|
2051 | sync_Arb_IDs(); |
---|
2052 | #endif /* !CONFIG_XEN */ |
---|
2053 | setup_IO_APIC_irqs(); |
---|
2054 | init_IO_APIC_traps(); |
---|
2055 | check_timer(); |
---|
2056 | if (!acpi_ioapic) |
---|
2057 | print_IO_APIC(); |
---|
2058 | } |
---|
2059 | |
---|
2060 | struct sysfs_ioapic_data { |
---|
2061 | struct sys_device dev; |
---|
2062 | struct IO_APIC_route_entry entry[0]; |
---|
2063 | }; |
---|
2064 | static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS]; |
---|
2065 | |
---|
2066 | static int ioapic_suspend(struct sys_device *dev, pm_message_t state) |
---|
2067 | { |
---|
2068 | struct IO_APIC_route_entry *entry; |
---|
2069 | struct sysfs_ioapic_data *data; |
---|
2070 | unsigned long flags; |
---|
2071 | int i; |
---|
2072 | |
---|
2073 | data = container_of(dev, struct sysfs_ioapic_data, dev); |
---|
2074 | entry = data->entry; |
---|
2075 | spin_lock_irqsave(&ioapic_lock, flags); |
---|
2076 | for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) { |
---|
2077 | *(((int *)entry) + 1) = io_apic_read(dev->id, 0x11 + 2 * i); |
---|
2078 | *(((int *)entry) + 0) = io_apic_read(dev->id, 0x10 + 2 * i); |
---|
2079 | } |
---|
2080 | spin_unlock_irqrestore(&ioapic_lock, flags); |
---|
2081 | |
---|
2082 | return 0; |
---|
2083 | } |
---|
2084 | |
---|
2085 | static int ioapic_resume(struct sys_device *dev) |
---|
2086 | { |
---|
2087 | struct IO_APIC_route_entry *entry; |
---|
2088 | struct sysfs_ioapic_data *data; |
---|
2089 | unsigned long flags; |
---|
2090 | union IO_APIC_reg_00 reg_00; |
---|
2091 | int i; |
---|
2092 | |
---|
2093 | data = container_of(dev, struct sysfs_ioapic_data, dev); |
---|
2094 | entry = data->entry; |
---|
2095 | |
---|
2096 | spin_lock_irqsave(&ioapic_lock, flags); |
---|
2097 | reg_00.raw = io_apic_read(dev->id, 0); |
---|
2098 | if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) { |
---|
2099 | reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid; |
---|
2100 | io_apic_write(dev->id, 0, reg_00.raw); |
---|
2101 | } |
---|
2102 | for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) { |
---|
2103 | io_apic_write(dev->id, 0x11+2*i, *(((int *)entry)+1)); |
---|
2104 | io_apic_write(dev->id, 0x10+2*i, *(((int *)entry)+0)); |
---|
2105 | } |
---|
2106 | spin_unlock_irqrestore(&ioapic_lock, flags); |
---|
2107 | |
---|
2108 | return 0; |
---|
2109 | } |
---|
2110 | |
---|
2111 | static struct sysdev_class ioapic_sysdev_class = { |
---|
2112 | set_kset_name("ioapic"), |
---|
2113 | .suspend = ioapic_suspend, |
---|
2114 | .resume = ioapic_resume, |
---|
2115 | }; |
---|
2116 | |
---|
2117 | static int __init ioapic_init_sysfs(void) |
---|
2118 | { |
---|
2119 | struct sys_device * dev; |
---|
2120 | int i, size, error = 0; |
---|
2121 | |
---|
2122 | error = sysdev_class_register(&ioapic_sysdev_class); |
---|
2123 | if (error) |
---|
2124 | return error; |
---|
2125 | |
---|
2126 | for (i = 0; i < nr_ioapics; i++ ) { |
---|
2127 | size = sizeof(struct sys_device) + nr_ioapic_registers[i] |
---|
2128 | * sizeof(struct IO_APIC_route_entry); |
---|
2129 | mp_ioapic_data[i] = kmalloc(size, GFP_KERNEL); |
---|
2130 | if (!mp_ioapic_data[i]) { |
---|
2131 | printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i); |
---|
2132 | continue; |
---|
2133 | } |
---|
2134 | memset(mp_ioapic_data[i], 0, size); |
---|
2135 | dev = &mp_ioapic_data[i]->dev; |
---|
2136 | dev->id = i; |
---|
2137 | dev->cls = &ioapic_sysdev_class; |
---|
2138 | error = sysdev_register(dev); |
---|
2139 | if (error) { |
---|
2140 | kfree(mp_ioapic_data[i]); |
---|
2141 | mp_ioapic_data[i] = NULL; |
---|
2142 | printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i); |
---|
2143 | continue; |
---|
2144 | } |
---|
2145 | } |
---|
2146 | |
---|
2147 | return 0; |
---|
2148 | } |
---|
2149 | |
---|
2150 | device_initcall(ioapic_init_sysfs); |
---|
2151 | |
---|
2152 | /* -------------------------------------------------------------------------- |
---|
2153 | ACPI-based IOAPIC Configuration |
---|
2154 | -------------------------------------------------------------------------- */ |
---|
2155 | |
---|
2156 | #ifdef CONFIG_ACPI |
---|
2157 | |
---|
2158 | #define IO_APIC_MAX_ID 0xFE |
---|
2159 | |
---|
2160 | int __init io_apic_get_version (int ioapic) |
---|
2161 | { |
---|
2162 | union IO_APIC_reg_01 reg_01; |
---|
2163 | unsigned long flags; |
---|
2164 | |
---|
2165 | spin_lock_irqsave(&ioapic_lock, flags); |
---|
2166 | reg_01.raw = io_apic_read(ioapic, 1); |
---|
2167 | spin_unlock_irqrestore(&ioapic_lock, flags); |
---|
2168 | |
---|
2169 | return reg_01.bits.version; |
---|
2170 | } |
---|
2171 | |
---|
2172 | |
---|
2173 | int __init io_apic_get_redir_entries (int ioapic) |
---|
2174 | { |
---|
2175 | union IO_APIC_reg_01 reg_01; |
---|
2176 | unsigned long flags; |
---|
2177 | |
---|
2178 | spin_lock_irqsave(&ioapic_lock, flags); |
---|
2179 | reg_01.raw = io_apic_read(ioapic, 1); |
---|
2180 | spin_unlock_irqrestore(&ioapic_lock, flags); |
---|
2181 | |
---|
2182 | return reg_01.bits.entries; |
---|
2183 | } |
---|
2184 | |
---|
2185 | |
---|
2186 | int io_apic_set_pci_routing (int ioapic, int pin, int irq, int edge_level, int active_high_low) |
---|
2187 | { |
---|
2188 | struct IO_APIC_route_entry entry; |
---|
2189 | unsigned long flags; |
---|
2190 | |
---|
2191 | if (!IO_APIC_IRQ(irq)) { |
---|
2192 | apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n", |
---|
2193 | ioapic); |
---|
2194 | return -EINVAL; |
---|
2195 | } |
---|
2196 | |
---|
2197 | /* |
---|
2198 | * Generate a PCI IRQ routing entry and program the IOAPIC accordingly. |
---|
2199 | * Note that we mask (disable) IRQs now -- these get enabled when the |
---|
2200 | * corresponding device driver registers for this IRQ. |
---|
2201 | */ |
---|
2202 | |
---|
2203 | memset(&entry,0,sizeof(entry)); |
---|
2204 | |
---|
2205 | entry.delivery_mode = INT_DELIVERY_MODE; |
---|
2206 | entry.dest_mode = INT_DEST_MODE; |
---|
2207 | entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS); |
---|
2208 | entry.trigger = edge_level; |
---|
2209 | entry.polarity = active_high_low; |
---|
2210 | entry.mask = 1; /* Disabled (masked) */ |
---|
2211 | |
---|
2212 | irq = gsi_irq_sharing(irq); |
---|
2213 | /* |
---|
2214 | * IRQs < 16 are already in the irq_2_pin[] map |
---|
2215 | */ |
---|
2216 | if (irq >= 16) |
---|
2217 | add_pin_to_irq(irq, ioapic, pin); |
---|
2218 | |
---|
2219 | entry.vector = assign_irq_vector(irq); |
---|
2220 | |
---|
2221 | apic_printk(APIC_VERBOSE,KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry (%d-%d -> 0x%x -> " |
---|
2222 | "IRQ %d Mode:%i Active:%i)\n", ioapic, |
---|
2223 | mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq, |
---|
2224 | edge_level, active_high_low); |
---|
2225 | |
---|
2226 | ioapic_register_intr(irq, entry.vector, edge_level); |
---|
2227 | |
---|
2228 | if (!ioapic && (irq < 16)) |
---|
2229 | disable_8259A_irq(irq); |
---|
2230 | |
---|
2231 | spin_lock_irqsave(&ioapic_lock, flags); |
---|
2232 | io_apic_write(ioapic, 0x11+2*pin, *(((int *)&entry)+1)); |
---|
2233 | io_apic_write(ioapic, 0x10+2*pin, *(((int *)&entry)+0)); |
---|
2234 | set_native_irq_info(use_pci_vector() ? entry.vector : irq, TARGET_CPUS); |
---|
2235 | spin_unlock_irqrestore(&ioapic_lock, flags); |
---|
2236 | |
---|
2237 | return 0; |
---|
2238 | } |
---|
2239 | |
---|
2240 | #endif /* CONFIG_ACPI */ |
---|
2241 | |
---|
2242 | |
---|
2243 | #ifndef CONFIG_XEN |
---|
2244 | /* |
---|
2245 | * This function currently is only a helper for the i386 smp boot process where |
---|
2246 | * we need to reprogram the ioredtbls to cater for the cpus which have come online |
---|
2247 | * so mask in all cases should simply be TARGET_CPUS |
---|
2248 | */ |
---|
2249 | #ifdef CONFIG_SMP |
---|
2250 | void __init setup_ioapic_dest(void) |
---|
2251 | { |
---|
2252 | int pin, ioapic, irq, irq_entry; |
---|
2253 | |
---|
2254 | if (skip_ioapic_setup == 1) |
---|
2255 | return; |
---|
2256 | |
---|
2257 | for (ioapic = 0; ioapic < nr_ioapics; ioapic++) { |
---|
2258 | for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) { |
---|
2259 | irq_entry = find_irq_entry(ioapic, pin, mp_INT); |
---|
2260 | if (irq_entry == -1) |
---|
2261 | continue; |
---|
2262 | irq = pin_2_irq(irq_entry, ioapic, pin); |
---|
2263 | set_ioapic_affinity_irq(irq, TARGET_CPUS); |
---|
2264 | } |
---|
2265 | |
---|
2266 | } |
---|
2267 | } |
---|
2268 | #endif |
---|
2269 | #endif /* !CONFIG_XEN */ |
---|