1 | /* |
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2 | * Intel IO-APIC support for multi-Pentium hosts. |
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3 | * |
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4 | * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo |
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5 | * |
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6 | * Many thanks to Stig Venaas for trying out countless experimental |
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7 | * patches and reporting/debugging problems patiently! |
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8 | * |
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9 | * (c) 1999, Multiple IO-APIC support, developed by |
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10 | * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and |
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11 | * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>, |
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12 | * further tested and cleaned up by Zach Brown <zab@redhat.com> |
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13 | * and Ingo Molnar <mingo@redhat.com> |
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14 | * |
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15 | * Fixes |
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16 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs; |
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17 | * thanks to Eric Gilmore |
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18 | * and Rolf G. Tews |
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19 | * for testing these extensively |
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20 | * Paul Diefenbaugh : Added full ACPI support |
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21 | */ |
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22 | |
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23 | #include <linux/mm.h> |
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24 | #include <linux/interrupt.h> |
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25 | #include <linux/init.h> |
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26 | #include <linux/delay.h> |
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27 | #include <linux/sched.h> |
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28 | #include <linux/smp_lock.h> |
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29 | #include <linux/mc146818rtc.h> |
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30 | #include <linux/compiler.h> |
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31 | #include <linux/acpi.h> |
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32 | #include <linux/module.h> |
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33 | #include <linux/sysdev.h> |
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34 | |
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35 | #include <asm/io.h> |
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36 | #include <asm/smp.h> |
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37 | #include <asm/desc.h> |
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38 | #include <asm/timer.h> |
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39 | #include <asm/i8259.h> |
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40 | #include <asm/nmi.h> |
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41 | |
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42 | #include <mach_apic.h> |
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43 | |
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44 | #include "io_ports.h" |
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45 | |
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46 | #ifdef CONFIG_XEN |
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47 | |
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48 | #include <xen/interface/xen.h> |
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49 | #include <xen/interface/physdev.h> |
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50 | |
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51 | /* Fake i8259 */ |
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52 | #define make_8259A_irq(_irq) (io_apic_irqs &= ~(1UL<<(_irq))) |
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53 | #define disable_8259A_irq(_irq) ((void)0) |
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54 | #define i8259A_irq_pending(_irq) (0) |
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55 | |
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56 | unsigned long io_apic_irqs; |
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57 | |
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58 | static inline unsigned int xen_io_apic_read(unsigned int apic, unsigned int reg) |
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59 | { |
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60 | struct physdev_apic apic_op; |
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61 | int ret; |
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62 | |
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63 | apic_op.apic_physbase = mp_ioapics[apic].mpc_apicaddr; |
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64 | apic_op.reg = reg; |
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65 | ret = HYPERVISOR_physdev_op(PHYSDEVOP_apic_read, &apic_op); |
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66 | if (ret) |
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67 | return ret; |
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68 | return apic_op.value; |
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69 | } |
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70 | |
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71 | static inline void xen_io_apic_write(unsigned int apic, unsigned int reg, unsigned int value) |
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72 | { |
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73 | struct physdev_apic apic_op; |
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74 | |
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75 | apic_op.apic_physbase = mp_ioapics[apic].mpc_apicaddr; |
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76 | apic_op.reg = reg; |
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77 | apic_op.value = value; |
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78 | HYPERVISOR_physdev_op(PHYSDEVOP_apic_write, &apic_op); |
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79 | } |
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80 | |
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81 | #define io_apic_read(a,r) xen_io_apic_read(a,r) |
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82 | #define io_apic_write(a,r,v) xen_io_apic_write(a,r,v) |
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83 | |
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84 | #endif /* CONFIG_XEN */ |
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85 | |
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86 | int (*ioapic_renumber_irq)(int ioapic, int irq); |
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87 | atomic_t irq_mis_count; |
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88 | |
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89 | /* Where if anywhere is the i8259 connect in external int mode */ |
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90 | static struct { int pin, apic; } ioapic_i8259 = { -1, -1 }; |
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91 | |
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92 | static DEFINE_SPINLOCK(ioapic_lock); |
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93 | static DEFINE_SPINLOCK(vector_lock); |
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94 | |
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95 | int timer_over_8254 __initdata = 1; |
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96 | |
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97 | /* |
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98 | * Is the SiS APIC rmw bug present ? |
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99 | * -1 = don't know, 0 = no, 1 = yes |
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100 | */ |
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101 | int sis_apic_bug = -1; |
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102 | |
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103 | /* |
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104 | * # of IRQ routing registers |
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105 | */ |
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106 | int nr_ioapic_registers[MAX_IO_APICS]; |
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107 | |
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108 | int disable_timer_pin_1 __initdata; |
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109 | |
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110 | /* |
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111 | * Rough estimation of how many shared IRQs there are, can |
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112 | * be changed anytime. |
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113 | */ |
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114 | #define MAX_PLUS_SHARED_IRQS NR_IRQS |
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115 | #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS) |
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116 | |
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117 | /* |
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118 | * This is performance-critical, we want to do it O(1) |
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119 | * |
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120 | * the indexing order of this array favors 1:1 mappings |
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121 | * between pins and IRQs. |
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122 | */ |
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123 | |
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124 | static struct irq_pin_list { |
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125 | int apic, pin, next; |
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126 | } irq_2_pin[PIN_MAP_SIZE]; |
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127 | |
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128 | int vector_irq[NR_VECTORS] __read_mostly = { [0 ... NR_VECTORS - 1] = -1}; |
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129 | #ifdef CONFIG_PCI_MSI |
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130 | #define vector_to_irq(vector) \ |
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131 | (platform_legacy_irq(vector) ? vector : vector_irq[vector]) |
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132 | #else |
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133 | #define vector_to_irq(vector) (vector) |
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134 | #endif |
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135 | |
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136 | /* |
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137 | * The common case is 1:1 IRQ<->pin mappings. Sometimes there are |
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138 | * shared ISA-space IRQs, so we have to support them. We are super |
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139 | * fast in the common case, and fast for shared ISA-space IRQs. |
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140 | */ |
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141 | static void add_pin_to_irq(unsigned int irq, int apic, int pin) |
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142 | { |
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143 | static int first_free_entry = NR_IRQS; |
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144 | struct irq_pin_list *entry = irq_2_pin + irq; |
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145 | |
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146 | while (entry->next) |
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147 | entry = irq_2_pin + entry->next; |
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148 | |
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149 | if (entry->pin != -1) { |
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150 | entry->next = first_free_entry; |
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151 | entry = irq_2_pin + entry->next; |
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152 | if (++first_free_entry >= PIN_MAP_SIZE) |
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153 | panic("io_apic.c: whoops"); |
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154 | } |
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155 | entry->apic = apic; |
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156 | entry->pin = pin; |
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157 | } |
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158 | |
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159 | #ifdef CONFIG_XEN |
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160 | #define clear_IO_APIC() ((void)0) |
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161 | #else |
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162 | /* |
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163 | * Reroute an IRQ to a different pin. |
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164 | */ |
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165 | static void __init replace_pin_at_irq(unsigned int irq, |
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166 | int oldapic, int oldpin, |
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167 | int newapic, int newpin) |
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168 | { |
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169 | struct irq_pin_list *entry = irq_2_pin + irq; |
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170 | |
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171 | while (1) { |
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172 | if (entry->apic == oldapic && entry->pin == oldpin) { |
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173 | entry->apic = newapic; |
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174 | entry->pin = newpin; |
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175 | } |
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176 | if (!entry->next) |
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177 | break; |
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178 | entry = irq_2_pin + entry->next; |
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179 | } |
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180 | } |
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181 | |
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182 | static void __modify_IO_APIC_irq (unsigned int irq, unsigned long enable, unsigned long disable) |
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183 | { |
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184 | struct irq_pin_list *entry = irq_2_pin + irq; |
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185 | unsigned int pin, reg; |
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186 | |
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187 | for (;;) { |
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188 | pin = entry->pin; |
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189 | if (pin == -1) |
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190 | break; |
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191 | reg = io_apic_read(entry->apic, 0x10 + pin*2); |
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192 | reg &= ~disable; |
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193 | reg |= enable; |
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194 | io_apic_modify(entry->apic, 0x10 + pin*2, reg); |
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195 | if (!entry->next) |
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196 | break; |
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197 | entry = irq_2_pin + entry->next; |
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198 | } |
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199 | } |
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200 | |
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201 | /* mask = 1 */ |
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202 | static void __mask_IO_APIC_irq (unsigned int irq) |
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203 | { |
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204 | __modify_IO_APIC_irq(irq, 0x00010000, 0); |
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205 | } |
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206 | |
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207 | /* mask = 0 */ |
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208 | static void __unmask_IO_APIC_irq (unsigned int irq) |
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209 | { |
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210 | __modify_IO_APIC_irq(irq, 0, 0x00010000); |
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211 | } |
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212 | |
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213 | /* mask = 1, trigger = 0 */ |
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214 | static void __mask_and_edge_IO_APIC_irq (unsigned int irq) |
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215 | { |
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216 | __modify_IO_APIC_irq(irq, 0x00010000, 0x00008000); |
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217 | } |
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218 | |
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219 | /* mask = 0, trigger = 1 */ |
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220 | static void __unmask_and_level_IO_APIC_irq (unsigned int irq) |
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221 | { |
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222 | __modify_IO_APIC_irq(irq, 0x00008000, 0x00010000); |
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223 | } |
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224 | |
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225 | static void mask_IO_APIC_irq (unsigned int irq) |
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226 | { |
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227 | unsigned long flags; |
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228 | |
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229 | spin_lock_irqsave(&ioapic_lock, flags); |
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230 | __mask_IO_APIC_irq(irq); |
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231 | spin_unlock_irqrestore(&ioapic_lock, flags); |
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232 | } |
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233 | |
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234 | static void unmask_IO_APIC_irq (unsigned int irq) |
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235 | { |
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236 | unsigned long flags; |
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237 | |
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238 | spin_lock_irqsave(&ioapic_lock, flags); |
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239 | __unmask_IO_APIC_irq(irq); |
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240 | spin_unlock_irqrestore(&ioapic_lock, flags); |
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241 | } |
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242 | |
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243 | static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin) |
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244 | { |
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245 | struct IO_APIC_route_entry entry; |
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246 | unsigned long flags; |
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247 | |
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248 | /* Check delivery_mode to be sure we're not clearing an SMI pin */ |
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249 | spin_lock_irqsave(&ioapic_lock, flags); |
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250 | *(((int*)&entry) + 0) = io_apic_read(apic, 0x10 + 2 * pin); |
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251 | *(((int*)&entry) + 1) = io_apic_read(apic, 0x11 + 2 * pin); |
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252 | spin_unlock_irqrestore(&ioapic_lock, flags); |
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253 | if (entry.delivery_mode == dest_SMI) |
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254 | return; |
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255 | |
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256 | /* |
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257 | * Disable it in the IO-APIC irq-routing table: |
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258 | */ |
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259 | memset(&entry, 0, sizeof(entry)); |
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260 | entry.mask = 1; |
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261 | spin_lock_irqsave(&ioapic_lock, flags); |
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262 | io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry) + 0)); |
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263 | io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry) + 1)); |
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264 | spin_unlock_irqrestore(&ioapic_lock, flags); |
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265 | } |
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266 | |
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267 | static void clear_IO_APIC (void) |
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268 | { |
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269 | int apic, pin; |
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270 | |
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271 | for (apic = 0; apic < nr_ioapics; apic++) |
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272 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) |
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273 | clear_IO_APIC_pin(apic, pin); |
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274 | } |
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275 | |
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276 | #ifdef CONFIG_SMP |
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277 | static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t cpumask) |
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278 | { |
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279 | unsigned long flags; |
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280 | int pin; |
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281 | struct irq_pin_list *entry = irq_2_pin + irq; |
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282 | unsigned int apicid_value; |
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283 | cpumask_t tmp; |
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284 | |
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285 | cpus_and(tmp, cpumask, cpu_online_map); |
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286 | if (cpus_empty(tmp)) |
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287 | tmp = TARGET_CPUS; |
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288 | |
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289 | cpus_and(cpumask, tmp, CPU_MASK_ALL); |
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290 | |
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291 | apicid_value = cpu_mask_to_apicid(cpumask); |
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292 | /* Prepare to do the io_apic_write */ |
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293 | apicid_value = apicid_value << 24; |
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294 | spin_lock_irqsave(&ioapic_lock, flags); |
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295 | for (;;) { |
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296 | pin = entry->pin; |
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297 | if (pin == -1) |
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298 | break; |
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299 | io_apic_write(entry->apic, 0x10 + 1 + pin*2, apicid_value); |
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300 | if (!entry->next) |
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301 | break; |
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302 | entry = irq_2_pin + entry->next; |
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303 | } |
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304 | set_irq_info(irq, cpumask); |
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305 | spin_unlock_irqrestore(&ioapic_lock, flags); |
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306 | } |
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307 | |
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308 | #if defined(CONFIG_IRQBALANCE) |
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309 | # include <asm/processor.h> /* kernel_thread() */ |
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310 | # include <linux/kernel_stat.h> /* kstat */ |
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311 | # include <linux/slab.h> /* kmalloc() */ |
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312 | # include <linux/timer.h> /* time_after() */ |
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313 | |
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314 | #ifdef CONFIG_BALANCED_IRQ_DEBUG |
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315 | # define TDprintk(x...) do { printk("<%ld:%s:%d>: ", jiffies, __FILE__, __LINE__); printk(x); } while (0) |
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316 | # define Dprintk(x...) do { TDprintk(x); } while (0) |
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317 | # else |
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318 | # define TDprintk(x...) |
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319 | # define Dprintk(x...) |
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320 | # endif |
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321 | |
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322 | #define IRQBALANCE_CHECK_ARCH -999 |
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323 | #define MAX_BALANCED_IRQ_INTERVAL (5*HZ) |
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324 | #define MIN_BALANCED_IRQ_INTERVAL (HZ/2) |
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325 | #define BALANCED_IRQ_MORE_DELTA (HZ/10) |
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326 | #define BALANCED_IRQ_LESS_DELTA (HZ) |
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327 | |
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328 | static int irqbalance_disabled __read_mostly = IRQBALANCE_CHECK_ARCH; |
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329 | static int physical_balance __read_mostly; |
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330 | static long balanced_irq_interval __read_mostly = MAX_BALANCED_IRQ_INTERVAL; |
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331 | |
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332 | static struct irq_cpu_info { |
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333 | unsigned long * last_irq; |
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334 | unsigned long * irq_delta; |
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335 | unsigned long irq; |
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336 | } irq_cpu_data[NR_CPUS]; |
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337 | |
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338 | #define CPU_IRQ(cpu) (irq_cpu_data[cpu].irq) |
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339 | #define LAST_CPU_IRQ(cpu,irq) (irq_cpu_data[cpu].last_irq[irq]) |
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340 | #define IRQ_DELTA(cpu,irq) (irq_cpu_data[cpu].irq_delta[irq]) |
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341 | |
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342 | #define IDLE_ENOUGH(cpu,now) \ |
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343 | (idle_cpu(cpu) && ((now) - per_cpu(irq_stat, (cpu)).idle_timestamp > 1)) |
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344 | |
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345 | #define IRQ_ALLOWED(cpu, allowed_mask) cpu_isset(cpu, allowed_mask) |
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346 | |
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347 | #define CPU_TO_PACKAGEINDEX(i) (first_cpu(cpu_sibling_map[i])) |
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348 | |
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349 | static cpumask_t balance_irq_affinity[NR_IRQS] = { |
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350 | [0 ... NR_IRQS-1] = CPU_MASK_ALL |
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351 | }; |
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352 | |
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353 | void set_balance_irq_affinity(unsigned int irq, cpumask_t mask) |
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354 | { |
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355 | balance_irq_affinity[irq] = mask; |
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356 | } |
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357 | |
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358 | static unsigned long move(int curr_cpu, cpumask_t allowed_mask, |
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359 | unsigned long now, int direction) |
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360 | { |
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361 | int search_idle = 1; |
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362 | int cpu = curr_cpu; |
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363 | |
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364 | goto inside; |
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365 | |
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366 | do { |
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367 | if (unlikely(cpu == curr_cpu)) |
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368 | search_idle = 0; |
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369 | inside: |
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370 | if (direction == 1) { |
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371 | cpu++; |
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372 | if (cpu >= NR_CPUS) |
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373 | cpu = 0; |
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374 | } else { |
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375 | cpu--; |
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376 | if (cpu == -1) |
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377 | cpu = NR_CPUS-1; |
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378 | } |
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379 | } while (!cpu_online(cpu) || !IRQ_ALLOWED(cpu,allowed_mask) || |
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380 | (search_idle && !IDLE_ENOUGH(cpu,now))); |
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381 | |
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382 | return cpu; |
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383 | } |
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384 | |
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385 | static inline void balance_irq(int cpu, int irq) |
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386 | { |
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387 | unsigned long now = jiffies; |
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388 | cpumask_t allowed_mask; |
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389 | unsigned int new_cpu; |
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390 | |
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391 | if (irqbalance_disabled) |
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392 | return; |
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393 | |
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394 | cpus_and(allowed_mask, cpu_online_map, balance_irq_affinity[irq]); |
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395 | new_cpu = move(cpu, allowed_mask, now, 1); |
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396 | if (cpu != new_cpu) { |
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397 | set_pending_irq(irq, cpumask_of_cpu(new_cpu)); |
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398 | } |
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399 | } |
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400 | |
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401 | static inline void rotate_irqs_among_cpus(unsigned long useful_load_threshold) |
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402 | { |
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403 | int i, j; |
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404 | Dprintk("Rotating IRQs among CPUs.\n"); |
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405 | for_each_online_cpu(i) { |
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406 | for (j = 0; j < NR_IRQS; j++) { |
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407 | if (!irq_desc[j].action) |
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408 | continue; |
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409 | /* Is it a significant load ? */ |
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410 | if (IRQ_DELTA(CPU_TO_PACKAGEINDEX(i),j) < |
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411 | useful_load_threshold) |
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412 | continue; |
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413 | balance_irq(i, j); |
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414 | } |
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415 | } |
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416 | balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL, |
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417 | balanced_irq_interval - BALANCED_IRQ_LESS_DELTA); |
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418 | return; |
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419 | } |
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420 | |
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421 | static void do_irq_balance(void) |
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422 | { |
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423 | int i, j; |
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424 | unsigned long max_cpu_irq = 0, min_cpu_irq = (~0); |
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425 | unsigned long move_this_load = 0; |
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426 | int max_loaded = 0, min_loaded = 0; |
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427 | int load; |
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428 | unsigned long useful_load_threshold = balanced_irq_interval + 10; |
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429 | int selected_irq; |
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430 | int tmp_loaded, first_attempt = 1; |
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431 | unsigned long tmp_cpu_irq; |
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432 | unsigned long imbalance = 0; |
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433 | cpumask_t allowed_mask, target_cpu_mask, tmp; |
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434 | |
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435 | for_each_possible_cpu(i) { |
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436 | int package_index; |
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437 | CPU_IRQ(i) = 0; |
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438 | if (!cpu_online(i)) |
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439 | continue; |
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440 | package_index = CPU_TO_PACKAGEINDEX(i); |
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441 | for (j = 0; j < NR_IRQS; j++) { |
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442 | unsigned long value_now, delta; |
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443 | /* Is this an active IRQ? */ |
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444 | if (!irq_desc[j].action) |
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445 | continue; |
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446 | if ( package_index == i ) |
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447 | IRQ_DELTA(package_index,j) = 0; |
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448 | /* Determine the total count per processor per IRQ */ |
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449 | value_now = (unsigned long) kstat_cpu(i).irqs[j]; |
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450 | |
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451 | /* Determine the activity per processor per IRQ */ |
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452 | delta = value_now - LAST_CPU_IRQ(i,j); |
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453 | |
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454 | /* Update last_cpu_irq[][] for the next time */ |
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455 | LAST_CPU_IRQ(i,j) = value_now; |
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456 | |
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457 | /* Ignore IRQs whose rate is less than the clock */ |
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458 | if (delta < useful_load_threshold) |
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459 | continue; |
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460 | /* update the load for the processor or package total */ |
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461 | IRQ_DELTA(package_index,j) += delta; |
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462 | |
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463 | /* Keep track of the higher numbered sibling as well */ |
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464 | if (i != package_index) |
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465 | CPU_IRQ(i) += delta; |
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466 | /* |
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467 | * We have sibling A and sibling B in the package |
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468 | * |
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469 | * cpu_irq[A] = load for cpu A + load for cpu B |
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470 | * cpu_irq[B] = load for cpu B |
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471 | */ |
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472 | CPU_IRQ(package_index) += delta; |
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473 | } |
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474 | } |
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475 | /* Find the least loaded processor package */ |
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476 | for_each_online_cpu(i) { |
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477 | if (i != CPU_TO_PACKAGEINDEX(i)) |
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478 | continue; |
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479 | if (min_cpu_irq > CPU_IRQ(i)) { |
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480 | min_cpu_irq = CPU_IRQ(i); |
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481 | min_loaded = i; |
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482 | } |
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483 | } |
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484 | max_cpu_irq = ULONG_MAX; |
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485 | |
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486 | tryanothercpu: |
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487 | /* Look for heaviest loaded processor. |
---|
488 | * We may come back to get the next heaviest loaded processor. |
---|
489 | * Skip processors with trivial loads. |
---|
490 | */ |
---|
491 | tmp_cpu_irq = 0; |
---|
492 | tmp_loaded = -1; |
---|
493 | for_each_online_cpu(i) { |
---|
494 | if (i != CPU_TO_PACKAGEINDEX(i)) |
---|
495 | continue; |
---|
496 | if (max_cpu_irq <= CPU_IRQ(i)) |
---|
497 | continue; |
---|
498 | if (tmp_cpu_irq < CPU_IRQ(i)) { |
---|
499 | tmp_cpu_irq = CPU_IRQ(i); |
---|
500 | tmp_loaded = i; |
---|
501 | } |
---|
502 | } |
---|
503 | |
---|
504 | if (tmp_loaded == -1) { |
---|
505 | /* In the case of small number of heavy interrupt sources, |
---|
506 | * loading some of the cpus too much. We use Ingo's original |
---|
507 | * approach to rotate them around. |
---|
508 | */ |
---|
509 | if (!first_attempt && imbalance >= useful_load_threshold) { |
---|
510 | rotate_irqs_among_cpus(useful_load_threshold); |
---|
511 | return; |
---|
512 | } |
---|
513 | goto not_worth_the_effort; |
---|
514 | } |
---|
515 | |
---|
516 | first_attempt = 0; /* heaviest search */ |
---|
517 | max_cpu_irq = tmp_cpu_irq; /* load */ |
---|
518 | max_loaded = tmp_loaded; /* processor */ |
---|
519 | imbalance = (max_cpu_irq - min_cpu_irq) / 2; |
---|
520 | |
---|
521 | Dprintk("max_loaded cpu = %d\n", max_loaded); |
---|
522 | Dprintk("min_loaded cpu = %d\n", min_loaded); |
---|
523 | Dprintk("max_cpu_irq load = %ld\n", max_cpu_irq); |
---|
524 | Dprintk("min_cpu_irq load = %ld\n", min_cpu_irq); |
---|
525 | Dprintk("load imbalance = %lu\n", imbalance); |
---|
526 | |
---|
527 | /* if imbalance is less than approx 10% of max load, then |
---|
528 | * observe diminishing returns action. - quit |
---|
529 | */ |
---|
530 | if (imbalance < (max_cpu_irq >> 3)) { |
---|
531 | Dprintk("Imbalance too trivial\n"); |
---|
532 | goto not_worth_the_effort; |
---|
533 | } |
---|
534 | |
---|
535 | tryanotherirq: |
---|
536 | /* if we select an IRQ to move that can't go where we want, then |
---|
537 | * see if there is another one to try. |
---|
538 | */ |
---|
539 | move_this_load = 0; |
---|
540 | selected_irq = -1; |
---|
541 | for (j = 0; j < NR_IRQS; j++) { |
---|
542 | /* Is this an active IRQ? */ |
---|
543 | if (!irq_desc[j].action) |
---|
544 | continue; |
---|
545 | if (imbalance <= IRQ_DELTA(max_loaded,j)) |
---|
546 | continue; |
---|
547 | /* Try to find the IRQ that is closest to the imbalance |
---|
548 | * without going over. |
---|
549 | */ |
---|
550 | if (move_this_load < IRQ_DELTA(max_loaded,j)) { |
---|
551 | move_this_load = IRQ_DELTA(max_loaded,j); |
---|
552 | selected_irq = j; |
---|
553 | } |
---|
554 | } |
---|
555 | if (selected_irq == -1) { |
---|
556 | goto tryanothercpu; |
---|
557 | } |
---|
558 | |
---|
559 | imbalance = move_this_load; |
---|
560 | |
---|
561 | /* For physical_balance case, we accumlated both load |
---|
562 | * values in the one of the siblings cpu_irq[], |
---|
563 | * to use the same code for physical and logical processors |
---|
564 | * as much as possible. |
---|
565 | * |
---|
566 | * NOTE: the cpu_irq[] array holds the sum of the load for |
---|
567 | * sibling A and sibling B in the slot for the lowest numbered |
---|
568 | * sibling (A), _AND_ the load for sibling B in the slot for |
---|
569 | * the higher numbered sibling. |
---|
570 | * |
---|
571 | * We seek the least loaded sibling by making the comparison |
---|
572 | * (A+B)/2 vs B |
---|
573 | */ |
---|
574 | load = CPU_IRQ(min_loaded) >> 1; |
---|
575 | for_each_cpu_mask(j, cpu_sibling_map[min_loaded]) { |
---|
576 | if (load > CPU_IRQ(j)) { |
---|
577 | /* This won't change cpu_sibling_map[min_loaded] */ |
---|
578 | load = CPU_IRQ(j); |
---|
579 | min_loaded = j; |
---|
580 | } |
---|
581 | } |
---|
582 | |
---|
583 | cpus_and(allowed_mask, |
---|
584 | cpu_online_map, |
---|
585 | balance_irq_affinity[selected_irq]); |
---|
586 | target_cpu_mask = cpumask_of_cpu(min_loaded); |
---|
587 | cpus_and(tmp, target_cpu_mask, allowed_mask); |
---|
588 | |
---|
589 | if (!cpus_empty(tmp)) { |
---|
590 | |
---|
591 | Dprintk("irq = %d moved to cpu = %d\n", |
---|
592 | selected_irq, min_loaded); |
---|
593 | /* mark for change destination */ |
---|
594 | set_pending_irq(selected_irq, cpumask_of_cpu(min_loaded)); |
---|
595 | |
---|
596 | /* Since we made a change, come back sooner to |
---|
597 | * check for more variation. |
---|
598 | */ |
---|
599 | balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL, |
---|
600 | balanced_irq_interval - BALANCED_IRQ_LESS_DELTA); |
---|
601 | return; |
---|
602 | } |
---|
603 | goto tryanotherirq; |
---|
604 | |
---|
605 | not_worth_the_effort: |
---|
606 | /* |
---|
607 | * if we did not find an IRQ to move, then adjust the time interval |
---|
608 | * upward |
---|
609 | */ |
---|
610 | balanced_irq_interval = min((long)MAX_BALANCED_IRQ_INTERVAL, |
---|
611 | balanced_irq_interval + BALANCED_IRQ_MORE_DELTA); |
---|
612 | Dprintk("IRQ worth rotating not found\n"); |
---|
613 | return; |
---|
614 | } |
---|
615 | |
---|
616 | static int balanced_irq(void *unused) |
---|
617 | { |
---|
618 | int i; |
---|
619 | unsigned long prev_balance_time = jiffies; |
---|
620 | long time_remaining = balanced_irq_interval; |
---|
621 | |
---|
622 | daemonize("kirqd"); |
---|
623 | |
---|
624 | /* push everything to CPU 0 to give us a starting point. */ |
---|
625 | for (i = 0 ; i < NR_IRQS ; i++) { |
---|
626 | irq_desc[i].pending_mask = cpumask_of_cpu(0); |
---|
627 | set_pending_irq(i, cpumask_of_cpu(0)); |
---|
628 | } |
---|
629 | |
---|
630 | for ( ; ; ) { |
---|
631 | time_remaining = schedule_timeout_interruptible(time_remaining); |
---|
632 | try_to_freeze(); |
---|
633 | if (time_after(jiffies, |
---|
634 | prev_balance_time+balanced_irq_interval)) { |
---|
635 | preempt_disable(); |
---|
636 | do_irq_balance(); |
---|
637 | prev_balance_time = jiffies; |
---|
638 | time_remaining = balanced_irq_interval; |
---|
639 | preempt_enable(); |
---|
640 | } |
---|
641 | } |
---|
642 | return 0; |
---|
643 | } |
---|
644 | |
---|
645 | static int __init balanced_irq_init(void) |
---|
646 | { |
---|
647 | int i; |
---|
648 | struct cpuinfo_x86 *c; |
---|
649 | cpumask_t tmp; |
---|
650 | |
---|
651 | cpus_shift_right(tmp, cpu_online_map, 2); |
---|
652 | c = &boot_cpu_data; |
---|
653 | /* When not overwritten by the command line ask subarchitecture. */ |
---|
654 | if (irqbalance_disabled == IRQBALANCE_CHECK_ARCH) |
---|
655 | irqbalance_disabled = NO_BALANCE_IRQ; |
---|
656 | if (irqbalance_disabled) |
---|
657 | return 0; |
---|
658 | |
---|
659 | /* disable irqbalance completely if there is only one processor online */ |
---|
660 | if (num_online_cpus() < 2) { |
---|
661 | irqbalance_disabled = 1; |
---|
662 | return 0; |
---|
663 | } |
---|
664 | /* |
---|
665 | * Enable physical balance only if more than 1 physical processor |
---|
666 | * is present |
---|
667 | */ |
---|
668 | if (smp_num_siblings > 1 && !cpus_empty(tmp)) |
---|
669 | physical_balance = 1; |
---|
670 | |
---|
671 | for_each_online_cpu(i) { |
---|
672 | irq_cpu_data[i].irq_delta = kmalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL); |
---|
673 | irq_cpu_data[i].last_irq = kmalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL); |
---|
674 | if (irq_cpu_data[i].irq_delta == NULL || irq_cpu_data[i].last_irq == NULL) { |
---|
675 | printk(KERN_ERR "balanced_irq_init: out of memory"); |
---|
676 | goto failed; |
---|
677 | } |
---|
678 | memset(irq_cpu_data[i].irq_delta,0,sizeof(unsigned long) * NR_IRQS); |
---|
679 | memset(irq_cpu_data[i].last_irq,0,sizeof(unsigned long) * NR_IRQS); |
---|
680 | } |
---|
681 | |
---|
682 | printk(KERN_INFO "Starting balanced_irq\n"); |
---|
683 | if (kernel_thread(balanced_irq, NULL, CLONE_KERNEL) >= 0) |
---|
684 | return 0; |
---|
685 | else |
---|
686 | printk(KERN_ERR "balanced_irq_init: failed to spawn balanced_irq"); |
---|
687 | failed: |
---|
688 | for_each_possible_cpu(i) { |
---|
689 | kfree(irq_cpu_data[i].irq_delta); |
---|
690 | irq_cpu_data[i].irq_delta = NULL; |
---|
691 | kfree(irq_cpu_data[i].last_irq); |
---|
692 | irq_cpu_data[i].last_irq = NULL; |
---|
693 | } |
---|
694 | return 0; |
---|
695 | } |
---|
696 | |
---|
697 | int __init irqbalance_disable(char *str) |
---|
698 | { |
---|
699 | irqbalance_disabled = 1; |
---|
700 | return 1; |
---|
701 | } |
---|
702 | |
---|
703 | __setup("noirqbalance", irqbalance_disable); |
---|
704 | |
---|
705 | late_initcall(balanced_irq_init); |
---|
706 | #endif /* CONFIG_IRQBALANCE */ |
---|
707 | #endif /* CONFIG_SMP */ |
---|
708 | #endif |
---|
709 | |
---|
710 | #ifndef CONFIG_SMP |
---|
711 | void fastcall send_IPI_self(int vector) |
---|
712 | { |
---|
713 | #ifndef CONFIG_XEN |
---|
714 | unsigned int cfg; |
---|
715 | |
---|
716 | /* |
---|
717 | * Wait for idle. |
---|
718 | */ |
---|
719 | apic_wait_icr_idle(); |
---|
720 | cfg = APIC_DM_FIXED | APIC_DEST_SELF | vector | APIC_DEST_LOGICAL; |
---|
721 | /* |
---|
722 | * Send the IPI. The write to APIC_ICR fires this off. |
---|
723 | */ |
---|
724 | apic_write_around(APIC_ICR, cfg); |
---|
725 | #endif |
---|
726 | } |
---|
727 | #endif /* !CONFIG_SMP */ |
---|
728 | |
---|
729 | |
---|
730 | /* |
---|
731 | * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to |
---|
732 | * specific CPU-side IRQs. |
---|
733 | */ |
---|
734 | |
---|
735 | #define MAX_PIRQS 8 |
---|
736 | static int pirq_entries [MAX_PIRQS]; |
---|
737 | static int pirqs_enabled; |
---|
738 | int skip_ioapic_setup; |
---|
739 | |
---|
740 | static int __init ioapic_setup(char *str) |
---|
741 | { |
---|
742 | skip_ioapic_setup = 1; |
---|
743 | return 1; |
---|
744 | } |
---|
745 | |
---|
746 | __setup("noapic", ioapic_setup); |
---|
747 | |
---|
748 | static int __init ioapic_pirq_setup(char *str) |
---|
749 | { |
---|
750 | int i, max; |
---|
751 | int ints[MAX_PIRQS+1]; |
---|
752 | |
---|
753 | get_options(str, ARRAY_SIZE(ints), ints); |
---|
754 | |
---|
755 | for (i = 0; i < MAX_PIRQS; i++) |
---|
756 | pirq_entries[i] = -1; |
---|
757 | |
---|
758 | pirqs_enabled = 1; |
---|
759 | apic_printk(APIC_VERBOSE, KERN_INFO |
---|
760 | "PIRQ redirection, working around broken MP-BIOS.\n"); |
---|
761 | max = MAX_PIRQS; |
---|
762 | if (ints[0] < MAX_PIRQS) |
---|
763 | max = ints[0]; |
---|
764 | |
---|
765 | for (i = 0; i < max; i++) { |
---|
766 | apic_printk(APIC_VERBOSE, KERN_DEBUG |
---|
767 | "... PIRQ%d -> IRQ %d\n", i, ints[i+1]); |
---|
768 | /* |
---|
769 | * PIRQs are mapped upside down, usually. |
---|
770 | */ |
---|
771 | pirq_entries[MAX_PIRQS-i-1] = ints[i+1]; |
---|
772 | } |
---|
773 | return 1; |
---|
774 | } |
---|
775 | |
---|
776 | __setup("pirq=", ioapic_pirq_setup); |
---|
777 | |
---|
778 | /* |
---|
779 | * Find the IRQ entry number of a certain pin. |
---|
780 | */ |
---|
781 | static int find_irq_entry(int apic, int pin, int type) |
---|
782 | { |
---|
783 | int i; |
---|
784 | |
---|
785 | for (i = 0; i < mp_irq_entries; i++) |
---|
786 | if (mp_irqs[i].mpc_irqtype == type && |
---|
787 | (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid || |
---|
788 | mp_irqs[i].mpc_dstapic == MP_APIC_ALL) && |
---|
789 | mp_irqs[i].mpc_dstirq == pin) |
---|
790 | return i; |
---|
791 | |
---|
792 | return -1; |
---|
793 | } |
---|
794 | |
---|
795 | /* |
---|
796 | * Find the pin to which IRQ[irq] (ISA) is connected |
---|
797 | */ |
---|
798 | static int __init find_isa_irq_pin(int irq, int type) |
---|
799 | { |
---|
800 | int i; |
---|
801 | |
---|
802 | for (i = 0; i < mp_irq_entries; i++) { |
---|
803 | int lbus = mp_irqs[i].mpc_srcbus; |
---|
804 | |
---|
805 | if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA || |
---|
806 | mp_bus_id_to_type[lbus] == MP_BUS_EISA || |
---|
807 | mp_bus_id_to_type[lbus] == MP_BUS_MCA || |
---|
808 | mp_bus_id_to_type[lbus] == MP_BUS_NEC98 |
---|
809 | ) && |
---|
810 | (mp_irqs[i].mpc_irqtype == type) && |
---|
811 | (mp_irqs[i].mpc_srcbusirq == irq)) |
---|
812 | |
---|
813 | return mp_irqs[i].mpc_dstirq; |
---|
814 | } |
---|
815 | return -1; |
---|
816 | } |
---|
817 | |
---|
818 | static int __init find_isa_irq_apic(int irq, int type) |
---|
819 | { |
---|
820 | int i; |
---|
821 | |
---|
822 | for (i = 0; i < mp_irq_entries; i++) { |
---|
823 | int lbus = mp_irqs[i].mpc_srcbus; |
---|
824 | |
---|
825 | if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA || |
---|
826 | mp_bus_id_to_type[lbus] == MP_BUS_EISA || |
---|
827 | mp_bus_id_to_type[lbus] == MP_BUS_MCA || |
---|
828 | mp_bus_id_to_type[lbus] == MP_BUS_NEC98 |
---|
829 | ) && |
---|
830 | (mp_irqs[i].mpc_irqtype == type) && |
---|
831 | (mp_irqs[i].mpc_srcbusirq == irq)) |
---|
832 | break; |
---|
833 | } |
---|
834 | if (i < mp_irq_entries) { |
---|
835 | int apic; |
---|
836 | for(apic = 0; apic < nr_ioapics; apic++) { |
---|
837 | if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic) |
---|
838 | return apic; |
---|
839 | } |
---|
840 | } |
---|
841 | |
---|
842 | return -1; |
---|
843 | } |
---|
844 | |
---|
845 | /* |
---|
846 | * Find a specific PCI IRQ entry. |
---|
847 | * Not an __init, possibly needed by modules |
---|
848 | */ |
---|
849 | static int pin_2_irq(int idx, int apic, int pin); |
---|
850 | |
---|
851 | int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin) |
---|
852 | { |
---|
853 | int apic, i, best_guess = -1; |
---|
854 | |
---|
855 | apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, " |
---|
856 | "slot:%d, pin:%d.\n", bus, slot, pin); |
---|
857 | if (mp_bus_id_to_pci_bus[bus] == -1) { |
---|
858 | printk(KERN_WARNING "PCI BIOS passed nonexistent PCI bus %d!\n", bus); |
---|
859 | return -1; |
---|
860 | } |
---|
861 | for (i = 0; i < mp_irq_entries; i++) { |
---|
862 | int lbus = mp_irqs[i].mpc_srcbus; |
---|
863 | |
---|
864 | for (apic = 0; apic < nr_ioapics; apic++) |
---|
865 | if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic || |
---|
866 | mp_irqs[i].mpc_dstapic == MP_APIC_ALL) |
---|
867 | break; |
---|
868 | |
---|
869 | if ((mp_bus_id_to_type[lbus] == MP_BUS_PCI) && |
---|
870 | !mp_irqs[i].mpc_irqtype && |
---|
871 | (bus == lbus) && |
---|
872 | (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) { |
---|
873 | int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq); |
---|
874 | |
---|
875 | if (!(apic || IO_APIC_IRQ(irq))) |
---|
876 | continue; |
---|
877 | |
---|
878 | if (pin == (mp_irqs[i].mpc_srcbusirq & 3)) |
---|
879 | return irq; |
---|
880 | /* |
---|
881 | * Use the first all-but-pin matching entry as a |
---|
882 | * best-guess fuzzy result for broken mptables. |
---|
883 | */ |
---|
884 | if (best_guess < 0) |
---|
885 | best_guess = irq; |
---|
886 | } |
---|
887 | } |
---|
888 | return best_guess; |
---|
889 | } |
---|
890 | EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector); |
---|
891 | |
---|
892 | /* |
---|
893 | * This function currently is only a helper for the i386 smp boot process where |
---|
894 | * we need to reprogram the ioredtbls to cater for the cpus which have come online |
---|
895 | * so mask in all cases should simply be TARGET_CPUS |
---|
896 | */ |
---|
897 | #ifdef CONFIG_SMP |
---|
898 | #ifndef CONFIG_XEN |
---|
899 | void __init setup_ioapic_dest(void) |
---|
900 | { |
---|
901 | int pin, ioapic, irq, irq_entry; |
---|
902 | |
---|
903 | if (skip_ioapic_setup == 1) |
---|
904 | return; |
---|
905 | |
---|
906 | for (ioapic = 0; ioapic < nr_ioapics; ioapic++) { |
---|
907 | for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) { |
---|
908 | irq_entry = find_irq_entry(ioapic, pin, mp_INT); |
---|
909 | if (irq_entry == -1) |
---|
910 | continue; |
---|
911 | irq = pin_2_irq(irq_entry, ioapic, pin); |
---|
912 | set_ioapic_affinity_irq(irq, TARGET_CPUS); |
---|
913 | } |
---|
914 | |
---|
915 | } |
---|
916 | } |
---|
917 | #endif /* !CONFIG_XEN */ |
---|
918 | #endif |
---|
919 | |
---|
920 | /* |
---|
921 | * EISA Edge/Level control register, ELCR |
---|
922 | */ |
---|
923 | static int EISA_ELCR(unsigned int irq) |
---|
924 | { |
---|
925 | if (irq < 16) { |
---|
926 | unsigned int port = 0x4d0 + (irq >> 3); |
---|
927 | return (inb(port) >> (irq & 7)) & 1; |
---|
928 | } |
---|
929 | apic_printk(APIC_VERBOSE, KERN_INFO |
---|
930 | "Broken MPtable reports ISA irq %d\n", irq); |
---|
931 | return 0; |
---|
932 | } |
---|
933 | |
---|
934 | /* EISA interrupts are always polarity zero and can be edge or level |
---|
935 | * trigger depending on the ELCR value. If an interrupt is listed as |
---|
936 | * EISA conforming in the MP table, that means its trigger type must |
---|
937 | * be read in from the ELCR */ |
---|
938 | |
---|
939 | #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].mpc_srcbusirq)) |
---|
940 | #define default_EISA_polarity(idx) (0) |
---|
941 | |
---|
942 | /* ISA interrupts are always polarity zero edge triggered, |
---|
943 | * when listed as conforming in the MP table. */ |
---|
944 | |
---|
945 | #define default_ISA_trigger(idx) (0) |
---|
946 | #define default_ISA_polarity(idx) (0) |
---|
947 | |
---|
948 | /* PCI interrupts are always polarity one level triggered, |
---|
949 | * when listed as conforming in the MP table. */ |
---|
950 | |
---|
951 | #define default_PCI_trigger(idx) (1) |
---|
952 | #define default_PCI_polarity(idx) (1) |
---|
953 | |
---|
954 | /* MCA interrupts are always polarity zero level triggered, |
---|
955 | * when listed as conforming in the MP table. */ |
---|
956 | |
---|
957 | #define default_MCA_trigger(idx) (1) |
---|
958 | #define default_MCA_polarity(idx) (0) |
---|
959 | |
---|
960 | /* NEC98 interrupts are always polarity zero edge triggered, |
---|
961 | * when listed as conforming in the MP table. */ |
---|
962 | |
---|
963 | #define default_NEC98_trigger(idx) (0) |
---|
964 | #define default_NEC98_polarity(idx) (0) |
---|
965 | |
---|
966 | static int __init MPBIOS_polarity(int idx) |
---|
967 | { |
---|
968 | int bus = mp_irqs[idx].mpc_srcbus; |
---|
969 | int polarity; |
---|
970 | |
---|
971 | /* |
---|
972 | * Determine IRQ line polarity (high active or low active): |
---|
973 | */ |
---|
974 | switch (mp_irqs[idx].mpc_irqflag & 3) |
---|
975 | { |
---|
976 | case 0: /* conforms, ie. bus-type dependent polarity */ |
---|
977 | { |
---|
978 | switch (mp_bus_id_to_type[bus]) |
---|
979 | { |
---|
980 | case MP_BUS_ISA: /* ISA pin */ |
---|
981 | { |
---|
982 | polarity = default_ISA_polarity(idx); |
---|
983 | break; |
---|
984 | } |
---|
985 | case MP_BUS_EISA: /* EISA pin */ |
---|
986 | { |
---|
987 | polarity = default_EISA_polarity(idx); |
---|
988 | break; |
---|
989 | } |
---|
990 | case MP_BUS_PCI: /* PCI pin */ |
---|
991 | { |
---|
992 | polarity = default_PCI_polarity(idx); |
---|
993 | break; |
---|
994 | } |
---|
995 | case MP_BUS_MCA: /* MCA pin */ |
---|
996 | { |
---|
997 | polarity = default_MCA_polarity(idx); |
---|
998 | break; |
---|
999 | } |
---|
1000 | case MP_BUS_NEC98: /* NEC 98 pin */ |
---|
1001 | { |
---|
1002 | polarity = default_NEC98_polarity(idx); |
---|
1003 | break; |
---|
1004 | } |
---|
1005 | default: |
---|
1006 | { |
---|
1007 | printk(KERN_WARNING "broken BIOS!!\n"); |
---|
1008 | polarity = 1; |
---|
1009 | break; |
---|
1010 | } |
---|
1011 | } |
---|
1012 | break; |
---|
1013 | } |
---|
1014 | case 1: /* high active */ |
---|
1015 | { |
---|
1016 | polarity = 0; |
---|
1017 | break; |
---|
1018 | } |
---|
1019 | case 2: /* reserved */ |
---|
1020 | { |
---|
1021 | printk(KERN_WARNING "broken BIOS!!\n"); |
---|
1022 | polarity = 1; |
---|
1023 | break; |
---|
1024 | } |
---|
1025 | case 3: /* low active */ |
---|
1026 | { |
---|
1027 | polarity = 1; |
---|
1028 | break; |
---|
1029 | } |
---|
1030 | default: /* invalid */ |
---|
1031 | { |
---|
1032 | printk(KERN_WARNING "broken BIOS!!\n"); |
---|
1033 | polarity = 1; |
---|
1034 | break; |
---|
1035 | } |
---|
1036 | } |
---|
1037 | return polarity; |
---|
1038 | } |
---|
1039 | |
---|
1040 | static int MPBIOS_trigger(int idx) |
---|
1041 | { |
---|
1042 | int bus = mp_irqs[idx].mpc_srcbus; |
---|
1043 | int trigger; |
---|
1044 | |
---|
1045 | /* |
---|
1046 | * Determine IRQ trigger mode (edge or level sensitive): |
---|
1047 | */ |
---|
1048 | switch ((mp_irqs[idx].mpc_irqflag>>2) & 3) |
---|
1049 | { |
---|
1050 | case 0: /* conforms, ie. bus-type dependent */ |
---|
1051 | { |
---|
1052 | switch (mp_bus_id_to_type[bus]) |
---|
1053 | { |
---|
1054 | case MP_BUS_ISA: /* ISA pin */ |
---|
1055 | { |
---|
1056 | trigger = default_ISA_trigger(idx); |
---|
1057 | break; |
---|
1058 | } |
---|
1059 | case MP_BUS_EISA: /* EISA pin */ |
---|
1060 | { |
---|
1061 | trigger = default_EISA_trigger(idx); |
---|
1062 | break; |
---|
1063 | } |
---|
1064 | case MP_BUS_PCI: /* PCI pin */ |
---|
1065 | { |
---|
1066 | trigger = default_PCI_trigger(idx); |
---|
1067 | break; |
---|
1068 | } |
---|
1069 | case MP_BUS_MCA: /* MCA pin */ |
---|
1070 | { |
---|
1071 | trigger = default_MCA_trigger(idx); |
---|
1072 | break; |
---|
1073 | } |
---|
1074 | case MP_BUS_NEC98: /* NEC 98 pin */ |
---|
1075 | { |
---|
1076 | trigger = default_NEC98_trigger(idx); |
---|
1077 | break; |
---|
1078 | } |
---|
1079 | default: |
---|
1080 | { |
---|
1081 | printk(KERN_WARNING "broken BIOS!!\n"); |
---|
1082 | trigger = 1; |
---|
1083 | break; |
---|
1084 | } |
---|
1085 | } |
---|
1086 | break; |
---|
1087 | } |
---|
1088 | case 1: /* edge */ |
---|
1089 | { |
---|
1090 | trigger = 0; |
---|
1091 | break; |
---|
1092 | } |
---|
1093 | case 2: /* reserved */ |
---|
1094 | { |
---|
1095 | printk(KERN_WARNING "broken BIOS!!\n"); |
---|
1096 | trigger = 1; |
---|
1097 | break; |
---|
1098 | } |
---|
1099 | case 3: /* level */ |
---|
1100 | { |
---|
1101 | trigger = 1; |
---|
1102 | break; |
---|
1103 | } |
---|
1104 | default: /* invalid */ |
---|
1105 | { |
---|
1106 | printk(KERN_WARNING "broken BIOS!!\n"); |
---|
1107 | trigger = 0; |
---|
1108 | break; |
---|
1109 | } |
---|
1110 | } |
---|
1111 | return trigger; |
---|
1112 | } |
---|
1113 | |
---|
1114 | static inline int irq_polarity(int idx) |
---|
1115 | { |
---|
1116 | return MPBIOS_polarity(idx); |
---|
1117 | } |
---|
1118 | |
---|
1119 | static inline int irq_trigger(int idx) |
---|
1120 | { |
---|
1121 | return MPBIOS_trigger(idx); |
---|
1122 | } |
---|
1123 | |
---|
1124 | static int pin_2_irq(int idx, int apic, int pin) |
---|
1125 | { |
---|
1126 | int irq, i; |
---|
1127 | int bus = mp_irqs[idx].mpc_srcbus; |
---|
1128 | |
---|
1129 | /* |
---|
1130 | * Debugging check, we are in big trouble if this message pops up! |
---|
1131 | */ |
---|
1132 | if (mp_irqs[idx].mpc_dstirq != pin) |
---|
1133 | printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n"); |
---|
1134 | |
---|
1135 | switch (mp_bus_id_to_type[bus]) |
---|
1136 | { |
---|
1137 | case MP_BUS_ISA: /* ISA pin */ |
---|
1138 | case MP_BUS_EISA: |
---|
1139 | case MP_BUS_MCA: |
---|
1140 | case MP_BUS_NEC98: |
---|
1141 | { |
---|
1142 | irq = mp_irqs[idx].mpc_srcbusirq; |
---|
1143 | break; |
---|
1144 | } |
---|
1145 | case MP_BUS_PCI: /* PCI pin */ |
---|
1146 | { |
---|
1147 | /* |
---|
1148 | * PCI IRQs are mapped in order |
---|
1149 | */ |
---|
1150 | i = irq = 0; |
---|
1151 | while (i < apic) |
---|
1152 | irq += nr_ioapic_registers[i++]; |
---|
1153 | irq += pin; |
---|
1154 | |
---|
1155 | /* |
---|
1156 | * For MPS mode, so far only needed by ES7000 platform |
---|
1157 | */ |
---|
1158 | if (ioapic_renumber_irq) |
---|
1159 | irq = ioapic_renumber_irq(apic, irq); |
---|
1160 | |
---|
1161 | break; |
---|
1162 | } |
---|
1163 | default: |
---|
1164 | { |
---|
1165 | printk(KERN_ERR "unknown bus type %d.\n",bus); |
---|
1166 | irq = 0; |
---|
1167 | break; |
---|
1168 | } |
---|
1169 | } |
---|
1170 | |
---|
1171 | /* |
---|
1172 | * PCI IRQ command line redirection. Yes, limits are hardcoded. |
---|
1173 | */ |
---|
1174 | if ((pin >= 16) && (pin <= 23)) { |
---|
1175 | if (pirq_entries[pin-16] != -1) { |
---|
1176 | if (!pirq_entries[pin-16]) { |
---|
1177 | apic_printk(APIC_VERBOSE, KERN_DEBUG |
---|
1178 | "disabling PIRQ%d\n", pin-16); |
---|
1179 | } else { |
---|
1180 | irq = pirq_entries[pin-16]; |
---|
1181 | apic_printk(APIC_VERBOSE, KERN_DEBUG |
---|
1182 | "using PIRQ%d -> IRQ %d\n", |
---|
1183 | pin-16, irq); |
---|
1184 | } |
---|
1185 | } |
---|
1186 | } |
---|
1187 | return irq; |
---|
1188 | } |
---|
1189 | |
---|
1190 | static inline int IO_APIC_irq_trigger(int irq) |
---|
1191 | { |
---|
1192 | int apic, idx, pin; |
---|
1193 | |
---|
1194 | for (apic = 0; apic < nr_ioapics; apic++) { |
---|
1195 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { |
---|
1196 | idx = find_irq_entry(apic,pin,mp_INT); |
---|
1197 | if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin))) |
---|
1198 | return irq_trigger(idx); |
---|
1199 | } |
---|
1200 | } |
---|
1201 | /* |
---|
1202 | * nonexistent IRQs are edge default |
---|
1203 | */ |
---|
1204 | return 0; |
---|
1205 | } |
---|
1206 | |
---|
1207 | /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */ |
---|
1208 | u8 irq_vector[NR_IRQ_VECTORS] __read_mostly; /* = { FIRST_DEVICE_VECTOR , 0 }; */ |
---|
1209 | |
---|
1210 | int assign_irq_vector(int irq) |
---|
1211 | { |
---|
1212 | unsigned long flags; |
---|
1213 | int vector; |
---|
1214 | struct physdev_irq irq_op; |
---|
1215 | |
---|
1216 | BUG_ON(irq != AUTO_ASSIGN && (unsigned)irq >= NR_IRQ_VECTORS); |
---|
1217 | |
---|
1218 | spin_lock_irqsave(&vector_lock, flags); |
---|
1219 | |
---|
1220 | if (irq != AUTO_ASSIGN && IO_APIC_VECTOR(irq) > 0) { |
---|
1221 | spin_unlock_irqrestore(&vector_lock, flags); |
---|
1222 | return IO_APIC_VECTOR(irq); |
---|
1223 | } |
---|
1224 | |
---|
1225 | irq_op.irq = irq; |
---|
1226 | if (HYPERVISOR_physdev_op(PHYSDEVOP_alloc_irq_vector, &irq_op)) { |
---|
1227 | spin_unlock_irqrestore(&vector_lock, flags); |
---|
1228 | return -ENOSPC; |
---|
1229 | } |
---|
1230 | |
---|
1231 | vector = irq_op.vector; |
---|
1232 | vector_irq[vector] = irq; |
---|
1233 | if (irq != AUTO_ASSIGN) |
---|
1234 | IO_APIC_VECTOR(irq) = vector; |
---|
1235 | |
---|
1236 | spin_unlock_irqrestore(&vector_lock, flags); |
---|
1237 | |
---|
1238 | return vector; |
---|
1239 | } |
---|
1240 | |
---|
1241 | #ifndef CONFIG_XEN |
---|
1242 | static struct hw_interrupt_type ioapic_level_type; |
---|
1243 | static struct hw_interrupt_type ioapic_edge_type; |
---|
1244 | |
---|
1245 | #define IOAPIC_AUTO -1 |
---|
1246 | #define IOAPIC_EDGE 0 |
---|
1247 | #define IOAPIC_LEVEL 1 |
---|
1248 | |
---|
1249 | static void ioapic_register_intr(int irq, int vector, unsigned long trigger) |
---|
1250 | { |
---|
1251 | unsigned idx; |
---|
1252 | |
---|
1253 | idx = use_pci_vector() && !platform_legacy_irq(irq) ? vector : irq; |
---|
1254 | |
---|
1255 | if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) || |
---|
1256 | trigger == IOAPIC_LEVEL) |
---|
1257 | irq_desc[idx].chip = &ioapic_level_type; |
---|
1258 | else |
---|
1259 | irq_desc[idx].chip = &ioapic_edge_type; |
---|
1260 | set_intr_gate(vector, interrupt[idx]); |
---|
1261 | } |
---|
1262 | #else |
---|
1263 | #define ioapic_register_intr(_irq,_vector,_trigger) ((void)0) |
---|
1264 | #endif |
---|
1265 | |
---|
1266 | static void __init setup_IO_APIC_irqs(void) |
---|
1267 | { |
---|
1268 | struct IO_APIC_route_entry entry; |
---|
1269 | int apic, pin, idx, irq, first_notcon = 1, vector; |
---|
1270 | unsigned long flags; |
---|
1271 | |
---|
1272 | apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n"); |
---|
1273 | |
---|
1274 | for (apic = 0; apic < nr_ioapics; apic++) { |
---|
1275 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { |
---|
1276 | |
---|
1277 | /* |
---|
1278 | * add it to the IO-APIC irq-routing table: |
---|
1279 | */ |
---|
1280 | memset(&entry,0,sizeof(entry)); |
---|
1281 | |
---|
1282 | entry.delivery_mode = INT_DELIVERY_MODE; |
---|
1283 | entry.dest_mode = INT_DEST_MODE; |
---|
1284 | entry.mask = 0; /* enable IRQ */ |
---|
1285 | entry.dest.logical.logical_dest = |
---|
1286 | cpu_mask_to_apicid(TARGET_CPUS); |
---|
1287 | |
---|
1288 | idx = find_irq_entry(apic,pin,mp_INT); |
---|
1289 | if (idx == -1) { |
---|
1290 | if (first_notcon) { |
---|
1291 | apic_printk(APIC_VERBOSE, KERN_DEBUG |
---|
1292 | " IO-APIC (apicid-pin) %d-%d", |
---|
1293 | mp_ioapics[apic].mpc_apicid, |
---|
1294 | pin); |
---|
1295 | first_notcon = 0; |
---|
1296 | } else |
---|
1297 | apic_printk(APIC_VERBOSE, ", %d-%d", |
---|
1298 | mp_ioapics[apic].mpc_apicid, pin); |
---|
1299 | continue; |
---|
1300 | } |
---|
1301 | |
---|
1302 | entry.trigger = irq_trigger(idx); |
---|
1303 | entry.polarity = irq_polarity(idx); |
---|
1304 | |
---|
1305 | if (irq_trigger(idx)) { |
---|
1306 | entry.trigger = 1; |
---|
1307 | entry.mask = 1; |
---|
1308 | } |
---|
1309 | |
---|
1310 | irq = pin_2_irq(idx, apic, pin); |
---|
1311 | /* |
---|
1312 | * skip adding the timer int on secondary nodes, which causes |
---|
1313 | * a small but painful rift in the time-space continuum |
---|
1314 | */ |
---|
1315 | if (multi_timer_check(apic, irq)) |
---|
1316 | continue; |
---|
1317 | else |
---|
1318 | add_pin_to_irq(irq, apic, pin); |
---|
1319 | |
---|
1320 | if (/*!apic &&*/ !IO_APIC_IRQ(irq)) |
---|
1321 | continue; |
---|
1322 | |
---|
1323 | if (IO_APIC_IRQ(irq)) { |
---|
1324 | vector = assign_irq_vector(irq); |
---|
1325 | entry.vector = vector; |
---|
1326 | ioapic_register_intr(irq, vector, IOAPIC_AUTO); |
---|
1327 | |
---|
1328 | if (!apic && (irq < 16)) |
---|
1329 | disable_8259A_irq(irq); |
---|
1330 | } |
---|
1331 | spin_lock_irqsave(&ioapic_lock, flags); |
---|
1332 | io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1)); |
---|
1333 | io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0)); |
---|
1334 | set_native_irq_info(irq, TARGET_CPUS); |
---|
1335 | spin_unlock_irqrestore(&ioapic_lock, flags); |
---|
1336 | } |
---|
1337 | } |
---|
1338 | |
---|
1339 | if (!first_notcon) |
---|
1340 | apic_printk(APIC_VERBOSE, " not connected.\n"); |
---|
1341 | } |
---|
1342 | |
---|
1343 | /* |
---|
1344 | * Set up the 8259A-master output pin: |
---|
1345 | */ |
---|
1346 | #ifndef CONFIG_XEN |
---|
1347 | static void __init setup_ExtINT_IRQ0_pin(unsigned int apic, unsigned int pin, int vector) |
---|
1348 | { |
---|
1349 | struct IO_APIC_route_entry entry; |
---|
1350 | unsigned long flags; |
---|
1351 | |
---|
1352 | memset(&entry,0,sizeof(entry)); |
---|
1353 | |
---|
1354 | disable_8259A_irq(0); |
---|
1355 | |
---|
1356 | /* mask LVT0 */ |
---|
1357 | apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT); |
---|
1358 | |
---|
1359 | /* |
---|
1360 | * We use logical delivery to get the timer IRQ |
---|
1361 | * to the first CPU. |
---|
1362 | */ |
---|
1363 | entry.dest_mode = INT_DEST_MODE; |
---|
1364 | entry.mask = 0; /* unmask IRQ now */ |
---|
1365 | entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS); |
---|
1366 | entry.delivery_mode = INT_DELIVERY_MODE; |
---|
1367 | entry.polarity = 0; |
---|
1368 | entry.trigger = 0; |
---|
1369 | entry.vector = vector; |
---|
1370 | |
---|
1371 | /* |
---|
1372 | * The timer IRQ doesn't have to know that behind the |
---|
1373 | * scene we have a 8259A-master in AEOI mode ... |
---|
1374 | */ |
---|
1375 | irq_desc[0].chip = &ioapic_edge_type; |
---|
1376 | |
---|
1377 | /* |
---|
1378 | * Add it to the IO-APIC irq-routing table: |
---|
1379 | */ |
---|
1380 | spin_lock_irqsave(&ioapic_lock, flags); |
---|
1381 | io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1)); |
---|
1382 | io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0)); |
---|
1383 | spin_unlock_irqrestore(&ioapic_lock, flags); |
---|
1384 | |
---|
1385 | enable_8259A_irq(0); |
---|
1386 | } |
---|
1387 | |
---|
1388 | static inline void UNEXPECTED_IO_APIC(void) |
---|
1389 | { |
---|
1390 | } |
---|
1391 | |
---|
1392 | void __init print_IO_APIC(void) |
---|
1393 | { |
---|
1394 | int apic, i; |
---|
1395 | union IO_APIC_reg_00 reg_00; |
---|
1396 | union IO_APIC_reg_01 reg_01; |
---|
1397 | union IO_APIC_reg_02 reg_02; |
---|
1398 | union IO_APIC_reg_03 reg_03; |
---|
1399 | unsigned long flags; |
---|
1400 | |
---|
1401 | if (apic_verbosity == APIC_QUIET) |
---|
1402 | return; |
---|
1403 | |
---|
1404 | printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries); |
---|
1405 | for (i = 0; i < nr_ioapics; i++) |
---|
1406 | printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n", |
---|
1407 | mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]); |
---|
1408 | |
---|
1409 | /* |
---|
1410 | * We are a bit conservative about what we expect. We have to |
---|
1411 | * know about every hardware change ASAP. |
---|
1412 | */ |
---|
1413 | printk(KERN_INFO "testing the IO APIC.......................\n"); |
---|
1414 | |
---|
1415 | for (apic = 0; apic < nr_ioapics; apic++) { |
---|
1416 | |
---|
1417 | spin_lock_irqsave(&ioapic_lock, flags); |
---|
1418 | reg_00.raw = io_apic_read(apic, 0); |
---|
1419 | reg_01.raw = io_apic_read(apic, 1); |
---|
1420 | if (reg_01.bits.version >= 0x10) |
---|
1421 | reg_02.raw = io_apic_read(apic, 2); |
---|
1422 | if (reg_01.bits.version >= 0x20) |
---|
1423 | reg_03.raw = io_apic_read(apic, 3); |
---|
1424 | spin_unlock_irqrestore(&ioapic_lock, flags); |
---|
1425 | |
---|
1426 | printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid); |
---|
1427 | printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw); |
---|
1428 | printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID); |
---|
1429 | printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type); |
---|
1430 | printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS); |
---|
1431 | if (reg_00.bits.ID >= get_physical_broadcast()) |
---|
1432 | UNEXPECTED_IO_APIC(); |
---|
1433 | if (reg_00.bits.__reserved_1 || reg_00.bits.__reserved_2) |
---|
1434 | UNEXPECTED_IO_APIC(); |
---|
1435 | |
---|
1436 | printk(KERN_DEBUG ".... register #01: %08X\n", reg_01.raw); |
---|
1437 | printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries); |
---|
1438 | if ( (reg_01.bits.entries != 0x0f) && /* older (Neptune) boards */ |
---|
1439 | (reg_01.bits.entries != 0x17) && /* typical ISA+PCI boards */ |
---|
1440 | (reg_01.bits.entries != 0x1b) && /* Compaq Proliant boards */ |
---|
1441 | (reg_01.bits.entries != 0x1f) && /* dual Xeon boards */ |
---|
1442 | (reg_01.bits.entries != 0x22) && /* bigger Xeon boards */ |
---|
1443 | (reg_01.bits.entries != 0x2E) && |
---|
1444 | (reg_01.bits.entries != 0x3F) |
---|
1445 | ) |
---|
1446 | UNEXPECTED_IO_APIC(); |
---|
1447 | |
---|
1448 | printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ); |
---|
1449 | printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version); |
---|
1450 | if ( (reg_01.bits.version != 0x01) && /* 82489DX IO-APICs */ |
---|
1451 | (reg_01.bits.version != 0x10) && /* oldest IO-APICs */ |
---|
1452 | (reg_01.bits.version != 0x11) && /* Pentium/Pro IO-APICs */ |
---|
1453 | (reg_01.bits.version != 0x13) && /* Xeon IO-APICs */ |
---|
1454 | (reg_01.bits.version != 0x20) /* Intel P64H (82806 AA) */ |
---|
1455 | ) |
---|
1456 | UNEXPECTED_IO_APIC(); |
---|
1457 | if (reg_01.bits.__reserved_1 || reg_01.bits.__reserved_2) |
---|
1458 | UNEXPECTED_IO_APIC(); |
---|
1459 | |
---|
1460 | /* |
---|
1461 | * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02, |
---|
1462 | * but the value of reg_02 is read as the previous read register |
---|
1463 | * value, so ignore it if reg_02 == reg_01. |
---|
1464 | */ |
---|
1465 | if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) { |
---|
1466 | printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw); |
---|
1467 | printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration); |
---|
1468 | if (reg_02.bits.__reserved_1 || reg_02.bits.__reserved_2) |
---|
1469 | UNEXPECTED_IO_APIC(); |
---|
1470 | } |
---|
1471 | |
---|
1472 | /* |
---|
1473 | * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02 |
---|
1474 | * or reg_03, but the value of reg_0[23] is read as the previous read |
---|
1475 | * register value, so ignore it if reg_03 == reg_0[12]. |
---|
1476 | */ |
---|
1477 | if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw && |
---|
1478 | reg_03.raw != reg_01.raw) { |
---|
1479 | printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw); |
---|
1480 | printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT); |
---|
1481 | if (reg_03.bits.__reserved_1) |
---|
1482 | UNEXPECTED_IO_APIC(); |
---|
1483 | } |
---|
1484 | |
---|
1485 | printk(KERN_DEBUG ".... IRQ redirection table:\n"); |
---|
1486 | |
---|
1487 | printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol" |
---|
1488 | " Stat Dest Deli Vect: \n"); |
---|
1489 | |
---|
1490 | for (i = 0; i <= reg_01.bits.entries; i++) { |
---|
1491 | struct IO_APIC_route_entry entry; |
---|
1492 | |
---|
1493 | spin_lock_irqsave(&ioapic_lock, flags); |
---|
1494 | *(((int *)&entry)+0) = io_apic_read(apic, 0x10+i*2); |
---|
1495 | *(((int *)&entry)+1) = io_apic_read(apic, 0x11+i*2); |
---|
1496 | spin_unlock_irqrestore(&ioapic_lock, flags); |
---|
1497 | |
---|
1498 | printk(KERN_DEBUG " %02x %03X %02X ", |
---|
1499 | i, |
---|
1500 | entry.dest.logical.logical_dest, |
---|
1501 | entry.dest.physical.physical_dest |
---|
1502 | ); |
---|
1503 | |
---|
1504 | printk("%1d %1d %1d %1d %1d %1d %1d %02X\n", |
---|
1505 | entry.mask, |
---|
1506 | entry.trigger, |
---|
1507 | entry.irr, |
---|
1508 | entry.polarity, |
---|
1509 | entry.delivery_status, |
---|
1510 | entry.dest_mode, |
---|
1511 | entry.delivery_mode, |
---|
1512 | entry.vector |
---|
1513 | ); |
---|
1514 | } |
---|
1515 | } |
---|
1516 | if (use_pci_vector()) |
---|
1517 | printk(KERN_INFO "Using vector-based indexing\n"); |
---|
1518 | printk(KERN_DEBUG "IRQ to pin mappings:\n"); |
---|
1519 | for (i = 0; i < NR_IRQS; i++) { |
---|
1520 | struct irq_pin_list *entry = irq_2_pin + i; |
---|
1521 | if (entry->pin < 0) |
---|
1522 | continue; |
---|
1523 | if (use_pci_vector() && !platform_legacy_irq(i)) |
---|
1524 | printk(KERN_DEBUG "IRQ%d ", IO_APIC_VECTOR(i)); |
---|
1525 | else |
---|
1526 | printk(KERN_DEBUG "IRQ%d ", i); |
---|
1527 | for (;;) { |
---|
1528 | printk("-> %d:%d", entry->apic, entry->pin); |
---|
1529 | if (!entry->next) |
---|
1530 | break; |
---|
1531 | entry = irq_2_pin + entry->next; |
---|
1532 | } |
---|
1533 | printk("\n"); |
---|
1534 | } |
---|
1535 | |
---|
1536 | printk(KERN_INFO ".................................... done.\n"); |
---|
1537 | |
---|
1538 | return; |
---|
1539 | } |
---|
1540 | |
---|
1541 | #if 0 |
---|
1542 | |
---|
1543 | static void print_APIC_bitfield (int base) |
---|
1544 | { |
---|
1545 | unsigned int v; |
---|
1546 | int i, j; |
---|
1547 | |
---|
1548 | if (apic_verbosity == APIC_QUIET) |
---|
1549 | return; |
---|
1550 | |
---|
1551 | printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG); |
---|
1552 | for (i = 0; i < 8; i++) { |
---|
1553 | v = apic_read(base + i*0x10); |
---|
1554 | for (j = 0; j < 32; j++) { |
---|
1555 | if (v & (1<<j)) |
---|
1556 | printk("1"); |
---|
1557 | else |
---|
1558 | printk("0"); |
---|
1559 | } |
---|
1560 | printk("\n"); |
---|
1561 | } |
---|
1562 | } |
---|
1563 | |
---|
1564 | void /*__init*/ print_local_APIC(void * dummy) |
---|
1565 | { |
---|
1566 | unsigned int v, ver, maxlvt; |
---|
1567 | |
---|
1568 | if (apic_verbosity == APIC_QUIET) |
---|
1569 | return; |
---|
1570 | |
---|
1571 | printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n", |
---|
1572 | smp_processor_id(), hard_smp_processor_id()); |
---|
1573 | v = apic_read(APIC_ID); |
---|
1574 | printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, GET_APIC_ID(v)); |
---|
1575 | v = apic_read(APIC_LVR); |
---|
1576 | printk(KERN_INFO "... APIC VERSION: %08x\n", v); |
---|
1577 | ver = GET_APIC_VERSION(v); |
---|
1578 | maxlvt = get_maxlvt(); |
---|
1579 | |
---|
1580 | v = apic_read(APIC_TASKPRI); |
---|
1581 | printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK); |
---|
1582 | |
---|
1583 | if (APIC_INTEGRATED(ver)) { /* !82489DX */ |
---|
1584 | v = apic_read(APIC_ARBPRI); |
---|
1585 | printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v, |
---|
1586 | v & APIC_ARBPRI_MASK); |
---|
1587 | v = apic_read(APIC_PROCPRI); |
---|
1588 | printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v); |
---|
1589 | } |
---|
1590 | |
---|
1591 | v = apic_read(APIC_EOI); |
---|
1592 | printk(KERN_DEBUG "... APIC EOI: %08x\n", v); |
---|
1593 | v = apic_read(APIC_RRR); |
---|
1594 | printk(KERN_DEBUG "... APIC RRR: %08x\n", v); |
---|
1595 | v = apic_read(APIC_LDR); |
---|
1596 | printk(KERN_DEBUG "... APIC LDR: %08x\n", v); |
---|
1597 | v = apic_read(APIC_DFR); |
---|
1598 | printk(KERN_DEBUG "... APIC DFR: %08x\n", v); |
---|
1599 | v = apic_read(APIC_SPIV); |
---|
1600 | printk(KERN_DEBUG "... APIC SPIV: %08x\n", v); |
---|
1601 | |
---|
1602 | printk(KERN_DEBUG "... APIC ISR field:\n"); |
---|
1603 | print_APIC_bitfield(APIC_ISR); |
---|
1604 | printk(KERN_DEBUG "... APIC TMR field:\n"); |
---|
1605 | print_APIC_bitfield(APIC_TMR); |
---|
1606 | printk(KERN_DEBUG "... APIC IRR field:\n"); |
---|
1607 | print_APIC_bitfield(APIC_IRR); |
---|
1608 | |
---|
1609 | if (APIC_INTEGRATED(ver)) { /* !82489DX */ |
---|
1610 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ |
---|
1611 | apic_write(APIC_ESR, 0); |
---|
1612 | v = apic_read(APIC_ESR); |
---|
1613 | printk(KERN_DEBUG "... APIC ESR: %08x\n", v); |
---|
1614 | } |
---|
1615 | |
---|
1616 | v = apic_read(APIC_ICR); |
---|
1617 | printk(KERN_DEBUG "... APIC ICR: %08x\n", v); |
---|
1618 | v = apic_read(APIC_ICR2); |
---|
1619 | printk(KERN_DEBUG "... APIC ICR2: %08x\n", v); |
---|
1620 | |
---|
1621 | v = apic_read(APIC_LVTT); |
---|
1622 | printk(KERN_DEBUG "... APIC LVTT: %08x\n", v); |
---|
1623 | |
---|
1624 | if (maxlvt > 3) { /* PC is LVT#4. */ |
---|
1625 | v = apic_read(APIC_LVTPC); |
---|
1626 | printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v); |
---|
1627 | } |
---|
1628 | v = apic_read(APIC_LVT0); |
---|
1629 | printk(KERN_DEBUG "... APIC LVT0: %08x\n", v); |
---|
1630 | v = apic_read(APIC_LVT1); |
---|
1631 | printk(KERN_DEBUG "... APIC LVT1: %08x\n", v); |
---|
1632 | |
---|
1633 | if (maxlvt > 2) { /* ERR is LVT#3. */ |
---|
1634 | v = apic_read(APIC_LVTERR); |
---|
1635 | printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v); |
---|
1636 | } |
---|
1637 | |
---|
1638 | v = apic_read(APIC_TMICT); |
---|
1639 | printk(KERN_DEBUG "... APIC TMICT: %08x\n", v); |
---|
1640 | v = apic_read(APIC_TMCCT); |
---|
1641 | printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v); |
---|
1642 | v = apic_read(APIC_TDCR); |
---|
1643 | printk(KERN_DEBUG "... APIC TDCR: %08x\n", v); |
---|
1644 | printk("\n"); |
---|
1645 | } |
---|
1646 | |
---|
1647 | void print_all_local_APICs (void) |
---|
1648 | { |
---|
1649 | on_each_cpu(print_local_APIC, NULL, 1, 1); |
---|
1650 | } |
---|
1651 | |
---|
1652 | void /*__init*/ print_PIC(void) |
---|
1653 | { |
---|
1654 | unsigned int v; |
---|
1655 | unsigned long flags; |
---|
1656 | |
---|
1657 | if (apic_verbosity == APIC_QUIET) |
---|
1658 | return; |
---|
1659 | |
---|
1660 | printk(KERN_DEBUG "\nprinting PIC contents\n"); |
---|
1661 | |
---|
1662 | spin_lock_irqsave(&i8259A_lock, flags); |
---|
1663 | |
---|
1664 | v = inb(0xa1) << 8 | inb(0x21); |
---|
1665 | printk(KERN_DEBUG "... PIC IMR: %04x\n", v); |
---|
1666 | |
---|
1667 | v = inb(0xa0) << 8 | inb(0x20); |
---|
1668 | printk(KERN_DEBUG "... PIC IRR: %04x\n", v); |
---|
1669 | |
---|
1670 | outb(0x0b,0xa0); |
---|
1671 | outb(0x0b,0x20); |
---|
1672 | v = inb(0xa0) << 8 | inb(0x20); |
---|
1673 | outb(0x0a,0xa0); |
---|
1674 | outb(0x0a,0x20); |
---|
1675 | |
---|
1676 | spin_unlock_irqrestore(&i8259A_lock, flags); |
---|
1677 | |
---|
1678 | printk(KERN_DEBUG "... PIC ISR: %04x\n", v); |
---|
1679 | |
---|
1680 | v = inb(0x4d1) << 8 | inb(0x4d0); |
---|
1681 | printk(KERN_DEBUG "... PIC ELCR: %04x\n", v); |
---|
1682 | } |
---|
1683 | |
---|
1684 | #endif /* 0 */ |
---|
1685 | |
---|
1686 | #else |
---|
1687 | void __init print_IO_APIC(void) { } |
---|
1688 | #endif /* !CONFIG_XEN */ |
---|
1689 | |
---|
1690 | static void __init enable_IO_APIC(void) |
---|
1691 | { |
---|
1692 | union IO_APIC_reg_01 reg_01; |
---|
1693 | int i8259_apic, i8259_pin; |
---|
1694 | int i, apic; |
---|
1695 | unsigned long flags; |
---|
1696 | |
---|
1697 | for (i = 0; i < PIN_MAP_SIZE; i++) { |
---|
1698 | irq_2_pin[i].pin = -1; |
---|
1699 | irq_2_pin[i].next = 0; |
---|
1700 | } |
---|
1701 | if (!pirqs_enabled) |
---|
1702 | for (i = 0; i < MAX_PIRQS; i++) |
---|
1703 | pirq_entries[i] = -1; |
---|
1704 | |
---|
1705 | /* |
---|
1706 | * The number of IO-APIC IRQ registers (== #pins): |
---|
1707 | */ |
---|
1708 | for (apic = 0; apic < nr_ioapics; apic++) { |
---|
1709 | spin_lock_irqsave(&ioapic_lock, flags); |
---|
1710 | reg_01.raw = io_apic_read(apic, 1); |
---|
1711 | spin_unlock_irqrestore(&ioapic_lock, flags); |
---|
1712 | nr_ioapic_registers[apic] = reg_01.bits.entries+1; |
---|
1713 | } |
---|
1714 | for(apic = 0; apic < nr_ioapics; apic++) { |
---|
1715 | int pin; |
---|
1716 | /* See if any of the pins is in ExtINT mode */ |
---|
1717 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { |
---|
1718 | struct IO_APIC_route_entry entry; |
---|
1719 | spin_lock_irqsave(&ioapic_lock, flags); |
---|
1720 | *(((int *)&entry) + 0) = io_apic_read(apic, 0x10 + 2 * pin); |
---|
1721 | *(((int *)&entry) + 1) = io_apic_read(apic, 0x11 + 2 * pin); |
---|
1722 | spin_unlock_irqrestore(&ioapic_lock, flags); |
---|
1723 | |
---|
1724 | |
---|
1725 | /* If the interrupt line is enabled and in ExtInt mode |
---|
1726 | * I have found the pin where the i8259 is connected. |
---|
1727 | */ |
---|
1728 | if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) { |
---|
1729 | ioapic_i8259.apic = apic; |
---|
1730 | ioapic_i8259.pin = pin; |
---|
1731 | goto found_i8259; |
---|
1732 | } |
---|
1733 | } |
---|
1734 | } |
---|
1735 | found_i8259: |
---|
1736 | /* Look to see what if the MP table has reported the ExtINT */ |
---|
1737 | /* If we could not find the appropriate pin by looking at the ioapic |
---|
1738 | * the i8259 probably is not connected the ioapic but give the |
---|
1739 | * mptable a chance anyway. |
---|
1740 | */ |
---|
1741 | i8259_pin = find_isa_irq_pin(0, mp_ExtINT); |
---|
1742 | i8259_apic = find_isa_irq_apic(0, mp_ExtINT); |
---|
1743 | /* Trust the MP table if nothing is setup in the hardware */ |
---|
1744 | if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) { |
---|
1745 | printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n"); |
---|
1746 | ioapic_i8259.pin = i8259_pin; |
---|
1747 | ioapic_i8259.apic = i8259_apic; |
---|
1748 | } |
---|
1749 | /* Complain if the MP table and the hardware disagree */ |
---|
1750 | if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) && |
---|
1751 | (i8259_pin >= 0) && (ioapic_i8259.pin >= 0)) |
---|
1752 | { |
---|
1753 | printk(KERN_WARNING "ExtINT in hardware and MP table differ\n"); |
---|
1754 | } |
---|
1755 | |
---|
1756 | /* |
---|
1757 | * Do not trust the IO-APIC being empty at bootup |
---|
1758 | */ |
---|
1759 | clear_IO_APIC(); |
---|
1760 | } |
---|
1761 | |
---|
1762 | /* |
---|
1763 | * Not an __init, needed by the reboot code |
---|
1764 | */ |
---|
1765 | void disable_IO_APIC(void) |
---|
1766 | { |
---|
1767 | /* |
---|
1768 | * Clear the IO-APIC before rebooting: |
---|
1769 | */ |
---|
1770 | clear_IO_APIC(); |
---|
1771 | |
---|
1772 | #ifndef CONFIG_XEN |
---|
1773 | /* |
---|
1774 | * If the i8259 is routed through an IOAPIC |
---|
1775 | * Put that IOAPIC in virtual wire mode |
---|
1776 | * so legacy interrupts can be delivered. |
---|
1777 | */ |
---|
1778 | if (ioapic_i8259.pin != -1) { |
---|
1779 | struct IO_APIC_route_entry entry; |
---|
1780 | unsigned long flags; |
---|
1781 | |
---|
1782 | memset(&entry, 0, sizeof(entry)); |
---|
1783 | entry.mask = 0; /* Enabled */ |
---|
1784 | entry.trigger = 0; /* Edge */ |
---|
1785 | entry.irr = 0; |
---|
1786 | entry.polarity = 0; /* High */ |
---|
1787 | entry.delivery_status = 0; |
---|
1788 | entry.dest_mode = 0; /* Physical */ |
---|
1789 | entry.delivery_mode = dest_ExtINT; /* ExtInt */ |
---|
1790 | entry.vector = 0; |
---|
1791 | entry.dest.physical.physical_dest = |
---|
1792 | GET_APIC_ID(apic_read(APIC_ID)); |
---|
1793 | |
---|
1794 | /* |
---|
1795 | * Add it to the IO-APIC irq-routing table: |
---|
1796 | */ |
---|
1797 | spin_lock_irqsave(&ioapic_lock, flags); |
---|
1798 | io_apic_write(ioapic_i8259.apic, 0x11+2*ioapic_i8259.pin, |
---|
1799 | *(((int *)&entry)+1)); |
---|
1800 | io_apic_write(ioapic_i8259.apic, 0x10+2*ioapic_i8259.pin, |
---|
1801 | *(((int *)&entry)+0)); |
---|
1802 | spin_unlock_irqrestore(&ioapic_lock, flags); |
---|
1803 | } |
---|
1804 | disconnect_bsp_APIC(ioapic_i8259.pin != -1); |
---|
1805 | #endif |
---|
1806 | } |
---|
1807 | |
---|
1808 | /* |
---|
1809 | * function to set the IO-APIC physical IDs based on the |
---|
1810 | * values stored in the MPC table. |
---|
1811 | * |
---|
1812 | * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999 |
---|
1813 | */ |
---|
1814 | |
---|
1815 | #if !defined(CONFIG_XEN) && !defined(CONFIG_X86_NUMAQ) |
---|
1816 | static void __init setup_ioapic_ids_from_mpc(void) |
---|
1817 | { |
---|
1818 | union IO_APIC_reg_00 reg_00; |
---|
1819 | physid_mask_t phys_id_present_map; |
---|
1820 | int apic; |
---|
1821 | int i; |
---|
1822 | unsigned char old_id; |
---|
1823 | unsigned long flags; |
---|
1824 | |
---|
1825 | /* |
---|
1826 | * Don't check I/O APIC IDs for xAPIC systems. They have |
---|
1827 | * no meaning without the serial APIC bus. |
---|
1828 | */ |
---|
1829 | if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) |
---|
1830 | || APIC_XAPIC(apic_version[boot_cpu_physical_apicid])) |
---|
1831 | return; |
---|
1832 | /* |
---|
1833 | * This is broken; anything with a real cpu count has to |
---|
1834 | * circumvent this idiocy regardless. |
---|
1835 | */ |
---|
1836 | phys_id_present_map = ioapic_phys_id_map(phys_cpu_present_map); |
---|
1837 | |
---|
1838 | /* |
---|
1839 | * Set the IOAPIC ID to the value stored in the MPC table. |
---|
1840 | */ |
---|
1841 | for (apic = 0; apic < nr_ioapics; apic++) { |
---|
1842 | |
---|
1843 | /* Read the register 0 value */ |
---|
1844 | spin_lock_irqsave(&ioapic_lock, flags); |
---|
1845 | reg_00.raw = io_apic_read(apic, 0); |
---|
1846 | spin_unlock_irqrestore(&ioapic_lock, flags); |
---|
1847 | |
---|
1848 | old_id = mp_ioapics[apic].mpc_apicid; |
---|
1849 | |
---|
1850 | if (mp_ioapics[apic].mpc_apicid >= get_physical_broadcast()) { |
---|
1851 | printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n", |
---|
1852 | apic, mp_ioapics[apic].mpc_apicid); |
---|
1853 | printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n", |
---|
1854 | reg_00.bits.ID); |
---|
1855 | mp_ioapics[apic].mpc_apicid = reg_00.bits.ID; |
---|
1856 | } |
---|
1857 | |
---|
1858 | /* |
---|
1859 | * Sanity check, is the ID really free? Every APIC in a |
---|
1860 | * system must have a unique ID or we get lots of nice |
---|
1861 | * 'stuck on smp_invalidate_needed IPI wait' messages. |
---|
1862 | */ |
---|
1863 | if (check_apicid_used(phys_id_present_map, |
---|
1864 | mp_ioapics[apic].mpc_apicid)) { |
---|
1865 | printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n", |
---|
1866 | apic, mp_ioapics[apic].mpc_apicid); |
---|
1867 | for (i = 0; i < get_physical_broadcast(); i++) |
---|
1868 | if (!physid_isset(i, phys_id_present_map)) |
---|
1869 | break; |
---|
1870 | if (i >= get_physical_broadcast()) |
---|
1871 | panic("Max APIC ID exceeded!\n"); |
---|
1872 | printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n", |
---|
1873 | i); |
---|
1874 | physid_set(i, phys_id_present_map); |
---|
1875 | mp_ioapics[apic].mpc_apicid = i; |
---|
1876 | } else { |
---|
1877 | physid_mask_t tmp; |
---|
1878 | tmp = apicid_to_cpu_present(mp_ioapics[apic].mpc_apicid); |
---|
1879 | apic_printk(APIC_VERBOSE, "Setting %d in the " |
---|
1880 | "phys_id_present_map\n", |
---|
1881 | mp_ioapics[apic].mpc_apicid); |
---|
1882 | physids_or(phys_id_present_map, phys_id_present_map, tmp); |
---|
1883 | } |
---|
1884 | |
---|
1885 | |
---|
1886 | /* |
---|
1887 | * We need to adjust the IRQ routing table |
---|
1888 | * if the ID changed. |
---|
1889 | */ |
---|
1890 | if (old_id != mp_ioapics[apic].mpc_apicid) |
---|
1891 | for (i = 0; i < mp_irq_entries; i++) |
---|
1892 | if (mp_irqs[i].mpc_dstapic == old_id) |
---|
1893 | mp_irqs[i].mpc_dstapic |
---|
1894 | = mp_ioapics[apic].mpc_apicid; |
---|
1895 | |
---|
1896 | /* |
---|
1897 | * Read the right value from the MPC table and |
---|
1898 | * write it into the ID register. |
---|
1899 | */ |
---|
1900 | apic_printk(APIC_VERBOSE, KERN_INFO |
---|
1901 | "...changing IO-APIC physical APIC ID to %d ...", |
---|
1902 | mp_ioapics[apic].mpc_apicid); |
---|
1903 | |
---|
1904 | reg_00.bits.ID = mp_ioapics[apic].mpc_apicid; |
---|
1905 | spin_lock_irqsave(&ioapic_lock, flags); |
---|
1906 | io_apic_write(apic, 0, reg_00.raw); |
---|
1907 | spin_unlock_irqrestore(&ioapic_lock, flags); |
---|
1908 | |
---|
1909 | /* |
---|
1910 | * Sanity check |
---|
1911 | */ |
---|
1912 | spin_lock_irqsave(&ioapic_lock, flags); |
---|
1913 | reg_00.raw = io_apic_read(apic, 0); |
---|
1914 | spin_unlock_irqrestore(&ioapic_lock, flags); |
---|
1915 | if (reg_00.bits.ID != mp_ioapics[apic].mpc_apicid) |
---|
1916 | printk("could not set ID!\n"); |
---|
1917 | else |
---|
1918 | apic_printk(APIC_VERBOSE, " ok.\n"); |
---|
1919 | } |
---|
1920 | } |
---|
1921 | #else |
---|
1922 | static void __init setup_ioapic_ids_from_mpc(void) { } |
---|
1923 | #endif |
---|
1924 | |
---|
1925 | #ifndef CONFIG_XEN |
---|
1926 | /* |
---|
1927 | * There is a nasty bug in some older SMP boards, their mptable lies |
---|
1928 | * about the timer IRQ. We do the following to work around the situation: |
---|
1929 | * |
---|
1930 | * - timer IRQ defaults to IO-APIC IRQ |
---|
1931 | * - if this function detects that timer IRQs are defunct, then we fall |
---|
1932 | * back to ISA timer IRQs |
---|
1933 | */ |
---|
1934 | static int __init timer_irq_works(void) |
---|
1935 | { |
---|
1936 | unsigned long t1 = jiffies; |
---|
1937 | |
---|
1938 | local_irq_enable(); |
---|
1939 | /* Let ten ticks pass... */ |
---|
1940 | mdelay((10 * 1000) / HZ); |
---|
1941 | |
---|
1942 | /* |
---|
1943 | * Expect a few ticks at least, to be sure some possible |
---|
1944 | * glue logic does not lock up after one or two first |
---|
1945 | * ticks in a non-ExtINT mode. Also the local APIC |
---|
1946 | * might have cached one ExtINT interrupt. Finally, at |
---|
1947 | * least one tick may be lost due to delays. |
---|
1948 | */ |
---|
1949 | if (jiffies - t1 > 4) |
---|
1950 | return 1; |
---|
1951 | |
---|
1952 | return 0; |
---|
1953 | } |
---|
1954 | |
---|
1955 | /* |
---|
1956 | * In the SMP+IOAPIC case it might happen that there are an unspecified |
---|
1957 | * number of pending IRQ events unhandled. These cases are very rare, |
---|
1958 | * so we 'resend' these IRQs via IPIs, to the same CPU. It's much |
---|
1959 | * better to do it this way as thus we do not have to be aware of |
---|
1960 | * 'pending' interrupts in the IRQ path, except at this point. |
---|
1961 | */ |
---|
1962 | /* |
---|
1963 | * Edge triggered needs to resend any interrupt |
---|
1964 | * that was delayed but this is now handled in the device |
---|
1965 | * independent code. |
---|
1966 | */ |
---|
1967 | |
---|
1968 | /* |
---|
1969 | * Starting up a edge-triggered IO-APIC interrupt is |
---|
1970 | * nasty - we need to make sure that we get the edge. |
---|
1971 | * If it is already asserted for some reason, we need |
---|
1972 | * return 1 to indicate that is was pending. |
---|
1973 | * |
---|
1974 | * This is not complete - we should be able to fake |
---|
1975 | * an edge even if it isn't on the 8259A... |
---|
1976 | */ |
---|
1977 | static unsigned int startup_edge_ioapic_irq(unsigned int irq) |
---|
1978 | { |
---|
1979 | int was_pending = 0; |
---|
1980 | unsigned long flags; |
---|
1981 | |
---|
1982 | spin_lock_irqsave(&ioapic_lock, flags); |
---|
1983 | if (irq < 16) { |
---|
1984 | disable_8259A_irq(irq); |
---|
1985 | if (i8259A_irq_pending(irq)) |
---|
1986 | was_pending = 1; |
---|
1987 | } |
---|
1988 | __unmask_IO_APIC_irq(irq); |
---|
1989 | spin_unlock_irqrestore(&ioapic_lock, flags); |
---|
1990 | |
---|
1991 | return was_pending; |
---|
1992 | } |
---|
1993 | |
---|
1994 | /* |
---|
1995 | * Once we have recorded IRQ_PENDING already, we can mask the |
---|
1996 | * interrupt for real. This prevents IRQ storms from unhandled |
---|
1997 | * devices. |
---|
1998 | */ |
---|
1999 | static void ack_edge_ioapic_irq(unsigned int irq) |
---|
2000 | { |
---|
2001 | move_irq(irq); |
---|
2002 | if ((irq_desc[irq].status & (IRQ_PENDING | IRQ_DISABLED)) |
---|
2003 | == (IRQ_PENDING | IRQ_DISABLED)) |
---|
2004 | mask_IO_APIC_irq(irq); |
---|
2005 | ack_APIC_irq(); |
---|
2006 | } |
---|
2007 | |
---|
2008 | /* |
---|
2009 | * Level triggered interrupts can just be masked, |
---|
2010 | * and shutting down and starting up the interrupt |
---|
2011 | * is the same as enabling and disabling them -- except |
---|
2012 | * with a startup need to return a "was pending" value. |
---|
2013 | * |
---|
2014 | * Level triggered interrupts are special because we |
---|
2015 | * do not touch any IO-APIC register while handling |
---|
2016 | * them. We ack the APIC in the end-IRQ handler, not |
---|
2017 | * in the start-IRQ-handler. Protection against reentrance |
---|
2018 | * from the same interrupt is still provided, both by the |
---|
2019 | * generic IRQ layer and by the fact that an unacked local |
---|
2020 | * APIC does not accept IRQs. |
---|
2021 | */ |
---|
2022 | static unsigned int startup_level_ioapic_irq (unsigned int irq) |
---|
2023 | { |
---|
2024 | unmask_IO_APIC_irq(irq); |
---|
2025 | |
---|
2026 | return 0; /* don't check for pending */ |
---|
2027 | } |
---|
2028 | |
---|
2029 | static void end_level_ioapic_irq (unsigned int irq) |
---|
2030 | { |
---|
2031 | unsigned long v; |
---|
2032 | int i; |
---|
2033 | |
---|
2034 | move_irq(irq); |
---|
2035 | /* |
---|
2036 | * It appears there is an erratum which affects at least version 0x11 |
---|
2037 | * of I/O APIC (that's the 82093AA and cores integrated into various |
---|
2038 | * chipsets). Under certain conditions a level-triggered interrupt is |
---|
2039 | * erroneously delivered as edge-triggered one but the respective IRR |
---|
2040 | * bit gets set nevertheless. As a result the I/O unit expects an EOI |
---|
2041 | * message but it will never arrive and further interrupts are blocked |
---|
2042 | * from the source. The exact reason is so far unknown, but the |
---|
2043 | * phenomenon was observed when two consecutive interrupt requests |
---|
2044 | * from a given source get delivered to the same CPU and the source is |
---|
2045 | * temporarily disabled in between. |
---|
2046 | * |
---|
2047 | * A workaround is to simulate an EOI message manually. We achieve it |
---|
2048 | * by setting the trigger mode to edge and then to level when the edge |
---|
2049 | * trigger mode gets detected in the TMR of a local APIC for a |
---|
2050 | * level-triggered interrupt. We mask the source for the time of the |
---|
2051 | * operation to prevent an edge-triggered interrupt escaping meanwhile. |
---|
2052 | * The idea is from Manfred Spraul. --macro |
---|
2053 | */ |
---|
2054 | i = IO_APIC_VECTOR(irq); |
---|
2055 | |
---|
2056 | v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1)); |
---|
2057 | |
---|
2058 | ack_APIC_irq(); |
---|
2059 | |
---|
2060 | if (!(v & (1 << (i & 0x1f)))) { |
---|
2061 | atomic_inc(&irq_mis_count); |
---|
2062 | spin_lock(&ioapic_lock); |
---|
2063 | __mask_and_edge_IO_APIC_irq(irq); |
---|
2064 | __unmask_and_level_IO_APIC_irq(irq); |
---|
2065 | spin_unlock(&ioapic_lock); |
---|
2066 | } |
---|
2067 | } |
---|
2068 | |
---|
2069 | #ifdef CONFIG_PCI_MSI |
---|
2070 | static unsigned int startup_edge_ioapic_vector(unsigned int vector) |
---|
2071 | { |
---|
2072 | int irq = vector_to_irq(vector); |
---|
2073 | |
---|
2074 | return startup_edge_ioapic_irq(irq); |
---|
2075 | } |
---|
2076 | |
---|
2077 | static void ack_edge_ioapic_vector(unsigned int vector) |
---|
2078 | { |
---|
2079 | int irq = vector_to_irq(vector); |
---|
2080 | |
---|
2081 | move_native_irq(vector); |
---|
2082 | ack_edge_ioapic_irq(irq); |
---|
2083 | } |
---|
2084 | |
---|
2085 | static unsigned int startup_level_ioapic_vector (unsigned int vector) |
---|
2086 | { |
---|
2087 | int irq = vector_to_irq(vector); |
---|
2088 | |
---|
2089 | return startup_level_ioapic_irq (irq); |
---|
2090 | } |
---|
2091 | |
---|
2092 | static void end_level_ioapic_vector (unsigned int vector) |
---|
2093 | { |
---|
2094 | int irq = vector_to_irq(vector); |
---|
2095 | |
---|
2096 | move_native_irq(vector); |
---|
2097 | end_level_ioapic_irq(irq); |
---|
2098 | } |
---|
2099 | |
---|
2100 | static void mask_IO_APIC_vector (unsigned int vector) |
---|
2101 | { |
---|
2102 | int irq = vector_to_irq(vector); |
---|
2103 | |
---|
2104 | mask_IO_APIC_irq(irq); |
---|
2105 | } |
---|
2106 | |
---|
2107 | static void unmask_IO_APIC_vector (unsigned int vector) |
---|
2108 | { |
---|
2109 | int irq = vector_to_irq(vector); |
---|
2110 | |
---|
2111 | unmask_IO_APIC_irq(irq); |
---|
2112 | } |
---|
2113 | |
---|
2114 | #ifdef CONFIG_SMP |
---|
2115 | static void set_ioapic_affinity_vector (unsigned int vector, |
---|
2116 | cpumask_t cpu_mask) |
---|
2117 | { |
---|
2118 | int irq = vector_to_irq(vector); |
---|
2119 | |
---|
2120 | set_native_irq_info(vector, cpu_mask); |
---|
2121 | set_ioapic_affinity_irq(irq, cpu_mask); |
---|
2122 | } |
---|
2123 | #endif |
---|
2124 | #endif |
---|
2125 | |
---|
2126 | static int ioapic_retrigger(unsigned int irq) |
---|
2127 | { |
---|
2128 | send_IPI_self(IO_APIC_VECTOR(irq)); |
---|
2129 | |
---|
2130 | return 1; |
---|
2131 | } |
---|
2132 | |
---|
2133 | /* |
---|
2134 | * Level and edge triggered IO-APIC interrupts need different handling, |
---|
2135 | * so we use two separate IRQ descriptors. Edge triggered IRQs can be |
---|
2136 | * handled with the level-triggered descriptor, but that one has slightly |
---|
2137 | * more overhead. Level-triggered interrupts cannot be handled with the |
---|
2138 | * edge-triggered handler, without risking IRQ storms and other ugly |
---|
2139 | * races. |
---|
2140 | */ |
---|
2141 | static struct hw_interrupt_type ioapic_edge_type __read_mostly = { |
---|
2142 | .typename = "IO-APIC-edge", |
---|
2143 | .startup = startup_edge_ioapic, |
---|
2144 | .shutdown = shutdown_edge_ioapic, |
---|
2145 | .enable = enable_edge_ioapic, |
---|
2146 | .disable = disable_edge_ioapic, |
---|
2147 | .ack = ack_edge_ioapic, |
---|
2148 | .end = end_edge_ioapic, |
---|
2149 | #ifdef CONFIG_SMP |
---|
2150 | .set_affinity = set_ioapic_affinity, |
---|
2151 | #endif |
---|
2152 | .retrigger = ioapic_retrigger, |
---|
2153 | }; |
---|
2154 | |
---|
2155 | static struct hw_interrupt_type ioapic_level_type __read_mostly = { |
---|
2156 | .typename = "IO-APIC-level", |
---|
2157 | .startup = startup_level_ioapic, |
---|
2158 | .shutdown = shutdown_level_ioapic, |
---|
2159 | .enable = enable_level_ioapic, |
---|
2160 | .disable = disable_level_ioapic, |
---|
2161 | .ack = mask_and_ack_level_ioapic, |
---|
2162 | .end = end_level_ioapic, |
---|
2163 | #ifdef CONFIG_SMP |
---|
2164 | .set_affinity = set_ioapic_affinity, |
---|
2165 | #endif |
---|
2166 | .retrigger = ioapic_retrigger, |
---|
2167 | }; |
---|
2168 | #endif /* !CONFIG_XEN */ |
---|
2169 | |
---|
2170 | static inline void init_IO_APIC_traps(void) |
---|
2171 | { |
---|
2172 | int irq; |
---|
2173 | |
---|
2174 | /* |
---|
2175 | * NOTE! The local APIC isn't very good at handling |
---|
2176 | * multiple interrupts at the same interrupt level. |
---|
2177 | * As the interrupt level is determined by taking the |
---|
2178 | * vector number and shifting that right by 4, we |
---|
2179 | * want to spread these out a bit so that they don't |
---|
2180 | * all fall in the same interrupt level. |
---|
2181 | * |
---|
2182 | * Also, we've got to be careful not to trash gate |
---|
2183 | * 0x80, because int 0x80 is hm, kind of importantish. ;) |
---|
2184 | */ |
---|
2185 | for (irq = 0; irq < NR_IRQS ; irq++) { |
---|
2186 | int tmp = irq; |
---|
2187 | if (use_pci_vector()) { |
---|
2188 | if (!platform_legacy_irq(tmp)) |
---|
2189 | if ((tmp = vector_to_irq(tmp)) == -1) |
---|
2190 | continue; |
---|
2191 | } |
---|
2192 | if (IO_APIC_IRQ(tmp) && !IO_APIC_VECTOR(tmp)) { |
---|
2193 | /* |
---|
2194 | * Hmm.. We don't have an entry for this, |
---|
2195 | * so default to an old-fashioned 8259 |
---|
2196 | * interrupt if we can.. |
---|
2197 | */ |
---|
2198 | if (irq < 16) |
---|
2199 | make_8259A_irq(irq); |
---|
2200 | #ifndef CONFIG_XEN |
---|
2201 | else |
---|
2202 | /* Strange. Oh, well.. */ |
---|
2203 | irq_desc[irq].chip = &no_irq_type; |
---|
2204 | #endif |
---|
2205 | } |
---|
2206 | } |
---|
2207 | } |
---|
2208 | |
---|
2209 | #ifndef CONFIG_XEN |
---|
2210 | static void enable_lapic_irq (unsigned int irq) |
---|
2211 | { |
---|
2212 | unsigned long v; |
---|
2213 | |
---|
2214 | v = apic_read(APIC_LVT0); |
---|
2215 | apic_write_around(APIC_LVT0, v & ~APIC_LVT_MASKED); |
---|
2216 | } |
---|
2217 | |
---|
2218 | static void disable_lapic_irq (unsigned int irq) |
---|
2219 | { |
---|
2220 | unsigned long v; |
---|
2221 | |
---|
2222 | v = apic_read(APIC_LVT0); |
---|
2223 | apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED); |
---|
2224 | } |
---|
2225 | |
---|
2226 | static void ack_lapic_irq (unsigned int irq) |
---|
2227 | { |
---|
2228 | ack_APIC_irq(); |
---|
2229 | } |
---|
2230 | |
---|
2231 | static void end_lapic_irq (unsigned int i) { /* nothing */ } |
---|
2232 | |
---|
2233 | static struct hw_interrupt_type lapic_irq_type __read_mostly = { |
---|
2234 | .typename = "local-APIC-edge", |
---|
2235 | .startup = NULL, /* startup_irq() not used for IRQ0 */ |
---|
2236 | .shutdown = NULL, /* shutdown_irq() not used for IRQ0 */ |
---|
2237 | .enable = enable_lapic_irq, |
---|
2238 | .disable = disable_lapic_irq, |
---|
2239 | .ack = ack_lapic_irq, |
---|
2240 | .end = end_lapic_irq |
---|
2241 | }; |
---|
2242 | |
---|
2243 | static void setup_nmi (void) |
---|
2244 | { |
---|
2245 | /* |
---|
2246 | * Dirty trick to enable the NMI watchdog ... |
---|
2247 | * We put the 8259A master into AEOI mode and |
---|
2248 | * unmask on all local APICs LVT0 as NMI. |
---|
2249 | * |
---|
2250 | * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire') |
---|
2251 | * is from Maciej W. Rozycki - so we do not have to EOI from |
---|
2252 | * the NMI handler or the timer interrupt. |
---|
2253 | */ |
---|
2254 | apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ..."); |
---|
2255 | |
---|
2256 | on_each_cpu(enable_NMI_through_LVT0, NULL, 1, 1); |
---|
2257 | |
---|
2258 | apic_printk(APIC_VERBOSE, " done.\n"); |
---|
2259 | } |
---|
2260 | |
---|
2261 | /* |
---|
2262 | * This looks a bit hackish but it's about the only one way of sending |
---|
2263 | * a few INTA cycles to 8259As and any associated glue logic. ICR does |
---|
2264 | * not support the ExtINT mode, unfortunately. We need to send these |
---|
2265 | * cycles as some i82489DX-based boards have glue logic that keeps the |
---|
2266 | * 8259A interrupt line asserted until INTA. --macro |
---|
2267 | */ |
---|
2268 | static inline void unlock_ExtINT_logic(void) |
---|
2269 | { |
---|
2270 | int apic, pin, i; |
---|
2271 | struct IO_APIC_route_entry entry0, entry1; |
---|
2272 | unsigned char save_control, save_freq_select; |
---|
2273 | unsigned long flags; |
---|
2274 | |
---|
2275 | pin = find_isa_irq_pin(8, mp_INT); |
---|
2276 | apic = find_isa_irq_apic(8, mp_INT); |
---|
2277 | if (pin == -1) |
---|
2278 | return; |
---|
2279 | |
---|
2280 | spin_lock_irqsave(&ioapic_lock, flags); |
---|
2281 | *(((int *)&entry0) + 1) = io_apic_read(apic, 0x11 + 2 * pin); |
---|
2282 | *(((int *)&entry0) + 0) = io_apic_read(apic, 0x10 + 2 * pin); |
---|
2283 | spin_unlock_irqrestore(&ioapic_lock, flags); |
---|
2284 | clear_IO_APIC_pin(apic, pin); |
---|
2285 | |
---|
2286 | memset(&entry1, 0, sizeof(entry1)); |
---|
2287 | |
---|
2288 | entry1.dest_mode = 0; /* physical delivery */ |
---|
2289 | entry1.mask = 0; /* unmask IRQ now */ |
---|
2290 | entry1.dest.physical.physical_dest = hard_smp_processor_id(); |
---|
2291 | entry1.delivery_mode = dest_ExtINT; |
---|
2292 | entry1.polarity = entry0.polarity; |
---|
2293 | entry1.trigger = 0; |
---|
2294 | entry1.vector = 0; |
---|
2295 | |
---|
2296 | spin_lock_irqsave(&ioapic_lock, flags); |
---|
2297 | io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry1) + 1)); |
---|
2298 | io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry1) + 0)); |
---|
2299 | spin_unlock_irqrestore(&ioapic_lock, flags); |
---|
2300 | |
---|
2301 | save_control = CMOS_READ(RTC_CONTROL); |
---|
2302 | save_freq_select = CMOS_READ(RTC_FREQ_SELECT); |
---|
2303 | CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6, |
---|
2304 | RTC_FREQ_SELECT); |
---|
2305 | CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL); |
---|
2306 | |
---|
2307 | i = 100; |
---|
2308 | while (i-- > 0) { |
---|
2309 | mdelay(10); |
---|
2310 | if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF) |
---|
2311 | i -= 10; |
---|
2312 | } |
---|
2313 | |
---|
2314 | CMOS_WRITE(save_control, RTC_CONTROL); |
---|
2315 | CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT); |
---|
2316 | clear_IO_APIC_pin(apic, pin); |
---|
2317 | |
---|
2318 | spin_lock_irqsave(&ioapic_lock, flags); |
---|
2319 | io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry0) + 1)); |
---|
2320 | io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry0) + 0)); |
---|
2321 | spin_unlock_irqrestore(&ioapic_lock, flags); |
---|
2322 | } |
---|
2323 | |
---|
2324 | int timer_uses_ioapic_pin_0; |
---|
2325 | |
---|
2326 | /* |
---|
2327 | * This code may look a bit paranoid, but it's supposed to cooperate with |
---|
2328 | * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ |
---|
2329 | * is so screwy. Thanks to Brian Perkins for testing/hacking this beast |
---|
2330 | * fanatically on his truly buggy board. |
---|
2331 | */ |
---|
2332 | static inline void check_timer(void) |
---|
2333 | { |
---|
2334 | int apic1, pin1, apic2, pin2; |
---|
2335 | int vector; |
---|
2336 | |
---|
2337 | /* |
---|
2338 | * get/set the timer IRQ vector: |
---|
2339 | */ |
---|
2340 | disable_8259A_irq(0); |
---|
2341 | vector = assign_irq_vector(0); |
---|
2342 | set_intr_gate(vector, interrupt[0]); |
---|
2343 | |
---|
2344 | /* |
---|
2345 | * Subtle, code in do_timer_interrupt() expects an AEOI |
---|
2346 | * mode for the 8259A whenever interrupts are routed |
---|
2347 | * through I/O APICs. Also IRQ0 has to be enabled in |
---|
2348 | * the 8259A which implies the virtual wire has to be |
---|
2349 | * disabled in the local APIC. |
---|
2350 | */ |
---|
2351 | apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT); |
---|
2352 | init_8259A(1); |
---|
2353 | timer_ack = 1; |
---|
2354 | if (timer_over_8254 > 0) |
---|
2355 | enable_8259A_irq(0); |
---|
2356 | |
---|
2357 | pin1 = find_isa_irq_pin(0, mp_INT); |
---|
2358 | apic1 = find_isa_irq_apic(0, mp_INT); |
---|
2359 | pin2 = ioapic_i8259.pin; |
---|
2360 | apic2 = ioapic_i8259.apic; |
---|
2361 | |
---|
2362 | if (pin1 == 0) |
---|
2363 | timer_uses_ioapic_pin_0 = 1; |
---|
2364 | |
---|
2365 | printk(KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n", |
---|
2366 | vector, apic1, pin1, apic2, pin2); |
---|
2367 | |
---|
2368 | if (pin1 != -1) { |
---|
2369 | /* |
---|
2370 | * Ok, does IRQ0 through the IOAPIC work? |
---|
2371 | */ |
---|
2372 | unmask_IO_APIC_irq(0); |
---|
2373 | if (timer_irq_works()) { |
---|
2374 | if (nmi_watchdog == NMI_IO_APIC) { |
---|
2375 | disable_8259A_irq(0); |
---|
2376 | setup_nmi(); |
---|
2377 | enable_8259A_irq(0); |
---|
2378 | } |
---|
2379 | if (disable_timer_pin_1 > 0) |
---|
2380 | clear_IO_APIC_pin(0, pin1); |
---|
2381 | return; |
---|
2382 | } |
---|
2383 | clear_IO_APIC_pin(apic1, pin1); |
---|
2384 | printk(KERN_ERR "..MP-BIOS bug: 8254 timer not connected to " |
---|
2385 | "IO-APIC\n"); |
---|
2386 | } |
---|
2387 | |
---|
2388 | printk(KERN_INFO "...trying to set up timer (IRQ0) through the 8259A ... "); |
---|
2389 | if (pin2 != -1) { |
---|
2390 | printk("\n..... (found pin %d) ...", pin2); |
---|
2391 | /* |
---|
2392 | * legacy devices should be connected to IO APIC #0 |
---|
2393 | */ |
---|
2394 | setup_ExtINT_IRQ0_pin(apic2, pin2, vector); |
---|
2395 | if (timer_irq_works()) { |
---|
2396 | printk("works.\n"); |
---|
2397 | if (pin1 != -1) |
---|
2398 | replace_pin_at_irq(0, apic1, pin1, apic2, pin2); |
---|
2399 | else |
---|
2400 | add_pin_to_irq(0, apic2, pin2); |
---|
2401 | if (nmi_watchdog == NMI_IO_APIC) { |
---|
2402 | setup_nmi(); |
---|
2403 | } |
---|
2404 | return; |
---|
2405 | } |
---|
2406 | /* |
---|
2407 | * Cleanup, just in case ... |
---|
2408 | */ |
---|
2409 | clear_IO_APIC_pin(apic2, pin2); |
---|
2410 | } |
---|
2411 | printk(" failed.\n"); |
---|
2412 | |
---|
2413 | if (nmi_watchdog == NMI_IO_APIC) { |
---|
2414 | printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n"); |
---|
2415 | nmi_watchdog = 0; |
---|
2416 | } |
---|
2417 | |
---|
2418 | printk(KERN_INFO "...trying to set up timer as Virtual Wire IRQ..."); |
---|
2419 | |
---|
2420 | disable_8259A_irq(0); |
---|
2421 | irq_desc[0].chip = &lapic_irq_type; |
---|
2422 | apic_write_around(APIC_LVT0, APIC_DM_FIXED | vector); /* Fixed mode */ |
---|
2423 | enable_8259A_irq(0); |
---|
2424 | |
---|
2425 | if (timer_irq_works()) { |
---|
2426 | printk(" works.\n"); |
---|
2427 | return; |
---|
2428 | } |
---|
2429 | apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector); |
---|
2430 | printk(" failed.\n"); |
---|
2431 | |
---|
2432 | printk(KERN_INFO "...trying to set up timer as ExtINT IRQ..."); |
---|
2433 | |
---|
2434 | timer_ack = 0; |
---|
2435 | init_8259A(0); |
---|
2436 | make_8259A_irq(0); |
---|
2437 | apic_write_around(APIC_LVT0, APIC_DM_EXTINT); |
---|
2438 | |
---|
2439 | unlock_ExtINT_logic(); |
---|
2440 | |
---|
2441 | if (timer_irq_works()) { |
---|
2442 | printk(" works.\n"); |
---|
2443 | return; |
---|
2444 | } |
---|
2445 | printk(" failed :(.\n"); |
---|
2446 | panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a " |
---|
2447 | "report. Then try booting with the 'noapic' option"); |
---|
2448 | } |
---|
2449 | #else |
---|
2450 | int timer_uses_ioapic_pin_0 = 0; |
---|
2451 | #define check_timer() ((void)0) |
---|
2452 | #endif |
---|
2453 | |
---|
2454 | /* |
---|
2455 | * |
---|
2456 | * IRQ's that are handled by the PIC in the MPS IOAPIC case. |
---|
2457 | * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ. |
---|
2458 | * Linux doesn't really care, as it's not actually used |
---|
2459 | * for any interrupt handling anyway. |
---|
2460 | */ |
---|
2461 | #define PIC_IRQS (1 << PIC_CASCADE_IR) |
---|
2462 | |
---|
2463 | void __init setup_IO_APIC(void) |
---|
2464 | { |
---|
2465 | enable_IO_APIC(); |
---|
2466 | |
---|
2467 | if (acpi_ioapic) |
---|
2468 | io_apic_irqs = ~0; /* all IRQs go through IOAPIC */ |
---|
2469 | else |
---|
2470 | io_apic_irqs = ~PIC_IRQS; |
---|
2471 | |
---|
2472 | printk("ENABLING IO-APIC IRQs\n"); |
---|
2473 | |
---|
2474 | /* |
---|
2475 | * Set up IO-APIC IRQ routing. |
---|
2476 | */ |
---|
2477 | if (!acpi_ioapic) |
---|
2478 | setup_ioapic_ids_from_mpc(); |
---|
2479 | #ifndef CONFIG_XEN |
---|
2480 | sync_Arb_IDs(); |
---|
2481 | #endif |
---|
2482 | setup_IO_APIC_irqs(); |
---|
2483 | init_IO_APIC_traps(); |
---|
2484 | check_timer(); |
---|
2485 | if (!acpi_ioapic) |
---|
2486 | print_IO_APIC(); |
---|
2487 | } |
---|
2488 | |
---|
2489 | static int __init setup_disable_8254_timer(char *s) |
---|
2490 | { |
---|
2491 | timer_over_8254 = -1; |
---|
2492 | return 1; |
---|
2493 | } |
---|
2494 | static int __init setup_enable_8254_timer(char *s) |
---|
2495 | { |
---|
2496 | timer_over_8254 = 2; |
---|
2497 | return 1; |
---|
2498 | } |
---|
2499 | |
---|
2500 | __setup("disable_8254_timer", setup_disable_8254_timer); |
---|
2501 | __setup("enable_8254_timer", setup_enable_8254_timer); |
---|
2502 | |
---|
2503 | /* |
---|
2504 | * Called after all the initialization is done. If we didnt find any |
---|
2505 | * APIC bugs then we can allow the modify fast path |
---|
2506 | */ |
---|
2507 | |
---|
2508 | static int __init io_apic_bug_finalize(void) |
---|
2509 | { |
---|
2510 | if(sis_apic_bug == -1) |
---|
2511 | sis_apic_bug = 0; |
---|
2512 | if (is_initial_xendomain()) { |
---|
2513 | struct xen_platform_op op = { .cmd = XENPF_platform_quirk }; |
---|
2514 | op.u.platform_quirk.quirk_id = sis_apic_bug ? |
---|
2515 | QUIRK_IOAPIC_BAD_REGSEL : QUIRK_IOAPIC_GOOD_REGSEL; |
---|
2516 | HYPERVISOR_platform_op(&op); |
---|
2517 | } |
---|
2518 | return 0; |
---|
2519 | } |
---|
2520 | |
---|
2521 | late_initcall(io_apic_bug_finalize); |
---|
2522 | |
---|
2523 | struct sysfs_ioapic_data { |
---|
2524 | struct sys_device dev; |
---|
2525 | struct IO_APIC_route_entry entry[0]; |
---|
2526 | }; |
---|
2527 | static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS]; |
---|
2528 | |
---|
2529 | static int ioapic_suspend(struct sys_device *dev, pm_message_t state) |
---|
2530 | { |
---|
2531 | struct IO_APIC_route_entry *entry; |
---|
2532 | struct sysfs_ioapic_data *data; |
---|
2533 | unsigned long flags; |
---|
2534 | int i; |
---|
2535 | |
---|
2536 | data = container_of(dev, struct sysfs_ioapic_data, dev); |
---|
2537 | entry = data->entry; |
---|
2538 | spin_lock_irqsave(&ioapic_lock, flags); |
---|
2539 | for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) { |
---|
2540 | *(((int *)entry) + 1) = io_apic_read(dev->id, 0x11 + 2 * i); |
---|
2541 | *(((int *)entry) + 0) = io_apic_read(dev->id, 0x10 + 2 * i); |
---|
2542 | } |
---|
2543 | spin_unlock_irqrestore(&ioapic_lock, flags); |
---|
2544 | |
---|
2545 | return 0; |
---|
2546 | } |
---|
2547 | |
---|
2548 | static int ioapic_resume(struct sys_device *dev) |
---|
2549 | { |
---|
2550 | struct IO_APIC_route_entry *entry; |
---|
2551 | struct sysfs_ioapic_data *data; |
---|
2552 | unsigned long flags; |
---|
2553 | union IO_APIC_reg_00 reg_00; |
---|
2554 | int i; |
---|
2555 | |
---|
2556 | data = container_of(dev, struct sysfs_ioapic_data, dev); |
---|
2557 | entry = data->entry; |
---|
2558 | |
---|
2559 | spin_lock_irqsave(&ioapic_lock, flags); |
---|
2560 | reg_00.raw = io_apic_read(dev->id, 0); |
---|
2561 | if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) { |
---|
2562 | reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid; |
---|
2563 | io_apic_write(dev->id, 0, reg_00.raw); |
---|
2564 | } |
---|
2565 | for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) { |
---|
2566 | io_apic_write(dev->id, 0x11+2*i, *(((int *)entry)+1)); |
---|
2567 | io_apic_write(dev->id, 0x10+2*i, *(((int *)entry)+0)); |
---|
2568 | } |
---|
2569 | spin_unlock_irqrestore(&ioapic_lock, flags); |
---|
2570 | |
---|
2571 | return 0; |
---|
2572 | } |
---|
2573 | |
---|
2574 | static struct sysdev_class ioapic_sysdev_class = { |
---|
2575 | set_kset_name("ioapic"), |
---|
2576 | .suspend = ioapic_suspend, |
---|
2577 | .resume = ioapic_resume, |
---|
2578 | }; |
---|
2579 | |
---|
2580 | static int __init ioapic_init_sysfs(void) |
---|
2581 | { |
---|
2582 | struct sys_device * dev; |
---|
2583 | int i, size, error = 0; |
---|
2584 | |
---|
2585 | error = sysdev_class_register(&ioapic_sysdev_class); |
---|
2586 | if (error) |
---|
2587 | return error; |
---|
2588 | |
---|
2589 | for (i = 0; i < nr_ioapics; i++ ) { |
---|
2590 | size = sizeof(struct sys_device) + nr_ioapic_registers[i] |
---|
2591 | * sizeof(struct IO_APIC_route_entry); |
---|
2592 | mp_ioapic_data[i] = kmalloc(size, GFP_KERNEL); |
---|
2593 | if (!mp_ioapic_data[i]) { |
---|
2594 | printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i); |
---|
2595 | continue; |
---|
2596 | } |
---|
2597 | memset(mp_ioapic_data[i], 0, size); |
---|
2598 | dev = &mp_ioapic_data[i]->dev; |
---|
2599 | dev->id = i; |
---|
2600 | dev->cls = &ioapic_sysdev_class; |
---|
2601 | error = sysdev_register(dev); |
---|
2602 | if (error) { |
---|
2603 | kfree(mp_ioapic_data[i]); |
---|
2604 | mp_ioapic_data[i] = NULL; |
---|
2605 | printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i); |
---|
2606 | continue; |
---|
2607 | } |
---|
2608 | } |
---|
2609 | |
---|
2610 | return 0; |
---|
2611 | } |
---|
2612 | |
---|
2613 | device_initcall(ioapic_init_sysfs); |
---|
2614 | |
---|
2615 | /* -------------------------------------------------------------------------- |
---|
2616 | ACPI-based IOAPIC Configuration |
---|
2617 | -------------------------------------------------------------------------- */ |
---|
2618 | |
---|
2619 | #ifdef CONFIG_ACPI |
---|
2620 | |
---|
2621 | int __init io_apic_get_unique_id (int ioapic, int apic_id) |
---|
2622 | { |
---|
2623 | #ifndef CONFIG_XEN |
---|
2624 | union IO_APIC_reg_00 reg_00; |
---|
2625 | static physid_mask_t apic_id_map = PHYSID_MASK_NONE; |
---|
2626 | physid_mask_t tmp; |
---|
2627 | unsigned long flags; |
---|
2628 | int i = 0; |
---|
2629 | |
---|
2630 | /* |
---|
2631 | * The P4 platform supports up to 256 APIC IDs on two separate APIC |
---|
2632 | * buses (one for LAPICs, one for IOAPICs), where predecessors only |
---|
2633 | * supports up to 16 on one shared APIC bus. |
---|
2634 | * |
---|
2635 | * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full |
---|
2636 | * advantage of new APIC bus architecture. |
---|
2637 | */ |
---|
2638 | |
---|
2639 | if (physids_empty(apic_id_map)) |
---|
2640 | apic_id_map = ioapic_phys_id_map(phys_cpu_present_map); |
---|
2641 | |
---|
2642 | spin_lock_irqsave(&ioapic_lock, flags); |
---|
2643 | reg_00.raw = io_apic_read(ioapic, 0); |
---|
2644 | spin_unlock_irqrestore(&ioapic_lock, flags); |
---|
2645 | |
---|
2646 | if (apic_id >= get_physical_broadcast()) { |
---|
2647 | printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying " |
---|
2648 | "%d\n", ioapic, apic_id, reg_00.bits.ID); |
---|
2649 | apic_id = reg_00.bits.ID; |
---|
2650 | } |
---|
2651 | |
---|
2652 | /* |
---|
2653 | * Every APIC in a system must have a unique ID or we get lots of nice |
---|
2654 | * 'stuck on smp_invalidate_needed IPI wait' messages. |
---|
2655 | */ |
---|
2656 | if (check_apicid_used(apic_id_map, apic_id)) { |
---|
2657 | |
---|
2658 | for (i = 0; i < get_physical_broadcast(); i++) { |
---|
2659 | if (!check_apicid_used(apic_id_map, i)) |
---|
2660 | break; |
---|
2661 | } |
---|
2662 | |
---|
2663 | if (i == get_physical_broadcast()) |
---|
2664 | panic("Max apic_id exceeded!\n"); |
---|
2665 | |
---|
2666 | printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, " |
---|
2667 | "trying %d\n", ioapic, apic_id, i); |
---|
2668 | |
---|
2669 | apic_id = i; |
---|
2670 | } |
---|
2671 | |
---|
2672 | tmp = apicid_to_cpu_present(apic_id); |
---|
2673 | physids_or(apic_id_map, apic_id_map, tmp); |
---|
2674 | |
---|
2675 | if (reg_00.bits.ID != apic_id) { |
---|
2676 | reg_00.bits.ID = apic_id; |
---|
2677 | |
---|
2678 | spin_lock_irqsave(&ioapic_lock, flags); |
---|
2679 | io_apic_write(ioapic, 0, reg_00.raw); |
---|
2680 | reg_00.raw = io_apic_read(ioapic, 0); |
---|
2681 | spin_unlock_irqrestore(&ioapic_lock, flags); |
---|
2682 | |
---|
2683 | /* Sanity check */ |
---|
2684 | if (reg_00.bits.ID != apic_id) { |
---|
2685 | printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic); |
---|
2686 | return -1; |
---|
2687 | } |
---|
2688 | } |
---|
2689 | |
---|
2690 | apic_printk(APIC_VERBOSE, KERN_INFO |
---|
2691 | "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id); |
---|
2692 | #endif /* !CONFIG_XEN */ |
---|
2693 | |
---|
2694 | return apic_id; |
---|
2695 | } |
---|
2696 | |
---|
2697 | |
---|
2698 | int __init io_apic_get_version (int ioapic) |
---|
2699 | { |
---|
2700 | union IO_APIC_reg_01 reg_01; |
---|
2701 | unsigned long flags; |
---|
2702 | |
---|
2703 | spin_lock_irqsave(&ioapic_lock, flags); |
---|
2704 | reg_01.raw = io_apic_read(ioapic, 1); |
---|
2705 | spin_unlock_irqrestore(&ioapic_lock, flags); |
---|
2706 | |
---|
2707 | return reg_01.bits.version; |
---|
2708 | } |
---|
2709 | |
---|
2710 | |
---|
2711 | int __init io_apic_get_redir_entries (int ioapic) |
---|
2712 | { |
---|
2713 | union IO_APIC_reg_01 reg_01; |
---|
2714 | unsigned long flags; |
---|
2715 | |
---|
2716 | spin_lock_irqsave(&ioapic_lock, flags); |
---|
2717 | reg_01.raw = io_apic_read(ioapic, 1); |
---|
2718 | spin_unlock_irqrestore(&ioapic_lock, flags); |
---|
2719 | |
---|
2720 | return reg_01.bits.entries; |
---|
2721 | } |
---|
2722 | |
---|
2723 | |
---|
2724 | int io_apic_set_pci_routing (int ioapic, int pin, int irq, int edge_level, int active_high_low) |
---|
2725 | { |
---|
2726 | struct IO_APIC_route_entry entry; |
---|
2727 | unsigned long flags; |
---|
2728 | |
---|
2729 | if (!IO_APIC_IRQ(irq)) { |
---|
2730 | printk(KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n", |
---|
2731 | ioapic); |
---|
2732 | return -EINVAL; |
---|
2733 | } |
---|
2734 | |
---|
2735 | /* |
---|
2736 | * Generate a PCI IRQ routing entry and program the IOAPIC accordingly. |
---|
2737 | * Note that we mask (disable) IRQs now -- these get enabled when the |
---|
2738 | * corresponding device driver registers for this IRQ. |
---|
2739 | */ |
---|
2740 | |
---|
2741 | memset(&entry,0,sizeof(entry)); |
---|
2742 | |
---|
2743 | entry.delivery_mode = INT_DELIVERY_MODE; |
---|
2744 | entry.dest_mode = INT_DEST_MODE; |
---|
2745 | entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS); |
---|
2746 | entry.trigger = edge_level; |
---|
2747 | entry.polarity = active_high_low; |
---|
2748 | entry.mask = 1; |
---|
2749 | |
---|
2750 | /* |
---|
2751 | * IRQs < 16 are already in the irq_2_pin[] map |
---|
2752 | */ |
---|
2753 | if (irq >= 16) |
---|
2754 | add_pin_to_irq(irq, ioapic, pin); |
---|
2755 | |
---|
2756 | entry.vector = assign_irq_vector(irq); |
---|
2757 | |
---|
2758 | apic_printk(APIC_DEBUG, KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry " |
---|
2759 | "(%d-%d -> 0x%x -> IRQ %d Mode:%i Active:%i)\n", ioapic, |
---|
2760 | mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq, |
---|
2761 | edge_level, active_high_low); |
---|
2762 | |
---|
2763 | ioapic_register_intr(irq, entry.vector, edge_level); |
---|
2764 | |
---|
2765 | if (!ioapic && (irq < 16)) |
---|
2766 | disable_8259A_irq(irq); |
---|
2767 | |
---|
2768 | spin_lock_irqsave(&ioapic_lock, flags); |
---|
2769 | io_apic_write(ioapic, 0x11+2*pin, *(((int *)&entry)+1)); |
---|
2770 | io_apic_write(ioapic, 0x10+2*pin, *(((int *)&entry)+0)); |
---|
2771 | set_native_irq_info(use_pci_vector() ? entry.vector : irq, TARGET_CPUS); |
---|
2772 | spin_unlock_irqrestore(&ioapic_lock, flags); |
---|
2773 | |
---|
2774 | return 0; |
---|
2775 | } |
---|
2776 | |
---|
2777 | #endif /* CONFIG_ACPI */ |
---|