1 | /* |
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2 | * Done by Dietmar Hahn <dietmar.hahn@fujitsu-siemens.com> |
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3 | * This code is mostly taken from FreeBSD. |
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4 | * |
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5 | * |
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6 | **************************************************************************** |
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7 | * Copyright (c) 2000 Doug Rabson |
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8 | * All rights reserved. |
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9 | * |
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10 | * Redistribution and use in source and binary forms, with or without |
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11 | * modification, are permitted provided that the following conditions |
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12 | * are met: |
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13 | * 1. Redistributions of source code must retain the above copyright |
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14 | * notice, this list of conditions and the following disclaimer. |
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15 | * 2. Redistributions in binary form must reproduce the above copyright |
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16 | * notice, this list of conditions and the following disclaimer in the |
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17 | * documentation and/or other materials provided with the distribution. |
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18 | * |
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19 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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20 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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21 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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22 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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23 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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24 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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25 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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26 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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27 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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28 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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29 | * SUCH DAMAGE. |
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30 | * |
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31 | */ |
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32 | |
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33 | #ifndef _IA64_CPU_H_ |
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34 | #define _IA64_CPU_H_ |
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35 | |
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36 | #include "ia64_fpu.h" |
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37 | |
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38 | /* |
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39 | * Definition of Region Register bits (RR) |
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40 | * |
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41 | * RR bit field positions |
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42 | */ |
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43 | #define IA64_RR_VE 0 |
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44 | #define IA64_RR_MBZ0 1 |
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45 | #define IA64_RR_PS 2 |
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46 | #define IA64_RR_PS_LEN 6 |
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47 | #define IA64_RR_RID 8 |
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48 | #define IA64_RR_RID_LEN 24 |
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49 | #define IA64_RR_MBZ1 32 |
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50 | |
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51 | #define IA64_RR_IDX_POS 61 |
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52 | |
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53 | #define IA64_RR_VAL(size,rid) (((size) << IA64_RR_PS) | ((rid) << IA64_RR_RID)) |
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54 | |
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55 | /* |
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56 | * Define Protection Key Register (PKR) |
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57 | * |
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58 | * PKR bit field positions |
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59 | */ |
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60 | #define IA64_PKR_V 0 |
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61 | #define IA64_PKR_WD 1 |
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62 | #define IA64_PKR_RD 2 |
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63 | #define IA64_PKR_XD 3 |
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64 | #define IA64_PKR_MBZ0 4 |
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65 | #define IA64_PKR_KEY 8 |
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66 | #define IA64_PKR_KEY_LEN 24 |
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67 | #define IA64_PKR_MBZ1 32 |
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68 | |
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69 | #define IA64_PKR_VALID (1 << IA64_PKR_V) |
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70 | |
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71 | |
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72 | /* |
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73 | * ITIR bit field positions |
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74 | */ |
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75 | |
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76 | #define IA64_ITIR_MBZ0 0 |
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77 | #define IA64_ITIR_PS 2 |
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78 | #define IA64_ITIR_PS_LEN 6 |
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79 | #define IA64_ITIR_KEY 8 |
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80 | #define IA64_ITIR_KEY_LEN 24 |
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81 | #define IA64_ITIR_MBZ1 32 |
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82 | #define IA64_ITIR_MBZ1_LEN 16 |
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83 | #define IA64_ITIR_PPN 48 |
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84 | #define IA64_ITIR_PPN_LEN 15 |
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85 | #define IA64_ITIR_MBZ2 63 |
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86 | |
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87 | /* |
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88 | * Definition of PSR and IPSR bits. |
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89 | */ |
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90 | #define IA64_PSR_BE 0x0000000000000002 |
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91 | #define IA64_PSR_UP 0x0000000000000004 |
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92 | #define IA64_PSR_AC 0x0000000000000008 |
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93 | #define IA64_PSR_MFL 0x0000000000000010 |
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94 | #define IA64_PSR_MFH_BIT 5 |
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95 | #define IA64_PSR_MFH (1 << IA64_PSR_MFH_BIT) |
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96 | #define IA64_PSR_UMASK (IA64_PSR_BE | IA64_PSR_UP | \ |
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97 | IA64_PSR_AC | IA64_PSR_MFL | \ |
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98 | IA64_PSR_MFH) |
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99 | #define IA64_PSR_IC_BIT 13 |
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100 | #define IA64_PSR_IC (1<<IA64_PSR_IC_BIT) /*0x0000000000002000*/ |
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101 | #define IA64_PSR_I_BIT 14 |
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102 | #define IA64_PSR_I (1<<IA64_PSR_I_BIT) /*0x0000000000004000*/ |
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103 | #define IA64_PSR_PK 0x0000000000008000 |
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104 | #define IA64_PSR_DT 0x0000000000020000 |
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105 | #define IA64_PSR_DFL 0x0000000000040000 |
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106 | #define IA64_PSR_DFH 0x0000000000080000 |
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107 | #define IA64_PSR_SP 0x0000000000100000 |
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108 | #define IA64_PSR_PP 0x0000000000200000 |
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109 | #define IA64_PSR_DI 0x0000000000400000 |
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110 | #define IA64_PSR_SI 0x0000000000800000 |
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111 | #define IA64_PSR_DB 0x0000000001000000 |
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112 | #define IA64_PSR_LP 0x0000000002000000 |
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113 | #define IA64_PSR_TB 0x0000000004000000 |
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114 | #define IA64_PSR_RT 0x0000000008000000 |
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115 | #define IA64_PSR_CPL 0x0000000300000000 |
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116 | #define IA64_PSR_CPL_KERN 0x0000000000000000 |
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117 | #define IA64_PSR_CPL_1 0x0000000100000000 |
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118 | #define IA64_PSR_CPL_2 0x0000000200000000 |
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119 | #define IA64_PSR_CPL_USER 0x0000000300000000 |
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120 | #define IA64_PSR_IS 0x0000000400000000 |
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121 | #define IA64_PSR_MC 0x0000000800000000 |
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122 | #define IA64_PSR_IT 0x0000001000000000 |
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123 | #define IA64_PSR_ID 0x0000002000000000 |
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124 | #define IA64_PSR_DA 0x0000004000000000 |
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125 | #define IA64_PSR_DD 0x0000008000000000 |
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126 | #define IA64_PSR_SS 0x0000010000000000 |
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127 | #define IA64_PSR_RI 0x0000060000000000 |
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128 | #define IA64_PSR_RI_0 0x0000000000000000 |
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129 | #define IA64_PSR_RI_1 0x0000020000000000 |
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130 | #define IA64_PSR_RI_2 0x0000040000000000 |
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131 | #define IA64_PSR_RI_SHIFT 41 |
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132 | #define IA64_PSR_ED 0x0000080000000000 |
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133 | #define IA64_PSR_BN 0x0000100000000000 |
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134 | #define IA64_PSR_IA 0x0000200000000000 |
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135 | |
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136 | |
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137 | /* Endianess of mini-os. */ |
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138 | #if defined(BIG_ENDIAN) |
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139 | #define MOS_IA64_PSR_BE IA64_PSR_BE |
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140 | #else |
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141 | #define MOS_IA64_PSR_BE 0 |
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142 | #endif |
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143 | |
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144 | #define STARTUP_PSR (IA64_PSR_IT | \ |
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145 | IA64_PSR_DT | IA64_PSR_RT | MOS_IA64_PSR_BE | \ |
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146 | IA64_PSR_BN | IA64_PSR_CPL_2 | IA64_PSR_AC) |
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147 | |
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148 | #define MOS_SYS_PSR (IA64_PSR_IC | IA64_PSR_I | IA64_PSR_IT | \ |
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149 | IA64_PSR_DT | IA64_PSR_RT | MOS_IA64_PSR_BE | \ |
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150 | IA64_PSR_BN | IA64_PSR_CPL_2 | IA64_PSR_AC) |
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151 | |
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152 | #define MOS_USR_PSR (IA64_PSR_IC | IA64_PSR_I | IA64_PSR_IT | \ |
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153 | IA64_PSR_DT | IA64_PSR_RT | MOS_IA64_PSR_BE | \ |
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154 | IA64_PSR_BN | IA64_PSR_CPL_USER | IA64_PSR_AC) |
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155 | |
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156 | /* |
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157 | * Definition of ISR bits. |
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158 | */ |
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159 | #define IA64_ISR_CODE 0x000000000000ffff |
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160 | #define IA64_ISR_VECTOR 0x0000000000ff0000 |
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161 | #define IA64_ISR_X 0x0000000100000000 |
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162 | #define IA64_ISR_W 0x0000000200000000 |
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163 | #define IA64_ISR_R 0x0000000400000000 |
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164 | #define IA64_ISR_NA 0x0000000800000000 |
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165 | #define IA64_ISR_SP 0x0000001000000000 |
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166 | #define IA64_ISR_RS 0x0000002000000000 |
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167 | #define IA64_ISR_IR 0x0000004000000000 |
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168 | #define IA64_ISR_NI 0x0000008000000000 |
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169 | #define IA64_ISR_SO 0x0000010000000000 |
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170 | #define IA64_ISR_EI 0x0000060000000000 |
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171 | #define IA64_ISR_EI_0 0x0000000000000000 |
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172 | #define IA64_ISR_EI_1 0x0000020000000000 |
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173 | #define IA64_ISR_EI_2 0x0000040000000000 |
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174 | #define IA64_ISR_ED 0x0000080000000000 |
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175 | |
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176 | /* |
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177 | * DCR bit positions |
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178 | */ |
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179 | #define IA64_DCR_PP 0 |
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180 | #define IA64_DCR_BE 1 |
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181 | #define IA64_DCR_LC 2 |
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182 | #define IA64_DCR_MBZ0 4 |
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183 | #define IA64_DCR_MBZ0_V 0xf |
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184 | #define IA64_DCR_DM 8 |
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185 | #define IA64_DCR_DP 9 |
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186 | #define IA64_DCR_DK 10 |
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187 | #define IA64_DCR_DX 11 |
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188 | #define IA64_DCR_DR 12 |
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189 | #define IA64_DCR_DA 13 |
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190 | #define IA64_DCR_DD 14 |
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191 | #define IA64_DCR_DEFER_ALL 0x7f00 |
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192 | #define IA64_DCR_MBZ1 2 |
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193 | #define IA64_DCR_MBZ1_V 0xffffffffffffULL |
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194 | |
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195 | |
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196 | /* Endianess of DCR register. */ |
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197 | #if defined(BIG_ENDIAN) |
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198 | #define MOS_IA64_DCR_BE (1 << IA64_DCR_BE) |
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199 | #else |
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200 | #define MOS_IA64_DCR_BE (0 << IA64_DCR_BE) |
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201 | #endif |
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202 | |
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203 | #define IA64_DCR_DEFAULT (MOS_IA64_DCR_BE) |
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204 | |
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205 | /* |
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206 | * Vector numbers for various ia64 interrupts. |
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207 | */ |
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208 | #define IA64_VEC_VHPT 0 |
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209 | #define IA64_VEC_ITLB 1 |
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210 | #define IA64_VEC_DTLB 2 |
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211 | #define IA64_VEC_ALT_ITLB 3 |
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212 | #define IA64_VEC_ALT_DTLB 4 |
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213 | #define IA64_VEC_NESTED_DTLB 5 |
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214 | #define IA64_VEC_IKEY_MISS 6 |
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215 | #define IA64_VEC_DKEY_MISS 7 |
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216 | #define IA64_VEC_DIRTY_BIT 8 |
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217 | #define IA64_VEC_INST_ACCESS 9 |
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218 | #define IA64_VEC_DATA_ACCESS 10 |
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219 | #define IA64_VEC_BREAK 11 |
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220 | #define IA64_VEC_EXT_INTR 12 |
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221 | #define IA64_VEC_PAGE_NOT_PRESENT 20 |
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222 | #define IA64_VEC_KEY_PERMISSION 21 |
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223 | #define IA64_VEC_INST_ACCESS_RIGHTS 22 |
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224 | #define IA64_VEC_DATA_ACCESS_RIGHTS 23 |
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225 | #define IA64_VEC_GENERAL_EXCEPTION 24 |
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226 | #define IA64_VEC_DISABLED_FP 25 |
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227 | #define IA64_VEC_NAT_CONSUMPTION 26 |
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228 | #define IA64_VEC_SPECULATION 27 |
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229 | #define IA64_VEC_DEBUG 29 |
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230 | #define IA64_VEC_UNALIGNED_REFERENCE 30 |
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231 | #define IA64_VEC_UNSUPP_DATA_REFERENCE 31 |
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232 | #define IA64_VEC_FLOATING_POINT_FAULT 32 |
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233 | #define IA64_VEC_FLOATING_POINT_TRAP 33 |
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234 | #define IA64_VEC_LOWER_PRIVILEGE_TRANSFER 34 |
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235 | #define IA64_VEC_TAKEN_BRANCH_TRAP 35 |
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236 | #define IA64_VEC_SINGLE_STEP_TRAP 36 |
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237 | #define IA64_VEC_IA32_EXCEPTION 45 |
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238 | #define IA64_VEC_IA32_INTERCEPT 46 |
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239 | #define IA64_VEC_IA32_INTERRUPT 47 |
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240 | |
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241 | /* |
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242 | * Define hardware RSE Configuration Register |
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243 | * |
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244 | * RS Configuration (RSC) bit field positions |
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245 | */ |
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246 | |
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247 | #define IA64_RSC_MODE 0 |
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248 | #define IA64_RSC_PL 2 |
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249 | #define IA64_RSC_BE 4 |
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250 | #define IA64_RSC_MBZ0 5 |
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251 | #define IA64_RSC_MBZ0_V 0x3ff |
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252 | #define IA64_RSC_LOADRS 16 |
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253 | #define IA64_RSC_LOADRS_LEN 14 |
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254 | #define IA64_RSC_MBZ1 30 |
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255 | #define IA64_RSC_MBZ1_V 0x3ffffffffULL |
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256 | |
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257 | /* |
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258 | * RSC modes |
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259 | */ |
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260 | #define IA64_RSC_MODE_LY (0x0) /* Lazy */ |
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261 | #define IA64_RSC_MODE_SI (0x1) /* Store intensive */ |
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262 | #define IA64_RSC_MODE_LI (0x2) /* Load intensive */ |
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263 | #define IA64_RSC_MODE_EA (0x3) /* Eager */ |
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264 | |
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265 | /* RSE endian mode. */ |
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266 | #if defined(BIG_ENDIAN) |
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267 | #define MOS_IA64_RSC_BE 1 /* Big endian rse. */ |
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268 | #else |
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269 | #define MOS_IA64_RSC_BE 0 /* Little endian rse. */ |
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270 | #endif |
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271 | |
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272 | #define IA64_RSE_EAGER ((IA64_RSC_MODE_EA<<IA64_RSC_MODE) | \ |
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273 | (MOS_IA64_RSC_BE << IA64_RSC_BE) ) |
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274 | |
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275 | #define IA64_RSE_LAZY ((IA64_RSC_MODE_LY<<IA64_RSC_MODE) | \ |
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276 | (MOS_IA64_RSC_BE << IA64_RSC_BE) ) |
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277 | |
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278 | |
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279 | |
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280 | #ifndef __ASSEMBLY__ |
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281 | |
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282 | /* ia64 function descriptor and global pointer */ |
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283 | struct ia64_fdesc |
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284 | { |
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285 | uint64_t func; |
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286 | uint64_t gp; |
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287 | }; |
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288 | typedef struct ia64_fdesc ia64_fdesc_t; |
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289 | |
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290 | #define FDESC_FUNC(fn) (((struct ia64_fdesc *) fn)->func) |
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291 | #define FDESC_GP(fn) (((struct ia64_fdesc *) fn)->gp) |
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292 | |
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293 | |
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294 | /* |
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295 | * Various special ia64 instructions. |
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296 | */ |
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297 | |
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298 | /* |
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299 | * Memory Fence. |
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300 | */ |
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301 | static __inline void |
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302 | ia64_mf(void) |
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303 | { |
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304 | __asm __volatile("mf" ::: "memory"); |
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305 | } |
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306 | |
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307 | static __inline void |
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308 | ia64_mf_a(void) |
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309 | { |
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310 | __asm __volatile("mf.a"); |
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311 | } |
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312 | |
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313 | /* |
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314 | * Flush Cache. |
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315 | */ |
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316 | static __inline void |
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317 | ia64_fc(uint64_t va) |
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318 | { |
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319 | __asm __volatile("fc %0" :: "r"(va)); |
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320 | } |
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321 | |
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322 | /* |
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323 | * Sync instruction stream. |
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324 | */ |
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325 | static __inline void |
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326 | ia64_sync_i(void) |
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327 | { |
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328 | __asm __volatile("sync.i"); |
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329 | } |
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330 | |
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331 | /* |
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332 | * Calculate address in VHPT for va. |
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333 | */ |
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334 | static __inline uint64_t |
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335 | ia64_thash(uint64_t va) |
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336 | { |
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337 | uint64_t result; |
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338 | __asm __volatile("thash %0=%1" : "=r" (result) : "r" (va)); |
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339 | return result; |
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340 | } |
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341 | |
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342 | /* |
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343 | * Calculate VHPT tag for va. |
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344 | */ |
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345 | static __inline uint64_t |
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346 | ia64_ttag(uint64_t va) |
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347 | { |
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348 | uint64_t result; |
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349 | __asm __volatile("ttag %0=%1" : "=r" (result) : "r" (va)); |
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350 | return result; |
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351 | } |
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352 | |
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353 | /* |
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354 | * Convert virtual address to physical. |
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355 | */ |
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356 | static __inline uint64_t |
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357 | ia64_tpa(uint64_t va) |
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358 | { |
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359 | uint64_t result; |
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360 | __asm __volatile("tpa %0=%1" : "=r" (result) : "r" (va)); |
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361 | return result; |
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362 | } |
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363 | |
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364 | /* |
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365 | * Generate a ptc.e instruction. |
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366 | */ |
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367 | static __inline void |
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368 | ia64_ptc_e(uint64_t v) |
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369 | { |
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370 | __asm __volatile("ptc.e %0;; srlz.d;;" :: "r"(v)); |
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371 | } |
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372 | |
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373 | /* |
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374 | * Generate a ptc.g instruction. |
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375 | */ |
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376 | static __inline void |
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377 | ia64_ptc_g(uint64_t va, uint64_t size) |
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378 | { |
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379 | __asm __volatile("ptc.g %0,%1;; srlz.d;;" :: "r"(va), "r"(size<<2)); |
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380 | } |
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381 | |
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382 | /* |
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383 | * Generate a ptc.ga instruction. |
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384 | */ |
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385 | static __inline void |
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386 | ia64_ptc_ga(uint64_t va, uint64_t size) |
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387 | { |
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388 | __asm __volatile("ptc.ga %0,%1;; srlz.d;;" :: "r"(va), "r"(size<<2)); |
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389 | } |
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390 | |
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391 | /* |
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392 | * Generate a ptc.l instruction. |
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393 | */ |
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394 | static __inline void |
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395 | ia64_ptc_l(uint64_t va, uint64_t size) |
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396 | { |
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397 | __asm __volatile("ptc.l %0,%1;; srlz.d;;" :: "r"(va), "r"(size<<2)); |
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398 | } |
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399 | |
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400 | /* |
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401 | * Read the value of psr. |
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402 | */ |
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403 | static __inline uint64_t |
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404 | ia64_get_psr(void) |
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405 | { |
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406 | uint64_t result; |
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407 | __asm __volatile("mov %0=psr;;" : "=r" (result)); |
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408 | return result; |
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409 | } |
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410 | |
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411 | static __inline void |
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412 | ia64_set_psr(uint64_t v) |
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413 | { |
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414 | __asm __volatile("mov psr.l=%0" :: "r" (v)); |
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415 | } |
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416 | |
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417 | static __inline void |
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418 | ia64_srlz_d(void) |
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419 | { |
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420 | __asm __volatile("srlz.d;;"); |
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421 | } |
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422 | |
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423 | static __inline void |
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424 | disable_intr(void) |
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425 | { |
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426 | __asm __volatile ("rsm psr.ic|psr.i"); |
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427 | } |
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428 | |
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429 | static __inline void |
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430 | enable_intr(void) |
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431 | { |
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432 | __asm __volatile ("ssm psr.ic|psr.i"); |
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433 | } |
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434 | |
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435 | /* |
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436 | * Define accessors for application registers. |
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437 | */ |
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438 | |
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439 | #define IA64_AR(name) \ |
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440 | \ |
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441 | static __inline uint64_t \ |
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442 | ia64_get_##name(void) \ |
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443 | { \ |
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444 | uint64_t result; \ |
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445 | __asm __volatile(";;mov %0=ar." #name ";;" : "=r" (result)); \ |
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446 | return result; \ |
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447 | } \ |
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448 | \ |
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449 | static __inline void \ |
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450 | ia64_set_##name(uint64_t v) \ |
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451 | { \ |
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452 | __asm __volatile("mov ar." #name "=%0" :: "r" (v)); \ |
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453 | } |
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454 | |
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455 | IA64_AR(k0) |
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456 | IA64_AR(k1) |
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457 | IA64_AR(k2) |
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458 | IA64_AR(k3) |
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459 | IA64_AR(k4) |
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460 | IA64_AR(k5) |
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461 | IA64_AR(k6) |
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462 | IA64_AR(k7) |
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463 | |
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464 | IA64_AR(rsc) |
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465 | IA64_AR(bsp) |
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466 | IA64_AR(bspstore) |
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467 | IA64_AR(rnat) |
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468 | |
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469 | IA64_AR(fcr) |
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470 | |
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471 | IA64_AR(eflag) |
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472 | IA64_AR(csd) |
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473 | IA64_AR(ssd) |
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474 | IA64_AR(cflg) |
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475 | IA64_AR(fsr) |
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476 | IA64_AR(fir) |
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477 | IA64_AR(fdr) |
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478 | |
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479 | IA64_AR(ccv) |
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480 | |
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481 | IA64_AR(unat) |
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482 | |
---|
483 | IA64_AR(fpsr) |
---|
484 | |
---|
485 | IA64_AR(itc) |
---|
486 | |
---|
487 | IA64_AR(pfs) |
---|
488 | IA64_AR(lc) |
---|
489 | IA64_AR(ec) |
---|
490 | |
---|
491 | /* |
---|
492 | * Define accessors for control registers. |
---|
493 | */ |
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494 | |
---|
495 | #define IA64_CR(name) \ |
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496 | \ |
---|
497 | static __inline uint64_t \ |
---|
498 | ia64_get_##name(void) \ |
---|
499 | { \ |
---|
500 | uint64_t result; \ |
---|
501 | __asm __volatile("mov %0=cr." #name : "=r" (result)); \ |
---|
502 | return result; \ |
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503 | } \ |
---|
504 | \ |
---|
505 | static __inline void \ |
---|
506 | ia64_set_##name(uint64_t v) \ |
---|
507 | { \ |
---|
508 | __asm __volatile("mov cr." #name "=%0" :: "r" (v)); \ |
---|
509 | } |
---|
510 | |
---|
511 | IA64_CR(dcr) |
---|
512 | IA64_CR(itm) |
---|
513 | IA64_CR(iva) |
---|
514 | |
---|
515 | IA64_CR(pta) |
---|
516 | |
---|
517 | IA64_CR(ipsr) |
---|
518 | IA64_CR(isr) |
---|
519 | |
---|
520 | IA64_CR(iip) |
---|
521 | IA64_CR(ifa) |
---|
522 | IA64_CR(itir) |
---|
523 | IA64_CR(iipa) |
---|
524 | IA64_CR(ifs) |
---|
525 | IA64_CR(iim) |
---|
526 | IA64_CR(iha) |
---|
527 | |
---|
528 | IA64_CR(lid) |
---|
529 | IA64_CR(ivr) |
---|
530 | IA64_CR(tpr) |
---|
531 | IA64_CR(eoi) |
---|
532 | IA64_CR(irr0) |
---|
533 | IA64_CR(irr1) |
---|
534 | IA64_CR(irr2) |
---|
535 | IA64_CR(irr3) |
---|
536 | IA64_CR(itv) |
---|
537 | IA64_CR(pmv) |
---|
538 | IA64_CR(cmcv) |
---|
539 | |
---|
540 | IA64_CR(lrr0) |
---|
541 | IA64_CR(lrr1) |
---|
542 | |
---|
543 | #define IA64_GR(name) \ |
---|
544 | \ |
---|
545 | static __inline uint64_t \ |
---|
546 | ia64_get_##name(void) \ |
---|
547 | { \ |
---|
548 | uint64_t result; \ |
---|
549 | __asm __volatile("mov %0=" #name : "=r" (result)); \ |
---|
550 | return result; \ |
---|
551 | } \ |
---|
552 | \ |
---|
553 | static __inline void \ |
---|
554 | ia64_set_##name(uint64_t v) \ |
---|
555 | { \ |
---|
556 | __asm __volatile("mov " #name "=%0" :: "r" (v)); \ |
---|
557 | } |
---|
558 | |
---|
559 | IA64_GR(sp) |
---|
560 | IA64_GR(b0) |
---|
561 | IA64_GR(r13) // tp |
---|
562 | |
---|
563 | |
---|
564 | /* |
---|
565 | * Write a region register. |
---|
566 | */ |
---|
567 | static __inline void |
---|
568 | ia64_set_rr(uint64_t rrbase, uint64_t v) |
---|
569 | { |
---|
570 | __asm __volatile("mov rr[%0]=%1;; srlz.d;;" |
---|
571 | :: "r"(rrbase), "r"(v) : "memory"); |
---|
572 | } |
---|
573 | |
---|
574 | /* |
---|
575 | * Read a region register. |
---|
576 | */ |
---|
577 | static __inline uint64_t |
---|
578 | ia64_get_rr(uint64_t rrbase) |
---|
579 | { |
---|
580 | uint64_t v; |
---|
581 | __asm __volatile("mov %1=rr[%0];;" |
---|
582 | : "=r" (v) : "r"(rrbase) : "memory"); |
---|
583 | return v; |
---|
584 | } |
---|
585 | |
---|
586 | |
---|
587 | /* |
---|
588 | * Read a CPUID register. |
---|
589 | */ |
---|
590 | static __inline uint64_t |
---|
591 | ia64_get_cpuid(int i) |
---|
592 | { |
---|
593 | uint64_t result; |
---|
594 | __asm __volatile("mov %0=cpuid[%1]" |
---|
595 | : "=r" (result) : "r"(i)); |
---|
596 | return result; |
---|
597 | } |
---|
598 | |
---|
599 | |
---|
600 | struct trap_frame |
---|
601 | { |
---|
602 | uint64_t rsc; |
---|
603 | uint64_t ndirty; /* number of dirty regs */ |
---|
604 | uint64_t ssd; |
---|
605 | uint64_t iip; /* interrupted ip */ |
---|
606 | uint64_t ipsr; /* interrupted psr */ |
---|
607 | uint64_t ifs; /* interruption func status register */ |
---|
608 | |
---|
609 | uint16_t trap_num; /* Trap num, index in trap_vec */ |
---|
610 | uint64_t cfm; /* current frame marker */ |
---|
611 | uint64_t pfs; /* previous function state ar64 */ |
---|
612 | uint64_t bsp; /* backing store pointer ar17 */ |
---|
613 | uint64_t rnat; /* rse nat collection ar19 */ |
---|
614 | uint64_t csd; /* comp and store data reg ar25 */ |
---|
615 | uint64_t ccv; /* comp and xchange val reg ar32 */ |
---|
616 | uint64_t unat; /* */ |
---|
617 | uint64_t fpsr; /* floating point state reg ar40 */ |
---|
618 | uint64_t pr; /* predicate regs 0-63 */ |
---|
619 | |
---|
620 | uint64_t gp; /* the gp pointer */ |
---|
621 | uint64_t sp; /* stack pointer */ |
---|
622 | uint64_t tp; /* thread pointer */ |
---|
623 | |
---|
624 | uint64_t r2; /* global reg 2 */ |
---|
625 | uint64_t r3; |
---|
626 | uint64_t r8; |
---|
627 | uint64_t r9; |
---|
628 | uint64_t r10; |
---|
629 | uint64_t r11; |
---|
630 | uint64_t r14; |
---|
631 | uint64_t r15; |
---|
632 | uint64_t r16; |
---|
633 | uint64_t r17; |
---|
634 | uint64_t r18; |
---|
635 | uint64_t r19; |
---|
636 | uint64_t r20; |
---|
637 | uint64_t r21; |
---|
638 | uint64_t r22; |
---|
639 | uint64_t r23; |
---|
640 | uint64_t r24; |
---|
641 | uint64_t r25; |
---|
642 | uint64_t r26; |
---|
643 | uint64_t r27; |
---|
644 | uint64_t r28; |
---|
645 | uint64_t r29; |
---|
646 | uint64_t r30; |
---|
647 | uint64_t r31; |
---|
648 | |
---|
649 | uint64_t b0; |
---|
650 | uint64_t b6; |
---|
651 | uint64_t b7; |
---|
652 | |
---|
653 | ia64_fpreg_t f6; /* floating point register 6 */ |
---|
654 | ia64_fpreg_t f7; |
---|
655 | ia64_fpreg_t f8; |
---|
656 | ia64_fpreg_t f9; |
---|
657 | ia64_fpreg_t f10; |
---|
658 | ia64_fpreg_t f11; |
---|
659 | |
---|
660 | uint64_t ifa; /* interruption faulting address */ |
---|
661 | uint64_t isr; /* interruption status register */ |
---|
662 | uint64_t iim; /* interruption immediate register */ |
---|
663 | }; |
---|
664 | |
---|
665 | typedef struct trap_frame trap_frame_t; |
---|
666 | |
---|
667 | |
---|
668 | #endif /* __ASSEMBLY__ */ |
---|
669 | |
---|
670 | /* Page access parameters. */ |
---|
671 | #define PTE_P_SHIFT 0 |
---|
672 | #define PTE_P 1 |
---|
673 | |
---|
674 | #define PTE_MA_SHIFT 2 |
---|
675 | #define PTE_MA_WB 0 |
---|
676 | |
---|
677 | #define PTE_A_SHIFT 5 |
---|
678 | #define PTE_A 1 |
---|
679 | #define PTE_D_SHIFT 6 |
---|
680 | #define PTE_D 1 |
---|
681 | |
---|
682 | #define PTE_AR_SHIFT 9 |
---|
683 | #define PTE_AR_R 0 |
---|
684 | #define PTE_AR_RX 1 |
---|
685 | #define PTE_AR_RW 2 |
---|
686 | #define PTE_AR_RWX 3 |
---|
687 | #define PTE_AR_R_RW 4 |
---|
688 | #define PTE_AR_RX_RWX 5 |
---|
689 | #define PTE_AR_RWX_RW 6 |
---|
690 | /* privilege level */ |
---|
691 | #define PTE_PL_SHIFT 7 |
---|
692 | #define PTE_PL_KERN 0 /* used for kernel */ |
---|
693 | /* page size */ |
---|
694 | #define PTE_PS_4K 12 |
---|
695 | #define PTE_PS_8K 13 |
---|
696 | #define PTE_PS_16K 14 |
---|
697 | #define PTE_PS_64K 16 |
---|
698 | #define PTE_PS_256K 18 |
---|
699 | #define PTE_PS_1M 20 |
---|
700 | #define PTE_PS_4M 22 |
---|
701 | #define PTE_PS_16M 24 |
---|
702 | #define PTE_PS_64M 26 |
---|
703 | #define PTE_PS_256M 28 |
---|
704 | |
---|
705 | |
---|
706 | /* Some offsets for ia64_pte_t. */ |
---|
707 | #define PTE_OFF_P 0 |
---|
708 | #define PTE_OFF_MA 3 |
---|
709 | #define PTE_OFF_A 5 |
---|
710 | #define PTE_OFF_D 6 |
---|
711 | #define PTE_OFF_PL 7 |
---|
712 | #define PTE_OFF_AR 9 |
---|
713 | #define PTE_OFF_PPN 12 |
---|
714 | #define PTE_OFF_ED 52 |
---|
715 | |
---|
716 | #if !defined(_ASM) && !defined(__ASSEMBLY__) |
---|
717 | /* |
---|
718 | * A short-format VHPT entry. Also matches the TLB insertion format. |
---|
719 | */ |
---|
720 | typedef struct |
---|
721 | { |
---|
722 | #if defined(BIG_ENDIAN) |
---|
723 | uint64_t pte_ig :11; /* bits 53..63 */ |
---|
724 | uint64_t pte_ed :1; /* bits 52..52 */ |
---|
725 | uint64_t pte_rv2:2; /* bits 50..51 */ |
---|
726 | uint64_t pte_ppn:38; /* bits 12..49 */ |
---|
727 | uint64_t pte_ar :3; /* bits 9..11 */ |
---|
728 | uint64_t pte_pl :2; /* bits 7..8 */ |
---|
729 | uint64_t pte_d :1; /* bits 6..6 */ |
---|
730 | uint64_t pte_a :1; /* bits 5..5 */ |
---|
731 | uint64_t pte_ma :3; /* bits 2..4 */ |
---|
732 | uint64_t pte_rv1:1; /* bits 1..1 */ |
---|
733 | uint64_t pte_p :1; /* bits 0..0 */ |
---|
734 | #else |
---|
735 | uint64_t pte_p :1; /* bits 0..0 */ |
---|
736 | uint64_t pte_rv1:1; /* bits 1..1 */ |
---|
737 | uint64_t pte_ma :3; /* bits 2..4 */ |
---|
738 | uint64_t pte_a :1; /* bits 5..5 */ |
---|
739 | uint64_t pte_d :1; /* bits 6..6 */ |
---|
740 | uint64_t pte_pl :2; /* bits 7..8 */ |
---|
741 | uint64_t pte_ar :3; /* bits 9..11 */ |
---|
742 | uint64_t pte_ppn:38; /* bits 12..49 */ |
---|
743 | uint64_t pte_rv2:2; /* bits 50..51 */ |
---|
744 | uint64_t pte_ed :1; /* bits 52..52 */ |
---|
745 | uint64_t pte_ig :11; /* bits 53..63 */ |
---|
746 | #endif |
---|
747 | } ia64_pte_t; |
---|
748 | |
---|
749 | |
---|
750 | /* |
---|
751 | * A long-format VHPT entry. |
---|
752 | */ |
---|
753 | typedef struct |
---|
754 | { |
---|
755 | uint64_t pte_p :1; /* bits 0..0 */ |
---|
756 | uint64_t pte_rv1 :1; /* bits 1..1 */ |
---|
757 | uint64_t pte_ma :3; /* bits 2..4 */ |
---|
758 | uint64_t pte_a :1; /* bits 5..5 */ |
---|
759 | uint64_t pte_d :1; /* bits 6..6 */ |
---|
760 | uint64_t pte_pl :2; /* bits 7..8 */ |
---|
761 | uint64_t pte_ar :3; /* bits 9..11 */ |
---|
762 | uint64_t pte_ppn :38; /* bits 12..49 */ |
---|
763 | uint64_t pte_rv2 :2; /* bits 50..51 */ |
---|
764 | uint64_t pte_ed :1; /* bits 52..52 */ |
---|
765 | uint64_t pte_ig :11; /* bits 53..63 */ |
---|
766 | uint64_t pte_rv3 :2; /* bits 0..1 */ |
---|
767 | uint64_t pte_ps :6; /* bits 2..7 */ |
---|
768 | uint64_t pte_key :24; /* bits 8..31 */ |
---|
769 | uint64_t pte_rv4 :32; /* bits 32..63 */ |
---|
770 | uint64_t pte_tag; /* includes ti */ |
---|
771 | uint64_t pte_chain; /* pa of collision chain */ |
---|
772 | } ia64_lpte_t; |
---|
773 | |
---|
774 | #endif /* __ASSEMBLY__ */ |
---|
775 | |
---|
776 | #endif /* _IA64_CPU_H_ */ |
---|