[34] | 1 | /****************************************************************************** |
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| 2 | * hypervisor.c |
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| 3 | * |
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| 4 | * Communication to/from hypervisor. |
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| 5 | * |
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| 6 | * Copyright (c) 2002-2003, K A Fraser |
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| 7 | * Copyright (c) 2005, Grzegorz Milos, gm281@cam.ac.uk,Intel Research Cambridge |
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| 8 | * |
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| 9 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
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| 10 | * of this software and associated documentation files (the "Software"), to |
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| 11 | * deal in the Software without restriction, including without limitation the |
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| 12 | * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or |
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| 13 | * sell copies of the Software, and to permit persons to whom the Software is |
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| 14 | * furnished to do so, subject to the following conditions: |
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| 15 | * |
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| 16 | * The above copyright notice and this permission notice shall be included in |
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| 17 | * all copies or substantial portions of the Software. |
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| 18 | * |
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| 19 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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| 20 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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| 21 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE |
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| 22 | * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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| 23 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
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| 24 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
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| 25 | * DEALINGS IN THE SOFTWARE. |
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| 26 | */ |
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| 27 | |
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| 28 | #include <os.h> |
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| 29 | #include <hypervisor.h> |
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| 30 | #include <events.h> |
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| 31 | |
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| 32 | #define active_evtchns(cpu,sh,idx) \ |
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| 33 | ((sh)->evtchn_pending[idx] & \ |
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| 34 | ~(sh)->evtchn_mask[idx]) |
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| 35 | |
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| 36 | void do_hypervisor_callback(struct pt_regs *regs) |
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| 37 | { |
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| 38 | unsigned long l1, l2, l1i, l2i; |
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| 39 | unsigned int port; |
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| 40 | int cpu = 0; |
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| 41 | shared_info_t *s = HYPERVISOR_shared_info; |
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| 42 | vcpu_info_t *vcpu_info = &s->vcpu_info[cpu]; |
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| 43 | |
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| 44 | |
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| 45 | vcpu_info->evtchn_upcall_pending = 0; |
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| 46 | /* NB. No need for a barrier here -- XCHG is a barrier on x86. */ |
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| 47 | l1 = xchg(&vcpu_info->evtchn_pending_sel, 0); |
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| 48 | while ( l1 != 0 ) |
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| 49 | { |
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| 50 | l1i = __ffs(l1); |
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| 51 | l1 &= ~(1 << l1i); |
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| 52 | |
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| 53 | while ( (l2 = active_evtchns(cpu, s, l1i)) != 0 ) |
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| 54 | { |
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| 55 | l2i = __ffs(l2); |
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| 56 | l2 &= ~(1 << l2i); |
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| 57 | |
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| 58 | port = (l1i << 5) + l2i; |
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| 59 | do_event(port, regs); |
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| 60 | } |
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| 61 | } |
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| 62 | } |
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| 63 | |
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| 64 | |
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| 65 | inline void mask_evtchn(u32 port) |
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| 66 | { |
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| 67 | shared_info_t *s = HYPERVISOR_shared_info; |
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| 68 | synch_set_bit(port, &s->evtchn_mask[0]); |
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| 69 | } |
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| 70 | |
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| 71 | inline void unmask_evtchn(u32 port) |
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| 72 | { |
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| 73 | shared_info_t *s = HYPERVISOR_shared_info; |
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| 74 | vcpu_info_t *vcpu_info = &s->vcpu_info[smp_processor_id()]; |
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| 75 | |
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| 76 | synch_clear_bit(port, &s->evtchn_mask[0]); |
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| 77 | |
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| 78 | /* |
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| 79 | * The following is basically the equivalent of 'hw_resend_irq'. Just like |
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| 80 | * a real IO-APIC we 'lose the interrupt edge' if the channel is masked. |
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| 81 | */ |
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| 82 | if ( synch_test_bit (port, &s->evtchn_pending[0]) && |
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| 83 | !synch_test_and_set_bit(port>>5, &vcpu_info->evtchn_pending_sel) ) |
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| 84 | { |
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| 85 | vcpu_info->evtchn_upcall_pending = 1; |
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| 86 | if ( !vcpu_info->evtchn_upcall_mask ) |
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| 87 | force_evtchn_callback(); |
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| 88 | } |
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| 89 | } |
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| 90 | |
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| 91 | inline void clear_evtchn(u32 port) |
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| 92 | { |
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| 93 | shared_info_t *s = HYPERVISOR_shared_info; |
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| 94 | synch_clear_bit(port, &s->evtchn_pending[0]); |
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| 95 | } |
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